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v_deinterlacer: Add multiple samples per clock support

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IP updated to add multiple pixels per clock support resulting in
API changes in driver.

Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Reviewed-by: Andrei Simion <andreis@xilinx.com>
This commit is contained in:
Rohit Consul 2015-07-31 13:47:38 -07:00 • committed by Nava kishore Manne
parent 7ab5756f84
commit 533b4d0587
5 changed files with 122 additions and 27 deletions
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34
XilinxProcessorIPLib/drivers/v_deinterlacer/data/v_deinterlacer.mdd
View file

@ -1,9 +1,33 @@
# ==============================================================
# File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
# Version: 2015.1
# Copyright (C) 2015 Xilinx Inc. All rights reserved.
##############################################################################
#
# ==============================================================
# Copyright (C) 2015 Xilinx, Inc. All rights reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"),to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
#
# Use of the Software is limited solely to applications:
# (a) running on a Xilinx device, or
# (b) that interact with a Xilinx device through a bus or interconnect.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
# XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
# IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
#
# Except as contained in this notice, the name of the Xilinx shall not be used
# in advertising or otherwise to promote the sale, use or other dealings in
# this Software without prior written authorization from Xilinx.
###############################################################################
OPTION psf_version = 2.1;

2
XilinxProcessorIPLib/drivers/v_deinterlacer/src/Makefile
View file

@ -1,6 +1,6 @@
# ==============================================================
# File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
# Version: 2015.1
# Version: 2015.3
# Copyright (C) 2015 Xilinx Inc. All rights reserved.
#
# ==============================================================

49
XilinxProcessorIPLib/drivers/v_deinterlacer/src/xv_deinterlacer.c
View file

@ -87,6 +87,39 @@ void XV_deinterlacer_DisableAutoRestart(XV_deinterlacer *InstancePtr) {
XV_deinterlacer_WriteReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_AP_CTRL, 0);
}
void XV_deinterlacer_Set_width(XV_deinterlacer *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_deinterlacer_WriteReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_WIDTH_DATA, Data);
}
u32 XV_deinterlacer_Get_width(XV_deinterlacer *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_deinterlacer_ReadReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_WIDTH_DATA);
return Data;
}
void XV_deinterlacer_Set_height(XV_deinterlacer *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_deinterlacer_WriteReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_HEIGHT_DATA, Data);
}
u32 XV_deinterlacer_Get_height(XV_deinterlacer *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_deinterlacer_ReadReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_HEIGHT_DATA);
return Data;
}
void XV_deinterlacer_Set_read_fb(XV_deinterlacer *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
@ -155,6 +188,22 @@ u32 XV_deinterlacer_Get_algo(XV_deinterlacer *InstancePtr) {
return Data;
}
void XV_deinterlacer_Set_invert_field_id(XV_deinterlacer *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_deinterlacer_WriteReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_INVERT_FIELD_ID_DATA, Data);
}
u32 XV_deinterlacer_Get_invert_field_id(XV_deinterlacer *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_deinterlacer_ReadReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_INVERT_FIELD_ID_DATA);
return Data;
}
void XV_deinterlacer_InterruptGlobalEnable(XV_deinterlacer *InstancePtr) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

6
XilinxProcessorIPLib/drivers/v_deinterlacer/src/xv_deinterlacer.h
View file

@ -99,6 +99,10 @@ u32 XV_deinterlacer_IsReady(XV_deinterlacer *InstancePtr);
void XV_deinterlacer_EnableAutoRestart(XV_deinterlacer *InstancePtr);
void XV_deinterlacer_DisableAutoRestart(XV_deinterlacer *InstancePtr);
void XV_deinterlacer_Set_width(XV_deinterlacer *InstancePtr, u32 Data);
u32 XV_deinterlacer_Get_width(XV_deinterlacer *InstancePtr);
void XV_deinterlacer_Set_height(XV_deinterlacer *InstancePtr, u32 Data);
u32 XV_deinterlacer_Get_height(XV_deinterlacer *InstancePtr);
void XV_deinterlacer_Set_read_fb(XV_deinterlacer *InstancePtr, u32 Data);
u32 XV_deinterlacer_Get_read_fb(XV_deinterlacer *InstancePtr);
void XV_deinterlacer_Set_write_fb(XV_deinterlacer *InstancePtr, u32 Data);
@ -107,6 +111,8 @@ void XV_deinterlacer_Set_colorFormat(XV_deinterlacer *InstancePtr, u32 Data);
u32 XV_deinterlacer_Get_colorFormat(XV_deinterlacer *InstancePtr);
void XV_deinterlacer_Set_algo(XV_deinterlacer *InstancePtr, u32 Data);
u32 XV_deinterlacer_Get_algo(XV_deinterlacer *InstancePtr);
void XV_deinterlacer_Set_invert_field_id(XV_deinterlacer *InstancePtr, u32 Data);
u32 XV_deinterlacer_Get_invert_field_id(XV_deinterlacer *InstancePtr);
void XV_deinterlacer_InterruptGlobalEnable(XV_deinterlacer *InstancePtr);
void XV_deinterlacer_InterruptGlobalDisable(XV_deinterlacer *InstancePtr);

58
XilinxProcessorIPLib/drivers/v_deinterlacer/src/xv_deinterlacer_hw.h
View file

@ -1,6 +1,6 @@
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.1
// Version: 2015.3
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
@ -24,31 +24,47 @@
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// 0x10 : Data signal of read_fb
// bit 31~0 - read_fb[31:0] (Read/Write)
// 0x10 : Data signal of width
// bit 31~0 - width[31:0] (Read/Write)
// 0x14 : reserved
// 0x18 : Data signal of write_fb
// bit 31~0 - write_fb[31:0] (Read/Write)
// 0x18 : Data signal of height
// bit 31~0 - height[31:0] (Read/Write)
// 0x1c : reserved
// 0x20 : Data signal of colorFormat
// 0x20 : Data signal of read_fb
// bit 31~0 - read_fb[31:0] (Read/Write)
// 0x24 : reserved
// 0x28 : Data signal of write_fb
// bit 31~0 - write_fb[31:0] (Read/Write)
// 0x2c : reserved
// 0x30 : Data signal of colorFormat
// bit 7~0 - colorFormat[7:0] (Read/Write)
// others - reserved
// 0x24 : reserved
// 0x28 : Data signal of algo
// 0x34 : reserved
// 0x38 : Data signal of algo
// bit 7~0 - algo[7:0] (Read/Write)
// others - reserved
// 0x2c : reserved
// 0x3c : reserved
// 0x40 : Data signal of invert_field_id
// bit 0 - invert_field_id[0] (Read/Write)
// others - reserved
// 0x44 : reserved
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
#define XV_DEINTERLACER_AXILITES_ADDR_AP_CTRL 0x00
#define XV_DEINTERLACER_AXILITES_ADDR_GIE 0x04
#define XV_DEINTERLACER_AXILITES_ADDR_IER 0x08
#define XV_DEINTERLACER_AXILITES_ADDR_ISR 0x0c
#define XV_DEINTERLACER_AXILITES_ADDR_READ_FB_DATA 0x10
#define XV_DEINTERLACER_AXILITES_BITS_READ_FB_DATA 32
#define XV_DEINTERLACER_AXILITES_ADDR_WRITE_FB_DATA 0x18
#define XV_DEINTERLACER_AXILITES_BITS_WRITE_FB_DATA 32
#define XV_DEINTERLACER_AXILITES_ADDR_COLORFORMAT_DATA 0x20
#define XV_DEINTERLACER_AXILITES_BITS_COLORFORMAT_DATA 8
#define XV_DEINTERLACER_AXILITES_ADDR_ALGO_DATA 0x28
#define XV_DEINTERLACER_AXILITES_BITS_ALGO_DATA 8
#define XV_DEINTERLACER_AXILITES_ADDR_AP_CTRL 0x00
#define XV_DEINTERLACER_AXILITES_ADDR_GIE 0x04
#define XV_DEINTERLACER_AXILITES_ADDR_IER 0x08
#define XV_DEINTERLACER_AXILITES_ADDR_ISR 0x0c
#define XV_DEINTERLACER_AXILITES_ADDR_WIDTH_DATA 0x10
#define XV_DEINTERLACER_AXILITES_BITS_WIDTH_DATA 32
#define XV_DEINTERLACER_AXILITES_ADDR_HEIGHT_DATA 0x18
#define XV_DEINTERLACER_AXILITES_BITS_HEIGHT_DATA 32
#define XV_DEINTERLACER_AXILITES_ADDR_READ_FB_DATA 0x20
#define XV_DEINTERLACER_AXILITES_BITS_READ_FB_DATA 32
#define XV_DEINTERLACER_AXILITES_ADDR_WRITE_FB_DATA 0x28
#define XV_DEINTERLACER_AXILITES_BITS_WRITE_FB_DATA 32
#define XV_DEINTERLACER_AXILITES_ADDR_COLORFORMAT_DATA 0x30
#define XV_DEINTERLACER_AXILITES_BITS_COLORFORMAT_DATA 8
#define XV_DEINTERLACER_AXILITES_ADDR_ALGO_DATA 0x38
#define XV_DEINTERLACER_AXILITES_BITS_ALGO_DATA 8
#define XV_DEINTERLACER_AXILITES_ADDR_INVERT_FIELD_ID_DATA 0x40
#define XV_DEINTERLACER_AXILITES_BITS_INVERT_FIELD_ID_DATA 1