v_deinterlacer: Add multiple samples per clock support
IP updated to add multiple pixels per clock support resulting in API changes in driver. Signed-off-by: Rohit Consul <rohit.consul@xilinx.com> Reviewed-by: Andrei Simion <andreis@xilinx.com>
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5 changed files with 122 additions and 27 deletions
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@ -1,9 +1,33 @@
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# ==============================================================
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# File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
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# Version: 2015.1
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# Copyright (C) 2015 Xilinx Inc. All rights reserved.
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##############################################################################
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#
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# ==============================================================
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# Copyright (C) 2015 Xilinx, Inc. All rights reserved.
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#
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# Permission is hereby granted, free of charge, to any person obtaining a copy
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# of this software and associated documentation files (the "Software"),to deal
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# in the Software without restriction, including without limitation the rights
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# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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# copies of the Software, and to permit persons to whom the Software is
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# furnished to do so, subject to the following conditions:
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#
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# The above copyright notice and this permission notice shall be included in
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# all copies or substantial portions of the Software.
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#
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# Use of the Software is limited solely to applications:
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# (a) running on a Xilinx device, or
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# (b) that interact with a Xilinx device through a bus or interconnect.
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#
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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# XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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# IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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# SOFTWARE.
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#
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# Except as contained in this notice, the name of the Xilinx shall not be used
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# in advertising or otherwise to promote the sale, use or other dealings in
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# this Software without prior written authorization from Xilinx.
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###############################################################################
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OPTION psf_version = 2.1;
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@ -1,6 +1,6 @@
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# ==============================================================
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# File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
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# Version: 2015.1
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# Version: 2015.3
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# Copyright (C) 2015 Xilinx Inc. All rights reserved.
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#
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# ==============================================================
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@ -87,6 +87,39 @@ void XV_deinterlacer_DisableAutoRestart(XV_deinterlacer *InstancePtr) {
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XV_deinterlacer_WriteReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_AP_CTRL, 0);
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}
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void XV_deinterlacer_Set_width(XV_deinterlacer *InstancePtr, u32 Data) {
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Xil_AssertVoid(InstancePtr != NULL);
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Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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XV_deinterlacer_WriteReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_WIDTH_DATA, Data);
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}
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u32 XV_deinterlacer_Get_width(XV_deinterlacer *InstancePtr) {
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u32 Data;
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Xil_AssertNonvoid(InstancePtr != NULL);
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Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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Data = XV_deinterlacer_ReadReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_WIDTH_DATA);
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return Data;
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}
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void XV_deinterlacer_Set_height(XV_deinterlacer *InstancePtr, u32 Data) {
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Xil_AssertVoid(InstancePtr != NULL);
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Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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XV_deinterlacer_WriteReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_HEIGHT_DATA, Data);
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}
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u32 XV_deinterlacer_Get_height(XV_deinterlacer *InstancePtr) {
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u32 Data;
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Xil_AssertNonvoid(InstancePtr != NULL);
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Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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Data = XV_deinterlacer_ReadReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_HEIGHT_DATA);
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return Data;
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}
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void XV_deinterlacer_Set_read_fb(XV_deinterlacer *InstancePtr, u32 Data) {
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Xil_AssertVoid(InstancePtr != NULL);
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Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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@ -155,6 +188,22 @@ u32 XV_deinterlacer_Get_algo(XV_deinterlacer *InstancePtr) {
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return Data;
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}
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void XV_deinterlacer_Set_invert_field_id(XV_deinterlacer *InstancePtr, u32 Data) {
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Xil_AssertVoid(InstancePtr != NULL);
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Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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XV_deinterlacer_WriteReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_INVERT_FIELD_ID_DATA, Data);
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}
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u32 XV_deinterlacer_Get_invert_field_id(XV_deinterlacer *InstancePtr) {
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u32 Data;
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Xil_AssertNonvoid(InstancePtr != NULL);
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Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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Data = XV_deinterlacer_ReadReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_INVERT_FIELD_ID_DATA);
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return Data;
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}
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void XV_deinterlacer_InterruptGlobalEnable(XV_deinterlacer *InstancePtr) {
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Xil_AssertVoid(InstancePtr != NULL);
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Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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@ -99,6 +99,10 @@ u32 XV_deinterlacer_IsReady(XV_deinterlacer *InstancePtr);
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void XV_deinterlacer_EnableAutoRestart(XV_deinterlacer *InstancePtr);
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void XV_deinterlacer_DisableAutoRestart(XV_deinterlacer *InstancePtr);
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void XV_deinterlacer_Set_width(XV_deinterlacer *InstancePtr, u32 Data);
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u32 XV_deinterlacer_Get_width(XV_deinterlacer *InstancePtr);
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void XV_deinterlacer_Set_height(XV_deinterlacer *InstancePtr, u32 Data);
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u32 XV_deinterlacer_Get_height(XV_deinterlacer *InstancePtr);
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void XV_deinterlacer_Set_read_fb(XV_deinterlacer *InstancePtr, u32 Data);
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u32 XV_deinterlacer_Get_read_fb(XV_deinterlacer *InstancePtr);
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void XV_deinterlacer_Set_write_fb(XV_deinterlacer *InstancePtr, u32 Data);
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u32 XV_deinterlacer_Get_colorFormat(XV_deinterlacer *InstancePtr);
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void XV_deinterlacer_Set_algo(XV_deinterlacer *InstancePtr, u32 Data);
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u32 XV_deinterlacer_Get_algo(XV_deinterlacer *InstancePtr);
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void XV_deinterlacer_Set_invert_field_id(XV_deinterlacer *InstancePtr, u32 Data);
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u32 XV_deinterlacer_Get_invert_field_id(XV_deinterlacer *InstancePtr);
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void XV_deinterlacer_InterruptGlobalEnable(XV_deinterlacer *InstancePtr);
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void XV_deinterlacer_InterruptGlobalDisable(XV_deinterlacer *InstancePtr);
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// ==============================================================
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// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
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// Version: 2015.1
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// Version: 2015.3
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// Copyright (C) 2015 Xilinx Inc. All rights reserved.
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//
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// ==============================================================
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// bit 0 - Channel 0 (ap_done)
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// bit 1 - Channel 1 (ap_ready)
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// others - reserved
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// 0x10 : Data signal of read_fb
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// bit 31~0 - read_fb[31:0] (Read/Write)
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// 0x10 : Data signal of width
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// bit 31~0 - width[31:0] (Read/Write)
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// 0x14 : reserved
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// 0x18 : Data signal of write_fb
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// bit 31~0 - write_fb[31:0] (Read/Write)
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// 0x18 : Data signal of height
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// bit 31~0 - height[31:0] (Read/Write)
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// 0x1c : reserved
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// 0x20 : Data signal of colorFormat
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// 0x20 : Data signal of read_fb
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// bit 31~0 - read_fb[31:0] (Read/Write)
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// 0x24 : reserved
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// 0x28 : Data signal of write_fb
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// bit 31~0 - write_fb[31:0] (Read/Write)
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// 0x2c : reserved
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// 0x30 : Data signal of colorFormat
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// bit 7~0 - colorFormat[7:0] (Read/Write)
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// others - reserved
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// 0x24 : reserved
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// 0x28 : Data signal of algo
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// 0x34 : reserved
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// 0x38 : Data signal of algo
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// bit 7~0 - algo[7:0] (Read/Write)
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// others - reserved
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// 0x2c : reserved
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// 0x3c : reserved
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// 0x40 : Data signal of invert_field_id
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// bit 0 - invert_field_id[0] (Read/Write)
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// others - reserved
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// 0x44 : reserved
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// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
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#define XV_DEINTERLACER_AXILITES_ADDR_AP_CTRL 0x00
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#define XV_DEINTERLACER_AXILITES_ADDR_GIE 0x04
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#define XV_DEINTERLACER_AXILITES_ADDR_IER 0x08
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#define XV_DEINTERLACER_AXILITES_ADDR_ISR 0x0c
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#define XV_DEINTERLACER_AXILITES_ADDR_READ_FB_DATA 0x10
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#define XV_DEINTERLACER_AXILITES_BITS_READ_FB_DATA 32
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#define XV_DEINTERLACER_AXILITES_ADDR_WRITE_FB_DATA 0x18
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#define XV_DEINTERLACER_AXILITES_BITS_WRITE_FB_DATA 32
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#define XV_DEINTERLACER_AXILITES_ADDR_COLORFORMAT_DATA 0x20
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#define XV_DEINTERLACER_AXILITES_BITS_COLORFORMAT_DATA 8
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#define XV_DEINTERLACER_AXILITES_ADDR_ALGO_DATA 0x28
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#define XV_DEINTERLACER_AXILITES_BITS_ALGO_DATA 8
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#define XV_DEINTERLACER_AXILITES_ADDR_AP_CTRL 0x00
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#define XV_DEINTERLACER_AXILITES_ADDR_GIE 0x04
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#define XV_DEINTERLACER_AXILITES_ADDR_IER 0x08
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#define XV_DEINTERLACER_AXILITES_ADDR_ISR 0x0c
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#define XV_DEINTERLACER_AXILITES_ADDR_WIDTH_DATA 0x10
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#define XV_DEINTERLACER_AXILITES_BITS_WIDTH_DATA 32
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#define XV_DEINTERLACER_AXILITES_ADDR_HEIGHT_DATA 0x18
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#define XV_DEINTERLACER_AXILITES_BITS_HEIGHT_DATA 32
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#define XV_DEINTERLACER_AXILITES_ADDR_READ_FB_DATA 0x20
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#define XV_DEINTERLACER_AXILITES_BITS_READ_FB_DATA 32
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#define XV_DEINTERLACER_AXILITES_ADDR_WRITE_FB_DATA 0x28
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#define XV_DEINTERLACER_AXILITES_BITS_WRITE_FB_DATA 32
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#define XV_DEINTERLACER_AXILITES_ADDR_COLORFORMAT_DATA 0x30
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#define XV_DEINTERLACER_AXILITES_BITS_COLORFORMAT_DATA 8
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#define XV_DEINTERLACER_AXILITES_ADDR_ALGO_DATA 0x38
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#define XV_DEINTERLACER_AXILITES_BITS_ALGO_DATA 8
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#define XV_DEINTERLACER_AXILITES_ADDR_INVERT_FIELD_ID_DATA 0x40
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#define XV_DEINTERLACER_AXILITES_BITS_INVERT_FIELD_ID_DATA 1
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