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gpiops: Added gpiops driver supports for Zynq and Zynq Ultrascale MP

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This patch modified source code with Misra c guidline

Signed-off-by: Om Mishra <omprakas@xilinx.com>
This commit is contained in:
Om Mishra 2014-12-31 16:12:16 +05:30 • committed by Nava kishore Manne
parent b00f16f481
commit 58b9762523
8 changed files with 251 additions and 237 deletions
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148
XilinxProcessorIPLib/drivers/gpiops/src/xgpiops.c
View file

@ -65,20 +65,10 @@
/************************** Variable Definitions *****************************/ /************************** Variable Definitions *****************************/
/*
* This structure defines the mapping of the pin numbers to the banks when
* the driver APIs are used for working on the individual pins.
*/
unsigned int XGpioPsPinTable[] = {
31, /* 0 - 31, Bank 0 */
53, /* 32 - 53, Bank 1 */
85, /* 54 - 85, Bank 2 */
117 /* 86 - 117 Bank 3 */
};
/************************** Function Prototypes ******************************/ /************************** Function Prototypes ******************************/
extern void StubHandler(void *CallBackRef, int Bank, u32 Status); extern void StubHandler(void *CallBackRef, u32 Bank, u32 Status);
/*****************************************************************************/ /*****************************************************************************/
/* /*
@ -100,18 +90,18 @@ extern void StubHandler(void *CallBackRef, int Bank, u32 Status);
* @note None. * @note None.
* *
******************************************************************************/ ******************************************************************************/
int XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr, s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr,
u32 EffectiveAddr) u32 EffectiveAddr)
{ {
s32 Status = XST_SUCCESS;
Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(ConfigPtr != NULL); Xil_AssertNonvoid(ConfigPtr != NULL);
Xil_AssertNonvoid(EffectiveAddr != (u32)0);
/* /*
* Set some default values for instance data, don't indicate the device * Set some default values for instance data, don't indicate the device
* is ready to use until everything has been initialized successfully. * is ready to use until everything has been initialized successfully.
*/ */
InstancePtr->IsReady = 0; InstancePtr->IsReady = 0U;
InstancePtr->GpioConfig.BaseAddr = EffectiveAddr; InstancePtr->GpioConfig.BaseAddr = EffectiveAddr;
InstancePtr->GpioConfig.DeviceId = ConfigPtr->DeviceId; InstancePtr->GpioConfig.DeviceId = ConfigPtr->DeviceId;
InstancePtr->Handler = StubHandler; InstancePtr->Handler = StubHandler;
@ -121,26 +111,26 @@ int XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr,
* interrupts for all pins in all the 4 banks. * interrupts for all pins in all the 4 banks.
*/ */
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFF); XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFFU);
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((1) * XGPIOPS_REG_MASK_OFFSET) + ((u32)(1) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFF); XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFFU);
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((2) * XGPIOPS_REG_MASK_OFFSET) + ((u32)(2) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFF); XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFFU);
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((3) * XGPIOPS_REG_MASK_OFFSET) + ((u32)(3) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFF); XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFFU);
/* /*
* Indicate the component is now ready to use. * Indicate the component is now ready to use.
*/ */
InstancePtr->IsReady = XIL_COMPONENT_IS_READY; InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
return XST_SUCCESS; return Status;
} }
/****************************************************************************/ /****************************************************************************/
@ -165,7 +155,7 @@ u32 XGpioPs_Read(XGpioPs *InstancePtr, u8 Bank)
Xil_AssertNonvoid(Bank < XGPIOPS_MAX_BANKS); Xil_AssertNonvoid(Bank < XGPIOPS_MAX_BANKS);
return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_DATA_BANK_OFFSET) + ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
XGPIOPS_DATA_RO_OFFSET); XGPIOPS_DATA_RO_OFFSET);
} }
@ -185,7 +175,7 @@ u32 XGpioPs_Read(XGpioPs *InstancePtr, u8 Bank)
* GPIO pin. * GPIO pin.
* *
*****************************************************************************/ *****************************************************************************/
int XGpioPs_ReadPin(XGpioPs *InstancePtr, int Pin) u32 XGpioPs_ReadPin(XGpioPs *InstancePtr, u32 Pin)
{ {
u8 Bank; u8 Bank;
u8 PinNumber; u8 PinNumber;
@ -197,11 +187,11 @@ int XGpioPs_ReadPin(XGpioPs *InstancePtr, int Pin)
/* /*
* Get the Bank number and Pin number within the bank. * Get the Bank number and Pin number within the bank.
*/ */
XGpioPs_GetBankPin(Pin, &Bank, &PinNumber); XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_DATA_BANK_OFFSET) + ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
XGPIOPS_DATA_RO_OFFSET) >> PinNumber) & 1; XGPIOPS_DATA_RO_OFFSET) >> (u32)PinNumber) & (u32)1;
} }
@ -228,7 +218,7 @@ void XGpioPs_Write(XGpioPs *InstancePtr, u8 Bank, u32 Data)
Xil_AssertVoid(Bank < XGPIOPS_MAX_BANKS); Xil_AssertVoid(Bank < XGPIOPS_MAX_BANKS);
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_DATA_BANK_OFFSET) + ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
XGPIOPS_DATA_OFFSET, Data); XGPIOPS_DATA_OFFSET, Data);
} }
@ -249,12 +239,13 @@ void XGpioPs_Write(XGpioPs *InstancePtr, u8 Bank, u32 Data)
* is maintained. * is maintained.
* *
*****************************************************************************/ *****************************************************************************/
void XGpioPs_WritePin(XGpioPs *InstancePtr, int Pin, int Data) void XGpioPs_WritePin(XGpioPs *InstancePtr, u32 Pin, u32 Data)
{ {
u32 RegOffset; u32 RegOffset;
u32 Value; u32 Value;
u8 Bank; u8 Bank;
u8 PinNumber; u8 PinNumber;
u32 DataVar = Data;
Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
@ -263,13 +254,13 @@ void XGpioPs_WritePin(XGpioPs *InstancePtr, int Pin, int Data)
/* /*
* Get the Bank number and Pin number within the bank. * Get the Bank number and Pin number within the bank.
*/ */
XGpioPs_GetBankPin(Pin, &Bank, &PinNumber); XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
if (PinNumber > 15) { if (PinNumber > 15U) {
/* /*
* There are only 16 data bits in bit maskable register. * There are only 16 data bits in bit maskable register.
*/ */
PinNumber -= 16; PinNumber -= (u8)16;
RegOffset = XGPIOPS_DATA_MSW_OFFSET; RegOffset = XGPIOPS_DATA_MSW_OFFSET;
} else { } else {
RegOffset = XGPIOPS_DATA_LSW_OFFSET; RegOffset = XGPIOPS_DATA_LSW_OFFSET;
@ -279,10 +270,10 @@ void XGpioPs_WritePin(XGpioPs *InstancePtr, int Pin, int Data)
* Get the 32 bit value to be written to the Mask/Data register where * Get the 32 bit value to be written to the Mask/Data register where
* the upper 16 bits is the mask and lower 16 bits is the data. * the upper 16 bits is the mask and lower 16 bits is the data.
*/ */
Data &= 0x01; DataVar &= (u32)0x01;
Value = ~(1 << (PinNumber + 16)) & ((Data << PinNumber) | 0xFFFF0000); Value = ~((u32)1 << (PinNumber + 16U)) & ((DataVar << PinNumber) | 0xFFFF0000U);
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_DATA_MASK_OFFSET) + ((u32)(Bank) * XGPIOPS_DATA_MASK_OFFSET) +
RegOffset, Value); RegOffset, Value);
} }
@ -314,7 +305,7 @@ void XGpioPs_SetDirection(XGpioPs *InstancePtr, u8 Bank, u32 Direction)
Xil_AssertVoid(Bank < XGPIOPS_MAX_BANKS); Xil_AssertVoid(Bank < XGPIOPS_MAX_BANKS);
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_DIRM_OFFSET, Direction); XGPIOPS_DIRM_OFFSET, Direction);
} }
@ -332,7 +323,7 @@ void XGpioPs_SetDirection(XGpioPs *InstancePtr, u8 Bank, u32 Direction)
* @return None. * @return None.
* *
*****************************************************************************/ *****************************************************************************/
void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, int Pin, int Direction) void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, u32 Pin, u32 Direction)
{ {
u8 Bank; u8 Bank;
u8 PinNumber; u8 PinNumber;
@ -341,25 +332,25 @@ void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, int Pin, int Direction)
Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM); Xil_AssertVoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM);
Xil_AssertVoid((Direction == 0) || (Direction == 1)); Xil_AssertVoid(Direction <= (u32)1);
/* /*
* Get the Bank number and Pin number within the bank. * Get the Bank number and Pin number within the bank.
*/ */
XGpioPs_GetBankPin(Pin, &Bank, &PinNumber); XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
DirModeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, DirModeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_DIRM_OFFSET); XGPIOPS_DIRM_OFFSET);
if (Direction) { /* Output Direction */ if (Direction!=(u32)0) { /* Output Direction */
DirModeReg |= (1 << PinNumber); DirModeReg |= ((u32)1 << (u32)PinNumber);
} else { /* Input Direction */ } else { /* Input Direction */
DirModeReg &= ~ (1 << PinNumber); DirModeReg &= ~ ((u32)1 << (u32)PinNumber);
} }
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_DIRM_OFFSET, DirModeReg); XGPIOPS_DIRM_OFFSET, DirModeReg);
} }
@ -385,7 +376,7 @@ u32 XGpioPs_GetDirection(XGpioPs *InstancePtr, u8 Bank)
Xil_AssertNonvoid(Bank < XGPIOPS_MAX_BANKS); Xil_AssertNonvoid(Bank < XGPIOPS_MAX_BANKS);
return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_DIRM_OFFSET); XGPIOPS_DIRM_OFFSET);
} }
@ -406,7 +397,7 @@ u32 XGpioPs_GetDirection(XGpioPs *InstancePtr, u8 Bank)
* @note None. * @note None.
* *
*****************************************************************************/ *****************************************************************************/
int XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, int Pin) u32 XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, u32 Pin)
{ {
u8 Bank; u8 Bank;
u8 PinNumber; u8 PinNumber;
@ -418,11 +409,11 @@ int XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, int Pin)
/* /*
* Get the Bank number and Pin number within the bank. * Get the Bank number and Pin number within the bank.
*/ */
XGpioPs_GetBankPin(Pin, &Bank, &PinNumber); XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_DIRM_OFFSET) >> PinNumber) & 1; XGPIOPS_DIRM_OFFSET) >> (u32)PinNumber) & (u32)1;
} }
/****************************************************************************/ /****************************************************************************/
@ -451,7 +442,7 @@ void XGpioPs_SetOutputEnable(XGpioPs *InstancePtr, u8 Bank, u32 OpEnable)
Xil_AssertVoid(Bank < XGPIOPS_MAX_BANKS); Xil_AssertVoid(Bank < XGPIOPS_MAX_BANKS);
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_OUTEN_OFFSET, OpEnable); XGPIOPS_OUTEN_OFFSET, OpEnable);
} }
@ -473,7 +464,7 @@ void XGpioPs_SetOutputEnable(XGpioPs *InstancePtr, u8 Bank, u32 OpEnable)
* @note None. * @note None.
* *
*****************************************************************************/ *****************************************************************************/
void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, int Pin, int OpEnable) void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin, u32 OpEnable)
{ {
u8 Bank; u8 Bank;
u8 PinNumber; u8 PinNumber;
@ -482,25 +473,25 @@ void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, int Pin, int OpEnable)
Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM); Xil_AssertVoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM);
Xil_AssertVoid((OpEnable == 0) || (OpEnable == 1)); Xil_AssertVoid(OpEnable <= (u32)1);
/* /*
* Get the Bank number and Pin number within the bank. * Get the Bank number and Pin number within the bank.
*/ */
XGpioPs_GetBankPin(Pin, &Bank, &PinNumber); XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
OpEnableReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, OpEnableReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_OUTEN_OFFSET); XGPIOPS_OUTEN_OFFSET);
if (OpEnable) { /* Enable Output Enable */ if (OpEnable != (u32)0) { /* Enable Output Enable */
OpEnableReg |= (1 << PinNumber); OpEnableReg |= ((u32)1 << (u32)PinNumber);
} else { /* Disable Output Enable */ } else { /* Disable Output Enable */
OpEnableReg &= ~ (1 << PinNumber); OpEnableReg &= ~ ((u32)1 << (u32)PinNumber);
} }
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_OUTEN_OFFSET, OpEnableReg); XGPIOPS_OUTEN_OFFSET, OpEnableReg);
} }
/****************************************************************************/ /****************************************************************************/
@ -526,7 +517,7 @@ u32 XGpioPs_GetOutputEnable(XGpioPs *InstancePtr, u8 Bank)
Xil_AssertNonvoid(Bank < XGPIOPS_MAX_BANKS); Xil_AssertNonvoid(Bank < XGPIOPS_MAX_BANKS);
return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_OUTEN_OFFSET); XGPIOPS_OUTEN_OFFSET);
} }
@ -547,7 +538,7 @@ u32 XGpioPs_GetOutputEnable(XGpioPs *InstancePtr, u8 Bank)
* @note None. * @note None.
* *
*****************************************************************************/ *****************************************************************************/
int XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, int Pin) u32 XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin)
{ {
u8 Bank; u8 Bank;
u8 PinNumber; u8 PinNumber;
@ -559,11 +550,11 @@ int XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, int Pin)
/* /*
* Get the Bank number and Pin number within the bank. * Get the Bank number and Pin number within the bank.
*/ */
XGpioPs_GetBankPin(Pin, &Bank, &PinNumber); XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_OUTEN_OFFSET) >> PinNumber) & 1; XGPIOPS_OUTEN_OFFSET) >> (u32)PinNumber) & (u32)1;
} }
/****************************************************************************/ /****************************************************************************/
@ -577,21 +568,34 @@ int XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, int Pin)
* Valid values are 0 to XGPIOPS_MAX_BANKS - 1. * Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
* @param PinNumberInBank returns the Pin Number within the Bank. * @param PinNumberInBank returns the Pin Number within the Bank.
* *
* return None; * @return None.
* *
* @note None. * @note None.
* *
*****************************************************************************/ *****************************************************************************/
void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank) void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank)
{ {
for (*BankNumber = 0; *BankNumber < 4; (*BankNumber)++) /*
if (PinNumber <= XGpioPsPinTable[*BankNumber]) * This structure defines the mapping of the pin numbers to the banks when
* the driver APIs are used for working on the individual pins.
*/
u32 XGpioPsPinTable[] = {
(u32)31, /* 0 - 31, Bank 0 */
(u32)53, /* 32 - 53, Bank 1 */
(u32)85, /* 54 - 85, Bank 2 */
(u32)117 /* 86 - 117 Bank 3 */
};
*BankNumber = 0U;
while (*BankNumber < 4U) {
if (PinNumber <= XGpioPsPinTable[*BankNumber]) {
break; break;
}
if (*BankNumber == 0) { (*BankNumber)++;
}
if (*BankNumber == (u8)0) {
*PinNumberInBank = PinNumber; *PinNumberInBank = PinNumber;
} else { } else {
*PinNumberInBank = PinNumber % *PinNumberInBank = (u8)((u32)PinNumber %
(XGpioPsPinTable[*BankNumber - 1] + 1); (XGpioPsPinTable[*BankNumber - (u8)1] + (u32)1));
} }
} }

60
XilinxProcessorIPLib/drivers/gpiops/src/xgpiops.h
View file

@ -115,22 +115,22 @@ extern "C" {
* The following constants define the interrupt types that can be set for each * The following constants define the interrupt types that can be set for each
* GPIO pin. * GPIO pin.
*/ */
#define XGPIOPS_IRQ_TYPE_EDGE_RISING 0 /**< Interrupt on Rising edge */ #define XGPIOPS_IRQ_TYPE_EDGE_RISING 0x00U /**< Interrupt on Rising edge */
#define XGPIOPS_IRQ_TYPE_EDGE_FALLING 1 /**< Interrupt Falling edge */ #define XGPIOPS_IRQ_TYPE_EDGE_FALLING 0x01U /**< Interrupt Falling edge */
#define XGPIOPS_IRQ_TYPE_EDGE_BOTH 2 /**< Interrupt on both edges */ #define XGPIOPS_IRQ_TYPE_EDGE_BOTH 0x02U /**< Interrupt on both edges */
#define XGPIOPS_IRQ_TYPE_LEVEL_HIGH 3 /**< Interrupt on high level */ #define XGPIOPS_IRQ_TYPE_LEVEL_HIGH 0x03U /**< Interrupt on high level */
#define XGPIOPS_IRQ_TYPE_LEVEL_LOW 4 /**< Interrupt on low level */ #define XGPIOPS_IRQ_TYPE_LEVEL_LOW 0x04U /**< Interrupt on low level */
/*@}*/ /*@}*/
#define XGPIOPS_BANK0 0 /**< GPIO Bank 0 */ #define XGPIOPS_BANK0 0x00U /**< GPIO Bank 0 */
#define XGPIOPS_BANK1 1 /**< GPIO Bank 1 */ #define XGPIOPS_BANK1 0x01U /**< GPIO Bank 1 */
#define XGPIOPS_BANK2 2 /**< GPIO Bank 2 */ #define XGPIOPS_BANK2 0x02U /**< GPIO Bank 2 */
#define XGPIOPS_BANK3 3 /**< GPIO Bank 3 */ #define XGPIOPS_BANK3 0x03U /**< GPIO Bank 3 */
#define XGPIOPS_MAX_BANKS 4 /**< Max banks in a GPIO device */ #define XGPIOPS_MAX_BANKS 0x04U /**< Max banks in a GPIO device */
#define XGPIOPS_BANK_MAX_PINS 32 /**< Max pins in a GPIO bank */ #define XGPIOPS_BANK_MAX_PINS (u32)32 /**< Max pins in a GPIO bank */
#define XGPIOPS_DEVICE_MAX_PIN_NUM 118 /*< Max pins in the GPIO device #define XGPIOPS_DEVICE_MAX_PIN_NUM (u32)118 /*< Max pins in the GPIO device
* 0 - 31, Bank 0 * 0 - 31, Bank 0
* 32 - 53, Bank 1 * 32 - 53, Bank 1
* 54 - 85, Bank 2 * 54 - 85, Bank 2
@ -156,7 +156,7 @@ extern "C" {
* @param Status is the Interrupt status of the GPIO bank. * @param Status is the Interrupt status of the GPIO bank.
* *
*****************************************************************************/ *****************************************************************************/
typedef void (*XGpioPs_Handler) (void *CallBackRef, int Bank, u32 Status); typedef void (*XGpioPs_Handler) (void *CallBackRef, u32 Bank, u32 Status);
/** /**
* This typedef contains configuration information for a device. * This typedef contains configuration information for a device.
@ -185,7 +185,7 @@ typedef struct {
/* /*
* Functions in xgpiops.c * Functions in xgpiops.c
*/ */
int XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr, s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr,
u32 EffectiveAddr); u32 EffectiveAddr);
/* /*
@ -195,24 +195,24 @@ u32 XGpioPs_Read(XGpioPs *InstancePtr, u8 Bank);
void XGpioPs_Write(XGpioPs *InstancePtr, u8 Bank, u32 Data); void XGpioPs_Write(XGpioPs *InstancePtr, u8 Bank, u32 Data);
void XGpioPs_SetDirection(XGpioPs *InstancePtr, u8 Bank, u32 Direction); void XGpioPs_SetDirection(XGpioPs *InstancePtr, u8 Bank, u32 Direction);
u32 XGpioPs_GetDirection(XGpioPs *InstancePtr, u8 Bank); u32 XGpioPs_GetDirection(XGpioPs *InstancePtr, u8 Bank);
void XGpioPs_SetOutputEnable(XGpioPs *InstancePtr, u8 Bank, u32 Enable); void XGpioPs_SetOutputEnable(XGpioPs *InstancePtr, u8 Bank, u32 OpEnable);
u32 XGpioPs_GetOutputEnable(XGpioPs *InstancePtr, u8 Bank); u32 XGpioPs_GetOutputEnable(XGpioPs *InstancePtr, u8 Bank);
void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank); void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank);
/* /*
* Pin APIs in xgpiops.c * Pin APIs in xgpiops.c
*/ */
int XGpioPs_ReadPin(XGpioPs *InstancePtr, int Pin); u32 XGpioPs_ReadPin(XGpioPs *InstancePtr, u32 Pin);
void XGpioPs_WritePin(XGpioPs *InstancePtr, int Pin, int Data); void XGpioPs_WritePin(XGpioPs *InstancePtr, u32 Pin, u32 Data);
void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, int Pin, int Direction); void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, u32 Pin, u32 Direction);
int XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, int Pin); u32 XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, u32 Pin);
void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, int Pin, int Enable); void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin, u32 OpEnable);
int XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, int Pin); u32 XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin);
/* /*
* Diagnostic functions in xgpiops_selftest.c * Diagnostic functions in xgpiops_selftest.c
*/ */
int XGpioPs_SelfTest(XGpioPs *InstancePtr); s32 XGpioPs_SelfTest(XGpioPs *InstancePtr);
/* /*
* Functions in xgpiops_intr.c * Functions in xgpiops_intr.c
@ -230,20 +230,20 @@ void XGpioPs_SetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
void XGpioPs_GetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 *IntrType, void XGpioPs_GetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
u32 *IntrPolarity, u32 *IntrOnAny); u32 *IntrPolarity, u32 *IntrOnAny);
void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef, void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
XGpioPs_Handler FuncPtr); XGpioPs_Handler FuncPointer);
void XGpioPs_IntrHandler(XGpioPs *InstancePtr); void XGpioPs_IntrHandler(XGpioPs *InstancePtr);
/* /*
* Pin APIs in xgpiops_intr.c * Pin APIs in xgpiops_intr.c
*/ */
void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, int Pin, u8 IrqType); void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, u32 Pin, u8 IrqType);
u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, int Pin); u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, u32 Pin);
void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, int Pin); void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, u32 Pin);
void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, int Pin); void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, u32 Pin);
int XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, int Pin); u32 XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, u32 Pin);
int XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, int Pin); u32 XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, u32 Pin);
void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, int Pin); void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, u32 Pin);
/* /*
* Functions in xgpiops_sinit.c * Functions in xgpiops_sinit.c

4
XilinxProcessorIPLib/drivers/gpiops/src/xgpiops_g.c
View file

@ -68,7 +68,7 @@
*/ */
XGpioPs_Config XGpioPs_ConfigTable[XPAR_XGPIOPS_NUM_INSTANCES] = { XGpioPs_Config XGpioPs_ConfigTable[XPAR_XGPIOPS_NUM_INSTANCES] = {
{ {
XPAR_XGPIOPS_0_DEVICE_ID, /* Unique ID of device */ (u16)XPAR_XGPIOPS_0_DEVICE_ID, /* Unique ID of device */
XPAR_XGPIOPS_0_BASEADDR /* Base address of device */ (u32)XPAR_XGPIOPS_0_BASEADDR /* Base address of device */
} }
}; };

34
XilinxProcessorIPLib/drivers/gpiops/src/xgpiops_hw.c
View file

@ -83,54 +83,54 @@ void XGpioPs_ResetHw(u32 BaseAddress)
/* /*
* Write reset values to all mask data registers * Write reset values to all mask data registers
*/ */
for(BankCount = 2; BankCount < XGPIOPS_MAX_BANKS; BankCount++) { for(BankCount = 2U; BankCount < (u32)XGPIOPS_MAX_BANKS; BankCount++) {
XGpioPs_WriteReg(BaseAddress, XGpioPs_WriteReg(BaseAddress,
((BankCount * XGPIOPS_DATA_MASK_OFFSET) + ((BankCount * XGPIOPS_DATA_MASK_OFFSET) +
XGPIOPS_DATA_LSW_OFFSET), 0x0); XGPIOPS_DATA_LSW_OFFSET), 0x0U);
XGpioPs_WriteReg(BaseAddress, XGpioPs_WriteReg(BaseAddress,
((BankCount * XGPIOPS_DATA_MASK_OFFSET) + ((BankCount * XGPIOPS_DATA_MASK_OFFSET) +
XGPIOPS_DATA_MSW_OFFSET), 0x0); XGPIOPS_DATA_MSW_OFFSET), 0x0U);
} }
/* /*
* Write reset values to all output data registers * Write reset values to all output data registers
*/ */
for(BankCount = 2; BankCount < XGPIOPS_MAX_BANKS; BankCount++) { for(BankCount = 2U; BankCount < (u32)XGPIOPS_MAX_BANKS; BankCount++) {
XGpioPs_WriteReg(BaseAddress, XGpioPs_WriteReg(BaseAddress,
((BankCount * XGPIOPS_DATA_BANK_OFFSET) + ((BankCount * XGPIOPS_DATA_BANK_OFFSET) +
XGPIOPS_DATA_OFFSET), 0x0); XGPIOPS_DATA_OFFSET), 0x0U);
} }
/* /*
* Reset all registers of all 4 banks * Reset all registers of all 4 banks
*/ */
for(BankCount = 0; BankCount < XGPIOPS_MAX_BANKS; BankCount++) { for(BankCount = 0U; BankCount < (u32)XGPIOPS_MAX_BANKS; BankCount++) {
XGpioPs_WriteReg(BaseAddress, XGpioPs_WriteReg(BaseAddress,
((BankCount * XGPIOPS_REG_MASK_OFFSET) + ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_DIRM_OFFSET), 0x0); XGPIOPS_DIRM_OFFSET), 0x0U);
XGpioPs_WriteReg(BaseAddress, XGpioPs_WriteReg(BaseAddress,
((BankCount * XGPIOPS_REG_MASK_OFFSET) + ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_OUTEN_OFFSET), 0x0); XGPIOPS_OUTEN_OFFSET), 0x0U);
XGpioPs_WriteReg(BaseAddress, XGpioPs_WriteReg(BaseAddress,
((BankCount * XGPIOPS_REG_MASK_OFFSET) + ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTMASK_OFFSET), 0x0); XGPIOPS_INTMASK_OFFSET), 0x0U);
XGpioPs_WriteReg(BaseAddress, XGpioPs_WriteReg(BaseAddress,
((BankCount * XGPIOPS_REG_MASK_OFFSET) + ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTEN_OFFSET), 0x0); XGPIOPS_INTEN_OFFSET), 0x0U);
XGpioPs_WriteReg(BaseAddress, XGpioPs_WriteReg(BaseAddress,
((BankCount * XGPIOPS_REG_MASK_OFFSET) + ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTDIS_OFFSET), 0x0); XGPIOPS_INTDIS_OFFSET), 0x0U);
XGpioPs_WriteReg(BaseAddress, XGpioPs_WriteReg(BaseAddress,
((BankCount * XGPIOPS_REG_MASK_OFFSET) + ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTSTS_OFFSET), 0x0); XGPIOPS_INTSTS_OFFSET), 0x0U);
XGpioPs_WriteReg(BaseAddress, XGpioPs_WriteReg(BaseAddress,
((BankCount * XGPIOPS_REG_MASK_OFFSET) + ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTPOL_OFFSET), 0x0); XGPIOPS_INTPOL_OFFSET), 0x0U);
XGpioPs_WriteReg(BaseAddress, XGpioPs_WriteReg(BaseAddress,
((BankCount * XGPIOPS_REG_MASK_OFFSET) + ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTANY_OFFSET), 0x0); XGPIOPS_INTANY_OFFSET), 0x0U);
} }
/* /*
@ -142,19 +142,19 @@ void XGpioPs_ResetHw(u32 BaseAddress)
* Bank 1 Int type * Bank 1 Int type
*/ */
XGpioPs_WriteReg(BaseAddress, XGpioPs_WriteReg(BaseAddress,
(XGPIOPS_REG_MASK_OFFSET + XGPIOPS_INTTYPE_OFFSET), ((u32)XGPIOPS_REG_MASK_OFFSET + (u32)XGPIOPS_INTTYPE_OFFSET),
XGPIOPS_INTTYPE_BANK1_RESET); XGPIOPS_INTTYPE_BANK1_RESET);
/* /*
* Bank 2 Int type * Bank 2 Int type
*/ */
XGpioPs_WriteReg(BaseAddress, XGpioPs_WriteReg(BaseAddress,
((2*XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET), (((u32)2 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
XGPIOPS_INTTYPE_BANK2_RESET); XGPIOPS_INTTYPE_BANK2_RESET);
/* /*
* Bank 3 Int type * Bank 3 Int type
*/ */
XGpioPs_WriteReg(BaseAddress, XGpioPs_WriteReg(BaseAddress,
((3*XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET), (((u32)3 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
XGPIOPS_INTTYPE_BANK3_RESET); XGPIOPS_INTTYPE_BANK3_RESET);
} }

46
XilinxProcessorIPLib/drivers/gpiops/src/xgpiops_hw.h
View file

@ -67,39 +67,39 @@ extern "C" {
/** @name Register offsets for the GPIO. Each register is 32 bits. /** @name Register offsets for the GPIO. Each register is 32 bits.
* @{ * @{
*/ */
#define XGPIOPS_DATA_LSW_OFFSET 0x000 /* Mask and Data Register LSW, WO */ #define XGPIOPS_DATA_LSW_OFFSET 0x00000000U /* Mask and Data Register LSW, WO */
#define XGPIOPS_DATA_MSW_OFFSET 0x004 /* Mask and Data Register MSW, WO */ #define XGPIOPS_DATA_MSW_OFFSET 0x00000004U /* Mask and Data Register MSW, WO */
#define XGPIOPS_DATA_OFFSET 0x040 /* Data Register, RW */ #define XGPIOPS_DATA_OFFSET 0x00000040U /* Data Register, RW */
#define XGPIOPS_DATA_RO_OFFSET 0x060 /* Data Register - Input, RO */ #define XGPIOPS_DATA_RO_OFFSET 0x00000060U /* Data Register - Input, RO */
#define XGPIOPS_DIRM_OFFSET 0x204 /* Direction Mode Register, RW */ #define XGPIOPS_DIRM_OFFSET 0x00000204U /* Direction Mode Register, RW */
#define XGPIOPS_OUTEN_OFFSET 0x208 /* Output Enable Register, RW */ #define XGPIOPS_OUTEN_OFFSET 0x00000208U /* Output Enable Register, RW */
#define XGPIOPS_INTMASK_OFFSET 0x20C /* Interrupt Mask Register, RO */ #define XGPIOPS_INTMASK_OFFSET 0x0000020CU /* Interrupt Mask Register, RO */
#define XGPIOPS_INTEN_OFFSET 0x210 /* Interrupt Enable Register, WO */ #define XGPIOPS_INTEN_OFFSET 0x00000210U /* Interrupt Enable Register, WO */
#define XGPIOPS_INTDIS_OFFSET 0x214 /* Interrupt Disable Register, WO*/ #define XGPIOPS_INTDIS_OFFSET 0x00000214U /* Interrupt Disable Register, WO*/
#define XGPIOPS_INTSTS_OFFSET 0x218 /* Interrupt Status Register, RO */ #define XGPIOPS_INTSTS_OFFSET 0x00000218U /* Interrupt Status Register, RO */
#define XGPIOPS_INTTYPE_OFFSET 0x21C /* Interrupt Type Register, RW */ #define XGPIOPS_INTTYPE_OFFSET 0x0000021CU /* Interrupt Type Register, RW */
#define XGPIOPS_INTPOL_OFFSET 0x220 /* Interrupt Polarity Register, RW */ #define XGPIOPS_INTPOL_OFFSET 0x00000220U /* Interrupt Polarity Register, RW */
#define XGPIOPS_INTANY_OFFSET 0x224 /* Interrupt On Any Register, RW */ #define XGPIOPS_INTANY_OFFSET 0x00000224U /* Interrupt On Any Register, RW */
/* @} */ /* @} */
/** @name Register offsets for each Bank. /** @name Register offsets for each Bank.
* @{ * @{
*/ */
#define XGPIOPS_DATA_MASK_OFFSET 0x8 /* Data/Mask Registers offset */ #define XGPIOPS_DATA_MASK_OFFSET 0x00000008U /* Data/Mask Registers offset */
#define XGPIOPS_DATA_BANK_OFFSET 0x4 /* Data Registers offset */ #define XGPIOPS_DATA_BANK_OFFSET 0x00000004U /* Data Registers offset */
#define XGPIOPS_REG_MASK_OFFSET 0x40 /* Registers offset */ #define XGPIOPS_REG_MASK_OFFSET 0x00000040U /* Registers offset */
/* @} */ /* @} */
/* For backwards compatibility */ /* For backwards compatibility */
#define XGPIOPS_BYPM_MASK_OFFSET XGPIOPS_REG_MASK_OFFSET #define XGPIOPS_BYPM_MASK_OFFSET (u32)0x40
/** @name Interrupt type reset values for each bank /** @name Interrupt type reset values for each bank
* @{ * @{
*/ */
#define XGPIOPS_INTTYPE_BANK0_RESET 0xFFFFFFFF #define XGPIOPS_INTTYPE_BANK0_RESET 0xFFFFFFFFU
#define XGPIOPS_INTTYPE_BANK1_RESET 0x3FFFFFFF #define XGPIOPS_INTTYPE_BANK1_RESET 0x3FFFFFFFU
#define XGPIOPS_INTTYPE_BANK2_RESET 0xFFFFFFFF #define XGPIOPS_INTTYPE_BANK2_RESET 0xFFFFFFFFU
#define XGPIOPS_INTTYPE_BANK3_RESET 0xFFFFFFFF #define XGPIOPS_INTTYPE_BANK3_RESET 0xFFFFFFFFU
/* @} */ /* @} */
/**************************** Type Definitions *******************************/ /**************************** Type Definitions *******************************/
@ -120,7 +120,7 @@ extern "C" {
* *
*****************************************************************************/ *****************************************************************************/
#define XGpioPs_ReadReg(BaseAddr, RegOffset) \ #define XGpioPs_ReadReg(BaseAddr, RegOffset) \
Xil_In32((BaseAddr) + (RegOffset)) Xil_In32((BaseAddr) + (u32)(RegOffset))
/****************************************************************************/ /****************************************************************************/
/** /**
@ -137,7 +137,7 @@ extern "C" {
* *
*****************************************************************************/ *****************************************************************************/
#define XGpioPs_WriteReg(BaseAddr, RegOffset, Data) \ #define XGpioPs_WriteReg(BaseAddr, RegOffset, Data) \
Xil_Out32((BaseAddr) + (RegOffset), (Data)) Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
/************************** Function Prototypes ******************************/ /************************** Function Prototypes ******************************/

170
XilinxProcessorIPLib/drivers/gpiops/src/xgpiops_intr.c
View file

@ -62,7 +62,7 @@
/************************** Function Prototypes ******************************/ /************************** Function Prototypes ******************************/
void StubHandler(void *CallBackRef, int Bank, u32 Status); void StubHandler(void *CallBackRef, u32 Bank, u32 Status);
/****************************************************************************/ /****************************************************************************/
/** /**
@ -89,7 +89,7 @@ void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask)
Xil_AssertVoid(Bank < XGPIOPS_MAX_BANKS); Xil_AssertVoid(Bank < XGPIOPS_MAX_BANKS);
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTEN_OFFSET, Mask); XGPIOPS_INTEN_OFFSET, Mask);
} }
@ -107,11 +107,11 @@ void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask)
* @note None. * @note None.
* *
*****************************************************************************/ *****************************************************************************/
void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, int Pin) void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, u32 Pin)
{ {
u8 Bank; u8 Bank;
u8 PinNumber; u8 PinNumber;
u32 IntrReg = 0; u32 IntrReg = 0U;
Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
@ -120,11 +120,11 @@ void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, int Pin)
/* /*
* Get the Bank number and Pin number within the bank. * Get the Bank number and Pin number within the bank.
*/ */
XGpioPs_GetBankPin(Pin, &Bank, &PinNumber); XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
IntrReg = 1 << PinNumber; IntrReg = ((u32)1 << (u32)PinNumber);
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTEN_OFFSET, IntrReg); XGPIOPS_INTEN_OFFSET, IntrReg);
} }
@ -153,7 +153,7 @@ void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask)
Xil_AssertVoid(Bank < XGPIOPS_MAX_BANKS); Xil_AssertVoid(Bank < XGPIOPS_MAX_BANKS);
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTDIS_OFFSET, Mask); XGPIOPS_INTDIS_OFFSET, Mask);
} }
@ -171,11 +171,11 @@ void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask)
* @note None. * @note None.
* *
*****************************************************************************/ *****************************************************************************/
void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, int Pin) void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, u32 Pin)
{ {
u8 Bank; u8 Bank;
u8 PinNumber; u8 PinNumber;
u32 IntrReg = 0; u32 IntrReg = 0U;
Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
@ -184,11 +184,11 @@ void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, int Pin)
/* /*
* Get the Bank number and Pin number within the bank. * Get the Bank number and Pin number within the bank.
*/ */
XGpioPs_GetBankPin(Pin, &Bank, &PinNumber); XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
IntrReg = 1 << PinNumber; IntrReg = ((u32)1 << (u32)PinNumber);
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTDIS_OFFSET, IntrReg); XGPIOPS_INTDIS_OFFSET, IntrReg);
} }
@ -218,9 +218,9 @@ u32 XGpioPs_IntrGetEnabled(XGpioPs *InstancePtr, u8 Bank)
Xil_AssertNonvoid(Bank < XGPIOPS_MAX_BANKS); Xil_AssertNonvoid(Bank < XGPIOPS_MAX_BANKS);
IntrMask = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, IntrMask = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTMASK_OFFSET); XGPIOPS_INTMASK_OFFSET);
return ~IntrMask; return (~IntrMask);
} }
/****************************************************************************/ /****************************************************************************/
@ -240,7 +240,7 @@ u32 XGpioPs_IntrGetEnabled(XGpioPs *InstancePtr, u8 Bank)
* @note None. * @note None.
* *
*****************************************************************************/ *****************************************************************************/
int XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, int Pin) u32 XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, u32 Pin)
{ {
u8 Bank; u8 Bank;
u8 PinNumber; u8 PinNumber;
@ -253,13 +253,13 @@ int XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, int Pin)
/* /*
* Get the Bank number and Pin number within the bank. * Get the Bank number and Pin number within the bank.
*/ */
XGpioPs_GetBankPin(Pin, &Bank, &PinNumber); XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTMASK_OFFSET); XGPIOPS_INTMASK_OFFSET);
return (IntrReg & (1 << PinNumber)) ? FALSE : TRUE; return (((IntrReg & ((u32)1 << PinNumber)) != (u32)0)? FALSE : TRUE);
} }
/****************************************************************************/ /****************************************************************************/
@ -283,7 +283,7 @@ u32 XGpioPs_IntrGetStatus(XGpioPs *InstancePtr, u8 Bank)
Xil_AssertNonvoid(Bank < XGPIOPS_MAX_BANKS); Xil_AssertNonvoid(Bank < XGPIOPS_MAX_BANKS);
return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTSTS_OFFSET); XGPIOPS_INTSTS_OFFSET);
} }
@ -304,7 +304,7 @@ u32 XGpioPs_IntrGetStatus(XGpioPs *InstancePtr, u8 Bank)
* @note None. * @note None.
* *
*****************************************************************************/ *****************************************************************************/
int XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, int Pin) u32 XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, u32 Pin)
{ {
u8 Bank; u8 Bank;
u8 PinNumber; u8 PinNumber;
@ -317,13 +317,13 @@ int XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, int Pin)
/* /*
* Get the Bank number and Pin number within the bank. * Get the Bank number and Pin number within the bank.
*/ */
XGpioPs_GetBankPin(Pin, &Bank, &PinNumber); XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTSTS_OFFSET); XGPIOPS_INTSTS_OFFSET);
return (IntrReg & (1 << PinNumber)) ? TRUE : FALSE; return (((IntrReg & ((u32)1 << PinNumber)) != (u32)0)? TRUE : FALSE);
} }
/****************************************************************************/ /****************************************************************************/
@ -353,7 +353,7 @@ void XGpioPs_IntrClear(XGpioPs *InstancePtr, u8 Bank, u32 Mask)
* Clear the currently pending interrupts. * Clear the currently pending interrupts.
*/ */
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTSTS_OFFSET, Mask); XGPIOPS_INTSTS_OFFSET, Mask);
} }
@ -370,7 +370,7 @@ void XGpioPs_IntrClear(XGpioPs *InstancePtr, u8 Bank, u32 Mask)
* @note None. * @note None.
* *
*****************************************************************************/ *****************************************************************************/
void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, int Pin) void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, u32 Pin)
{ {
u8 Bank; u8 Bank;
u8 PinNumber; u8 PinNumber;
@ -383,18 +383,18 @@ void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, int Pin)
/* /*
* Get the Bank number and Pin number within the bank. * Get the Bank number and Pin number within the bank.
*/ */
XGpioPs_GetBankPin(Pin, &Bank, &PinNumber); XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
/* /*
* Clear the specified pending interrupts. * Clear the specified pending interrupts.
*/ */
IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTSTS_OFFSET); XGPIOPS_INTSTS_OFFSET);
IntrReg &= (1 << PinNumber); IntrReg &= ((u32)1 << PinNumber);
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTSTS_OFFSET, IntrReg); XGPIOPS_INTSTS_OFFSET, IntrReg);
} }
@ -434,15 +434,15 @@ void XGpioPs_SetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
Xil_AssertVoid(Bank < XGPIOPS_MAX_BANKS); Xil_AssertVoid(Bank < XGPIOPS_MAX_BANKS);
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTTYPE_OFFSET, IntrType); XGPIOPS_INTTYPE_OFFSET, IntrType);
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTPOL_OFFSET, IntrPolarity); XGPIOPS_INTPOL_OFFSET, IntrPolarity);
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTANY_OFFSET, IntrOnAny); XGPIOPS_INTANY_OFFSET, IntrOnAny);
} }
@ -479,15 +479,15 @@ void XGpioPs_GetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
Xil_AssertVoid(Bank < XGPIOPS_MAX_BANKS); Xil_AssertVoid(Bank < XGPIOPS_MAX_BANKS);
*IntrType = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, *IntrType = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTTYPE_OFFSET); XGPIOPS_INTTYPE_OFFSET);
*IntrPolarity = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, *IntrPolarity = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTPOL_OFFSET); XGPIOPS_INTPOL_OFFSET);
*IntrOnAny = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, *IntrOnAny = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTANY_OFFSET); XGPIOPS_INTANY_OFFSET);
} }
@ -507,7 +507,7 @@ void XGpioPs_GetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
* @note None. * @note None.
* *
*****************************************************************************/ *****************************************************************************/
void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, int Pin, u8 IrqType) void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, u32 Pin, u8 IrqType)
{ {
u32 IntrTypeReg; u32 IntrTypeReg;
u32 IntrPolReg; u32 IntrPolReg;
@ -523,55 +523,58 @@ void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, int Pin, u8 IrqType)
/* /*
* Get the Bank number and Pin number within the bank. * Get the Bank number and Pin number within the bank.
*/ */
XGpioPs_GetBankPin(Pin, &Bank, &PinNumber); XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
IntrTypeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, IntrTypeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTTYPE_OFFSET); XGPIOPS_INTTYPE_OFFSET);
IntrPolReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, IntrPolReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTPOL_OFFSET); XGPIOPS_INTPOL_OFFSET);
IntrOnAnyReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, IntrOnAnyReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTANY_OFFSET); XGPIOPS_INTANY_OFFSET);
switch (IrqType) { switch (IrqType) {
case XGPIOPS_IRQ_TYPE_EDGE_RISING: case XGPIOPS_IRQ_TYPE_EDGE_RISING:
IntrTypeReg |= (1 << PinNumber); IntrTypeReg |= ((u32)1 << (u32)PinNumber);
IntrPolReg |= (1 << PinNumber); IntrPolReg |= ((u32)1 << (u32)PinNumber);
IntrOnAnyReg &= ~(1 << PinNumber); IntrOnAnyReg &= ~((u32)1 << (u32)PinNumber);
break; break;
case XGPIOPS_IRQ_TYPE_EDGE_FALLING: case XGPIOPS_IRQ_TYPE_EDGE_FALLING:
IntrTypeReg |= (1 << PinNumber); IntrTypeReg |= ((u32)1 << (u32)PinNumber);
IntrPolReg &= ~(1 << PinNumber); IntrPolReg &= ~((u32)1 << (u32)PinNumber);
IntrOnAnyReg &= ~(1 << PinNumber); IntrOnAnyReg &= ~((u32)1 << (u32)PinNumber);
break; break;
case XGPIOPS_IRQ_TYPE_EDGE_BOTH: case XGPIOPS_IRQ_TYPE_EDGE_BOTH:
IntrTypeReg |= (1 << PinNumber); IntrTypeReg |= ((u32)1 << (u32)PinNumber);
IntrOnAnyReg |= (1 << PinNumber); IntrOnAnyReg |= ((u32)1 << (u32)PinNumber);
break; break;
case XGPIOPS_IRQ_TYPE_LEVEL_HIGH: case XGPIOPS_IRQ_TYPE_LEVEL_HIGH:
IntrTypeReg &= ~(1 << PinNumber); IntrTypeReg &= ~((u32)1 << (u32)PinNumber);
IntrPolReg |= (1 << PinNumber); IntrPolReg |= ((u32)1 << (u32)PinNumber);
break; break;
case XGPIOPS_IRQ_TYPE_LEVEL_LOW: case XGPIOPS_IRQ_TYPE_LEVEL_LOW:
IntrTypeReg &= ~(1 << PinNumber); IntrTypeReg &= ~((u32)1 << (u32)PinNumber);
IntrPolReg &= ~(1 << PinNumber); IntrPolReg &= ~((u32)1 << (u32)PinNumber);
break;
default:
/**< Default statement is added for MISRA C compliance. */
break; break;
} }
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTTYPE_OFFSET, IntrTypeReg); XGPIOPS_INTTYPE_OFFSET, IntrTypeReg);
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTPOL_OFFSET, IntrPolReg); XGPIOPS_INTPOL_OFFSET, IntrPolReg);
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTANY_OFFSET, IntrOnAnyReg); XGPIOPS_INTANY_OFFSET, IntrOnAnyReg);
} }
@ -590,7 +593,7 @@ void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, int Pin, u8 IrqType)
* returned by this function. * returned by this function.
* *
*****************************************************************************/ *****************************************************************************/
u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, int Pin) u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, u32 Pin)
{ {
u32 IntrType; u32 IntrType;
u32 IntrPol; u32 IntrPol;
@ -606,30 +609,37 @@ u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, int Pin)
/* /*
* Get the Bank number and Pin number within the bank. * Get the Bank number and Pin number within the bank.
*/ */
XGpioPs_GetBankPin(Pin, &Bank, &PinNumber); XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
IntrType = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, IntrType = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTTYPE_OFFSET) & (1 << PinNumber); XGPIOPS_INTTYPE_OFFSET) & ((u32)1 << PinNumber);
IntrPol = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, if (IntrType == ((u32)1 << PinNumber)) {
((Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTPOL_OFFSET) & (1 << PinNumber);
IntrOnAny = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, IntrOnAny = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTANY_OFFSET) & (1 << PinNumber); XGPIOPS_INTANY_OFFSET) & ((u32)1 << PinNumber);
if (IntrType == (1 << PinNumber)) { IntrPol = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
if (IntrOnAny == (1 << PinNumber)) { ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTPOL_OFFSET) & ((u32)1 << PinNumber);
if (IntrOnAny == ((u32)1 << PinNumber)) {
IrqType = XGPIOPS_IRQ_TYPE_EDGE_BOTH; IrqType = XGPIOPS_IRQ_TYPE_EDGE_BOTH;
} else if (IntrPol == (1 << PinNumber)) { } else if (IntrPol == ((u32)1 << PinNumber)) {
IrqType = XGPIOPS_IRQ_TYPE_EDGE_RISING; IrqType = XGPIOPS_IRQ_TYPE_EDGE_RISING;
} else { } else {
IrqType = XGPIOPS_IRQ_TYPE_EDGE_FALLING; IrqType = XGPIOPS_IRQ_TYPE_EDGE_FALLING;
} }
} else { } else {
if (IntrPol == (1 << PinNumber)) {
IntrPol = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTPOL_OFFSET) & ((u32)1 << PinNumber);
if (IntrPol == ((u32)1 << PinNumber)) {
IrqType = XGPIOPS_IRQ_TYPE_LEVEL_HIGH; IrqType = XGPIOPS_IRQ_TYPE_LEVEL_HIGH;
} else { } else {
IrqType = XGPIOPS_IRQ_TYPE_LEVEL_LOW; IrqType = XGPIOPS_IRQ_TYPE_LEVEL_LOW;
@ -659,13 +669,13 @@ u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, int Pin)
* *
******************************************************************************/ ******************************************************************************/
void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef, void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
XGpioPs_Handler FuncPtr) XGpioPs_Handler FuncPointer)
{ {
Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(FuncPtr != NULL); Xil_AssertVoid(FuncPointer != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
InstancePtr->Handler = FuncPtr; InstancePtr->Handler = FuncPointer;
InstancePtr->CallBackRef = CallBackRef; InstancePtr->CallBackRef = CallBackRef;
} }
@ -695,14 +705,14 @@ void XGpioPs_IntrHandler(XGpioPs *InstancePtr)
Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
for (Bank = 0; Bank < XGPIOPS_MAX_BANKS; Bank++) { for (Bank = 0U; Bank < XGPIOPS_MAX_BANKS; Bank++) {
IntrStatus = XGpioPs_IntrGetStatus(InstancePtr, Bank); IntrStatus = XGpioPs_IntrGetStatus(InstancePtr, Bank);
if (IntrStatus != 0) { if (IntrStatus != (u32)0) {
IntrEnabled = XGpioPs_IntrGetEnabled(InstancePtr, IntrEnabled = XGpioPs_IntrGetEnabled(InstancePtr,
Bank); Bank);
XGpioPs_IntrClear(InstancePtr, Bank, XGpioPs_IntrClear((XGpioPs *)InstancePtr, Bank,
IntrStatus & IntrEnabled); (IntrStatus & IntrEnabled));
InstancePtr->Handler((void *)InstancePtr-> InstancePtr->Handler(InstancePtr->
CallBackRef, Bank, CallBackRef, Bank,
(IntrStatus & IntrEnabled)); (IntrStatus & IntrEnabled));
} }
@ -724,9 +734,9 @@ void XGpioPs_IntrHandler(XGpioPs *InstancePtr)
* @note None. * @note None.
* *
******************************************************************************/ ******************************************************************************/
void StubHandler(void *CallBackRef, int Bank, u32 Status) void StubHandler(void *CallBackRef, u32 Bank, u32 Status)
{ {
(void) CallBackRef; (void*) CallBackRef;
(void) Bank; (void) Bank;
(void) Status; (void) Status;

18
XilinxProcessorIPLib/drivers/gpiops/src/xgpiops_selftest.c
View file

@ -78,17 +78,17 @@
* *
* *
******************************************************************************/ ******************************************************************************/
int XGpioPs_SelfTest(XGpioPs *InstancePtr) s32 XGpioPs_SelfTest(XGpioPs *InstancePtr)
{ {
int Status = XST_SUCCESS; s32 Status = XST_SUCCESS;
u32 IntrEnabled; u32 IntrEnabled;
u32 CurrentIntrType; u32 CurrentIntrType = 0U;
u32 CurrentIntrPolarity; u32 CurrentIntrPolarity = 0U;
u32 CurrentIntrOnAny; u32 CurrentIntrOnAny = 0U;
u32 IntrType; u32 IntrType = 0U;
u32 IntrPolarity; u32 IntrPolarity = 0U;
u32 IntrOnAny; u32 IntrOnAny = 0U;
u32 IntrTestValue = 0x22; u32 IntrTestValue = 0x22U;
Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

8
XilinxProcessorIPLib/drivers/gpiops/src/xgpiops_sinit.c
View file

@ -52,8 +52,8 @@
/***************************** Include Files *********************************/ /***************************** Include Files *********************************/
#include "xparameters.h"
#include "xgpiops.h" #include "xgpiops.h"
#include "xparameters.h"
/************************** Constant Definitions *****************************/ /************************** Constant Definitions *****************************/
@ -64,7 +64,7 @@
/************************** Function Prototypes ******************************/ /************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/ /************************** Variable Definitions *****************************/
extern XGpioPs_Config XGpioPs_ConfigTable[]; extern XGpioPs_Config XGpioPs_ConfigTable[XPAR_XGPIOPS_NUM_INSTANCES];
/*****************************************************************************/ /*****************************************************************************/
/** /**
@ -86,12 +86,12 @@ XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId)
XGpioPs_Config *CfgPtr = NULL; XGpioPs_Config *CfgPtr = NULL;
u32 Index; u32 Index;
for (Index = 0; Index < XPAR_XGPIOPS_NUM_INSTANCES; Index++) { for (Index = 0U; Index < (u32)XPAR_XGPIOPS_NUM_INSTANCES; Index++) {
if (XGpioPs_ConfigTable[Index].DeviceId == DeviceId) { if (XGpioPs_ConfigTable[Index].DeviceId == DeviceId) {
CfgPtr = &XGpioPs_ConfigTable[Index]; CfgPtr = &XGpioPs_ConfigTable[Index];
break; break;
} }
} }
return CfgPtr; return (XGpioPs_Config *)CfgPtr;
} }