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axipmon : Modified code for MISRA-C:2012 Compliance.

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This patch modifies the code according to MISRA-C:2012
guidelines.

Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
This commit is contained in:
Venkata Naga Sai Krishna Kolapalli 2015-07-02 09:19:46 +05:30 • committed by Nava kishore Manne
parent 9873ff6b0a
commit 5d3e47ffad
5 changed files with 441 additions and 433 deletions
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285
XilinxProcessorIPLib/drivers/axipmon/src/xaxipmon.c
View file

@ -118,6 +118,7 @@
* XAxiPmon_SetWriteIdMask, XAxiPmon_SetReadIdMask,
* XAxiPmon_GetWriteIdMask, XAxiPmon_GetReadIdMask
* functions to support Zynq MP APM.
* 6.3 kvn 07/02/15 Modified code according to MISRA-C:2012 guidelines.
* </pre>
*
*****************************************************************************/
@ -158,7 +159,7 @@
* passed as a parameter to the XAxiPmon_CfgInitialize() API.
*
******************************************************************************/
int XAxiPmon_CfgInitialize(XAxiPmon *InstancePtr, XAxiPmon_Config *ConfigPtr,
s32 XAxiPmon_CfgInitialize(XAxiPmon *InstancePtr, XAxiPmon_Config *ConfigPtr,
u32 EffectiveAddr)
{
/*
@ -197,10 +198,10 @@ int XAxiPmon_CfgInitialize(XAxiPmon *InstancePtr, XAxiPmon_Config *ConfigPtr,
InstancePtr->Config.ScaleFactor = ConfigPtr->ScaleFactor;
if ((ConfigPtr->ModeProfile == ConfigPtr->ModeTrace)
|| ConfigPtr->ModeAdvanced == 1)
|| (ConfigPtr->ModeAdvanced == 1U))
{
InstancePtr->Mode = XAPM_MODE_ADVANCED;
} else if (ConfigPtr->ModeTrace == 1) {
} else if (ConfigPtr->ModeTrace == 1U) {
InstancePtr->Mode = XAPM_MODE_TRACE;
} else {
InstancePtr->Mode = XAPM_MODE_PROFILE;
@ -216,10 +217,10 @@ int XAxiPmon_CfgInitialize(XAxiPmon *InstancePtr, XAxiPmon_Config *ConfigPtr,
*/
/* Advanced and Profile */
if(InstancePtr->Mode == XAPM_MODE_ADVANCED ||
InstancePtr->Mode == XAPM_MODE_PROFILE)
if((InstancePtr->Mode == XAPM_MODE_ADVANCED) ||
(InstancePtr->Mode == XAPM_MODE_PROFILE))
{
XAxiPmon_ResetMetricCounter(InstancePtr);
(void)XAxiPmon_ResetMetricCounter(InstancePtr);
}
/* Advanced */
if(InstancePtr->Mode == XAPM_MODE_ADVANCED)
@ -227,10 +228,10 @@ int XAxiPmon_CfgInitialize(XAxiPmon *InstancePtr, XAxiPmon_Config *ConfigPtr,
XAxiPmon_ResetGlobalClkCounter(InstancePtr);
}
/* Advanced and Trace */
if(InstancePtr->Mode == XAPM_MODE_ADVANCED ||
InstancePtr->Mode == XAPM_MODE_TRACE)
if((InstancePtr->Mode == XAPM_MODE_ADVANCED) ||
(InstancePtr->Mode == XAPM_MODE_TRACE))
{
XAxiPmon_ResetFifo(InstancePtr);
(void)XAxiPmon_ResetFifo(InstancePtr);
}
return XST_SUCCESS;
}
@ -249,7 +250,7 @@ int XAxiPmon_CfgInitialize(XAxiPmon *InstancePtr, XAxiPmon_Config *ConfigPtr,
* @note None.
*
******************************************************************************/
int XAxiPmon_ResetMetricCounter(XAxiPmon *InstancePtr)
s32 XAxiPmon_ResetMetricCounter(XAxiPmon *InstancePtr)
{
u32 RegValue;
@ -331,7 +332,7 @@ void XAxiPmon_ResetGlobalClkCounter(XAxiPmon *InstancePtr)
* @note None.
*
******************************************************************************/
int XAxiPmon_ResetFifo(XAxiPmon *InstancePtr)
s32 XAxiPmon_ResetFifo(XAxiPmon *InstancePtr)
{
u32 RegValue;
@ -344,7 +345,7 @@ int XAxiPmon_ResetFifo(XAxiPmon *InstancePtr)
Xil_AssertNonvoid(InstancePtr->Mode != XAPM_MODE_PROFILE);
/* Check Event Logging is enabled in Hardware */
if((InstancePtr->Config.IsEventLog == 0) &&
if((InstancePtr->Config.IsEventLog == 0U) &&
(InstancePtr->Mode == XAPM_MODE_ADVANCED))
{
/*Event logging not enabled in Hardware*/
@ -401,10 +402,10 @@ void XAxiPmon_SetIncrementerRange(XAxiPmon *InstancePtr, u8 IncrementerNum,
/*
* Write to the specified Range register
*/
RegValue = RangeUpper << 16;
RegValue = (u32)RangeUpper << 16;
RegValue |= RangeLower;
XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress,
(XAPM_RANGE0_OFFSET + (IncrementerNum * 16)),
((u32)XAPM_RANGE0_OFFSET + ((u32)IncrementerNum * (u32)16)),
RegValue);
}
@ -440,10 +441,10 @@ void XAxiPmon_GetIncrementerRange(XAxiPmon *InstancePtr, u8 IncrementerNum,
Xil_AssertVoid(IncrementerNum < XAPM_MAX_COUNTERS);
RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
(XAPM_RANGE0_OFFSET + (IncrementerNum * 16)));
((u32)XAPM_RANGE0_OFFSET + ((u32)IncrementerNum * (u32)16)));
*RangeLower = RegValue & 0xFFFF;
*RangeUpper = (RegValue >> 16) & 0xFFFF;
*RangeLower = (u16)(RegValue & 0x0000FFFFU);
*RangeUpper = (u16)((RegValue >> 16) & 0x0000FFFFU);
}
/****************************************************************************/
@ -528,7 +529,7 @@ void XAxiPmon_GetSampleInterval(XAxiPmon *InstancePtr, u32 *SampleInterval)
* @note None.
*
*****************************************************************************/
int XAxiPmon_SetMetrics(XAxiPmon *InstancePtr, u8 Slot, u8 Metrics,
s32 XAxiPmon_SetMetrics(XAxiPmon *InstancePtr, u8 Slot, u8 Metrics,
u8 CounterNum)
{
u32 RegValue;
@ -545,48 +546,48 @@ int XAxiPmon_SetMetrics(XAxiPmon *InstancePtr, u8 Slot, u8 Metrics,
Xil_AssertNonvoid(CounterNum < XAPM_MAX_COUNTERS);
/* Find Mask value to force zero in counternum byte range */
if (CounterNum == 0 || CounterNum == 4 || CounterNum == 8) {
Mask = 0xFFFFFF00;
if ((CounterNum == 0U) || (CounterNum == 4U) || (CounterNum == 8U)) {
Mask = 0xFFFFFF00U;
}
else if (CounterNum == 1 || CounterNum == 5 || CounterNum == 9) {
Mask = 0xFFFF00FF;
else if ((CounterNum == 1U) || (CounterNum == 5U) || (CounterNum == 9U)) {
Mask = 0xFFFF00FFU;
}
else if (CounterNum == 2 || CounterNum == 6) {
Mask = 0xFF00FFFF;
else if ((CounterNum == 2U) || (CounterNum == 6U)) {
Mask = 0xFF00FFFFU;
}
else {
Mask = 0x00FFFFFF;
Mask = 0x00FFFFFFU;
}
if(CounterNum <= 3) {
if(CounterNum <= 3U) {
RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
XAPM_MSR0_OFFSET);
RegValue = RegValue & Mask;
RegValue = RegValue | (Metrics << (CounterNum * 8));
RegValue = RegValue | (Slot << (CounterNum * 8 + 5));
RegValue = RegValue | ((u32)Metrics << (CounterNum * (u8)8));
RegValue = RegValue | ((u32)Slot << ((CounterNum * (u8)8) + (u8)5));
XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress,
XAPM_MSR0_OFFSET,RegValue);
(u32)XAPM_MSR0_OFFSET,RegValue);
}
else if((CounterNum >= 4) && (CounterNum <= 7)) {
CounterNum = CounterNum - 4;
else if((CounterNum >= 4U) && (CounterNum <= 7U)) {
CounterNum = CounterNum - 4U;
RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
XAPM_MSR1_OFFSET);
(u32)XAPM_MSR1_OFFSET);
RegValue = RegValue & Mask;
RegValue = RegValue | (Metrics << (CounterNum * 8));
RegValue = RegValue | (Slot << (CounterNum * 8 + 5));
RegValue = RegValue | ((u32)Metrics << (CounterNum * (u8)8));
RegValue = RegValue | ((u32)Slot << ((CounterNum * (u8)8) + (u8)5));
XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress,
XAPM_MSR1_OFFSET,RegValue);
}
else {
CounterNum = CounterNum - 8;
CounterNum = CounterNum - 8U;
RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
XAPM_MSR2_OFFSET);
RegValue = RegValue & Mask;
RegValue = RegValue | (Metrics << (CounterNum * 8));
RegValue = RegValue | (Slot << (CounterNum * 8 + 5));
RegValue = RegValue | ((u32)Metrics << (CounterNum * (u8)8));
RegValue = RegValue | ((u32)Slot << ((CounterNum * (u8)8) + (u8)5));
XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress,
XAPM_MSR2_OFFSET,RegValue);
}
@ -612,7 +613,7 @@ int XAxiPmon_SetMetrics(XAxiPmon *InstancePtr, u8 Slot, u8 Metrics,
* @note None.
*
*****************************************************************************/
int XAxiPmon_GetMetrics(XAxiPmon *InstancePtr, u8 CounterNum, u8 *Metrics,
s32 XAxiPmon_GetMetrics(XAxiPmon *InstancePtr, u8 CounterNum, u8 *Metrics,
u8 *Slot)
{
u32 RegValue;
@ -624,26 +625,26 @@ int XAxiPmon_GetMetrics(XAxiPmon *InstancePtr, u8 CounterNum, u8 *Metrics,
Xil_AssertNonvoid(InstancePtr->Mode == XAPM_MODE_ADVANCED);
Xil_AssertNonvoid(CounterNum <= XAPM_MAX_COUNTERS);
if(CounterNum <= 3) {
if(CounterNum <= 3U) {
RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
XAPM_MSR0_OFFSET);
*Metrics = (RegValue >> (CounterNum * 8)) & 0x1F;
*Slot = (RegValue >> (CounterNum * 8 + 5)) & 0x7;
*Metrics = (u8)(RegValue >> (CounterNum * (u8)8)) & 0x1FU;
*Slot = (u8)(RegValue >> ((CounterNum * (u8)8) + (u8)5)) & 0x07U;
}
else if((CounterNum >= 4) && (CounterNum <= 7)) {
CounterNum = CounterNum - 4;
else if((CounterNum >= 4U) && (CounterNum <= 7U)) {
CounterNum = CounterNum - 4U;
RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
XAPM_MSR1_OFFSET);
*Metrics = (RegValue >> (CounterNum * 8)) & 0x1F;
*Slot = (RegValue >> (CounterNum * 8 + 5)) & 0x7;
*Metrics = (u8)(RegValue >> (CounterNum * (u8)8)) & 0x1FU;
*Slot = (u8)(RegValue >> ((CounterNum * (u8)8) + (u8)5)) & 0x07U;
}
else {
CounterNum = CounterNum - 8;
CounterNum = CounterNum - 8U;
RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
XAPM_MSR2_OFFSET);
*Metrics = (RegValue >> (CounterNum * 8)) & 0x1F;
*Slot = (RegValue >> (CounterNum * 8 + 5)) & 0x7;
*Metrics = (u8)(RegValue >> (CounterNum * (u8)8)) & 0x1FU;
*Slot = (u8)(RegValue >> ((CounterNum * (u8)8) + (u8)5)) & 0x07U;
}
return XST_SUCCESS;
}
@ -674,8 +675,8 @@ void XAxiPmon_GetGlobalClkCounter(XAxiPmon *InstancePtr,u32 *CntHighValue,
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(InstancePtr->Mode == XAPM_MODE_ADVANCED);
*CntHighValue = 0x0;
*CntLowValue = 0x0;
*CntHighValue = 0x0U;
*CntLowValue = 0x0U;
/*
* If Counter width is 64 bit then Counter Value has to be
@ -720,25 +721,26 @@ u32 XAxiPmon_GetMetricCounter(XAxiPmon *InstancePtr, u32 CounterNum)
Xil_AssertNonvoid(InstancePtr->Mode != XAPM_MODE_TRACE);
Xil_AssertNonvoid(CounterNum < XAPM_MAX_COUNTERS_PROFILE);
if (CounterNum < 10 ) {
if (CounterNum < 10U ) {
RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
(XAPM_MC0_OFFSET + (CounterNum * 16)));
((u32)XAPM_MC0_OFFSET + (CounterNum * (u32)16)));
}
else if (CounterNum >= 10 && CounterNum < 12) {
else if ((CounterNum >= 10U) && (CounterNum < 12U)) {
RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
(XAPM_MC10_OFFSET + ((CounterNum - 10) * 16)));
((u32)XAPM_MC10_OFFSET + ((CounterNum - (u32)10) * (u32)16)));
}
else if (CounterNum >= 12 && CounterNum < 24) {
else if ((CounterNum >= 12U) && (CounterNum < 24U)) {
RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
(XAPM_MC12_OFFSET + ((CounterNum - 12) * 16)));
((u32)XAPM_MC12_OFFSET + ((CounterNum - (u32)12) * (u32)16)));
}
else if (CounterNum >= 24 && CounterNum < 36) {
else if ((CounterNum >= 24U) && (CounterNum < 36U)) {
RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
(XAPM_MC24_OFFSET + ((CounterNum - 24) * 16)));
((u32)XAPM_MC24_OFFSET + ((CounterNum - (u32)24) * (u32)16)));
}
else
else {
RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
(XAPM_MC36_OFFSET + ((CounterNum - 36) * 16)));
((u32)XAPM_MC36_OFFSET + ((CounterNum - (u32)36) * (u32)16)));
}
return RegValue;
}
@ -770,29 +772,30 @@ u32 XAxiPmon_GetSampledMetricCounter(XAxiPmon *InstancePtr, u32 CounterNum)
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(InstancePtr->Mode != XAPM_MODE_TRACE);
Xil_AssertNonvoid(CounterNum < XAPM_MAX_COUNTERS_PROFILE);
Xil_AssertNonvoid(InstancePtr->Mode == XAPM_MODE_PROFILE ||
Xil_AssertNonvoid((InstancePtr->Mode == XAPM_MODE_PROFILE) ||
((InstancePtr->Mode == XAPM_MODE_ADVANCED) &&
(InstancePtr->Config.HaveSampledCounters == 1)));
(InstancePtr->Config.HaveSampledCounters == 1U)));
if (CounterNum < 10 ) {
if (CounterNum < 10U ) {
RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
(XAPM_SMC0_OFFSET + (CounterNum * 16)));
((u32)XAPM_SMC0_OFFSET + (CounterNum * (u32)16)));
}
else if (CounterNum >= 10 && CounterNum < 12) {
else if ((CounterNum >= 10U) && (CounterNum < 12U)) {
RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
(XAPM_SMC10_OFFSET + ((CounterNum - 10) * 16)));
((u32)XAPM_SMC10_OFFSET + ((CounterNum - (u32)10) * (u32)16)));
}
else if (CounterNum >= 12 && CounterNum < 24) {
else if ((CounterNum >= 12U) && (CounterNum < 24U)) {
RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
(XAPM_SMC12_OFFSET + ((CounterNum - 12) * 16)));
((u32)XAPM_SMC12_OFFSET + ((CounterNum - (u32)12) * (u32)16)));
}
else if (CounterNum >= 24 && CounterNum < 36) {
else if ((CounterNum >= 24U) && (CounterNum < 36U)) {
RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
(XAPM_SMC24_OFFSET + ((CounterNum - 24) * 16)));
((u32)XAPM_SMC24_OFFSET + ((CounterNum - (u32)24) * (u32)16)));
}
else
else {
RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
(XAPM_SMC36_OFFSET + ((CounterNum - 36) * 16)));
((u32)XAPM_SMC36_OFFSET + ((CounterNum - (u32)36) * (u32)16)));
}
return RegValue;
}
@ -823,12 +826,12 @@ u32 XAxiPmon_GetIncrementer(XAxiPmon *InstancePtr, u32 IncrementerNum)
*/
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(InstancePtr->Mode == XAPM_MODE_ADVANCED &&
InstancePtr->Config.IsEventCount == 1);
Xil_AssertNonvoid((InstancePtr->Mode == XAPM_MODE_ADVANCED) &&
(InstancePtr->Config.IsEventCount == 1U));
Xil_AssertNonvoid(IncrementerNum < XAPM_MAX_COUNTERS);
RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
(XAPM_INC0_OFFSET + (IncrementerNum * 16)));
((u32)XAPM_INC0_OFFSET + (IncrementerNum * (u32)16)));
return RegValue;
}
@ -859,13 +862,13 @@ u32 XAxiPmon_GetSampledIncrementer(XAxiPmon *InstancePtr, u32 IncrementerNum)
*/
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(InstancePtr->Mode == XAPM_MODE_ADVANCED &&
InstancePtr->Config.IsEventCount == 1 &&
InstancePtr->Config.HaveSampledCounters == 1);
Xil_AssertNonvoid((InstancePtr->Mode == XAPM_MODE_ADVANCED) &&
(InstancePtr->Config.IsEventCount == 1U) &&
(InstancePtr->Config.HaveSampledCounters == 1U));
Xil_AssertNonvoid(IncrementerNum < XAPM_MAX_COUNTERS);
RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
(XAPM_SINC0_OFFSET + (IncrementerNum * 16)));
((u32)XAPM_SINC0_OFFSET + (IncrementerNum * (u32)16)));
return RegValue;
}
@ -893,7 +896,7 @@ void XAxiPmon_SetSwDataReg(XAxiPmon *InstancePtr, u32 SwData)
/*
* Set Software-written Data Register
*/
XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_SWD_OFFSET,
XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, (u32)XAPM_SWD_OFFSET,
SwData);
}
@ -945,7 +948,7 @@ u32 XAxiPmon_GetSwDataReg(XAxiPmon *InstancePtr)
* @note None
*
******************************************************************************/
int XAxiPmon_StartEventLog(XAxiPmon *InstancePtr, u32 FlagEnables)
s32 XAxiPmon_StartEventLog(XAxiPmon *InstancePtr, u32 FlagEnables)
{
u32 RegValue;
@ -954,24 +957,24 @@ int XAxiPmon_StartEventLog(XAxiPmon *InstancePtr, u32 FlagEnables)
*/
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(InstancePtr->Mode == XAPM_MODE_TRACE ||
Xil_AssertNonvoid((InstancePtr->Mode == XAPM_MODE_TRACE) ||
((InstancePtr->Mode == XAPM_MODE_ADVANCED) &&
(InstancePtr->Config.IsEventLog == 1)));
(InstancePtr->Config.IsEventLog == 1U)));
/* Read current register value */
RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
XAPM_CTL_OFFSET);
(u32)XAPM_CTL_OFFSET);
/* Flag Enable register is present only in Advanced Mode */
if(InstancePtr->Mode == XAPM_MODE_ADVANCED)
{
/* Now write to flag enables register */
XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress,
XAPM_FEC_OFFSET, FlagEnables);
(u32)XAPM_FEC_OFFSET, FlagEnables);
}
/* Write the new value to the Control register to
* enable event logging */
XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET,
XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, (u32)XAPM_CTL_OFFSET,
RegValue | XAPM_CR_EVENTLOG_ENABLE_MASK);
return XST_SUCCESS;
@ -990,7 +993,7 @@ int XAxiPmon_StartEventLog(XAxiPmon *InstancePtr, u32 FlagEnables)
* @note None
*
******************************************************************************/
int XAxiPmon_StopEventLog(XAxiPmon *InstancePtr)
s32 XAxiPmon_StopEventLog(XAxiPmon *InstancePtr)
{
u32 RegValue;
@ -999,17 +1002,17 @@ int XAxiPmon_StopEventLog(XAxiPmon *InstancePtr)
*/
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(InstancePtr->Mode == XAPM_MODE_TRACE ||
Xil_AssertNonvoid((InstancePtr->Mode == XAPM_MODE_TRACE) ||
((InstancePtr->Mode == XAPM_MODE_ADVANCED) &&
(InstancePtr->Config.IsEventLog == 1)));
(InstancePtr->Config.IsEventLog == 1U)));
/* Read current register value */
RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
XAPM_CTL_OFFSET);
(u32)XAPM_CTL_OFFSET);
/* Write the new value to the Control register to disable
* event logging */
XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET,
XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, (u32)XAPM_CTL_OFFSET,
RegValue & ~XAPM_CR_EVENTLOG_ENABLE_MASK);
return XST_SUCCESS;
@ -1031,7 +1034,7 @@ int XAxiPmon_StopEventLog(XAxiPmon *InstancePtr)
*
* @note None
******************************************************************************/
int XAxiPmon_StartCounters(XAxiPmon *InstancePtr, u32 SampleInterval)
s32 XAxiPmon_StartCounters(XAxiPmon *InstancePtr, u32 SampleInterval)
{
u32 RegValue;
@ -1040,13 +1043,13 @@ int XAxiPmon_StartCounters(XAxiPmon *InstancePtr, u32 SampleInterval)
*/
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(InstancePtr->Mode == XAPM_MODE_PROFILE ||
Xil_AssertNonvoid((InstancePtr->Mode == XAPM_MODE_PROFILE) ||
((InstancePtr->Mode == XAPM_MODE_ADVANCED) &&
(InstancePtr->Config.IsEventCount == 1)));
(InstancePtr->Config.IsEventCount == 1U)));
/* Read current register value */
RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
XAPM_CTL_OFFSET);
(u32)XAPM_CTL_OFFSET);
/* Globlal Clock Counter is present in Advanced mode only */
if(InstancePtr->Mode == XAPM_MODE_ADVANCED)
{
@ -1057,7 +1060,7 @@ int XAxiPmon_StartCounters(XAxiPmon *InstancePtr, u32 SampleInterval)
* Write the new value to the Control register to enable
* global clock counter and metric counters
*/
XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET,
XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, (u32)XAPM_CTL_OFFSET,
RegValue | XAPM_CR_MCNTR_ENABLE_MASK);
/* Set, enable, and load sampled counters */
@ -1082,7 +1085,7 @@ int XAxiPmon_StartCounters(XAxiPmon *InstancePtr, u32 SampleInterval)
* @note None
*
******************************************************************************/
int XAxiPmon_StopCounters(XAxiPmon *InstancePtr)
s32 XAxiPmon_StopCounters(XAxiPmon *InstancePtr)
{
u32 RegValue;
@ -1091,13 +1094,13 @@ int XAxiPmon_StopCounters(XAxiPmon *InstancePtr)
*/
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(InstancePtr->Mode == XAPM_MODE_PROFILE ||
Xil_AssertNonvoid((InstancePtr->Mode == XAPM_MODE_PROFILE) ||
((InstancePtr->Mode == XAPM_MODE_ADVANCED) &&
(InstancePtr->Config.IsEventCount == 1)));
(InstancePtr->Config.IsEventCount == 1U)));
/* Read current register value */
RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
XAPM_CTL_OFFSET);
(u32)XAPM_CTL_OFFSET);
/* Globlal Clock Counter is present in Advanced mode only */
if(InstancePtr->Mode == XAPM_MODE_ADVANCED)
{
@ -1108,8 +1111,8 @@ int XAxiPmon_StopCounters(XAxiPmon *InstancePtr)
* Write the new value to the Control register to disable
* global clock counter and metric counters
*/
XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET,
RegValue & ~XAPM_CR_MCNTR_ENABLE_MASK);
XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, (u32)XAPM_CTL_OFFSET,
RegValue & ~XAPM_CR_MCNTR_ENABLE_MASK);
return XST_SUCCESS;
}
@ -1135,9 +1138,9 @@ void XAxiPmon_EnableMetricsCounter(XAxiPmon *InstancePtr)
*/
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(InstancePtr->Mode == XAPM_MODE_PROFILE ||
Xil_AssertVoid((InstancePtr->Mode == XAPM_MODE_PROFILE) ||
((InstancePtr->Mode == XAPM_MODE_ADVANCED) &&
(InstancePtr->Config.IsEventCount == 1)));
(InstancePtr->Config.IsEventCount == 1U)));
RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
XAPM_CTL_OFFSET);
@ -1165,14 +1168,14 @@ void XAxiPmon_DisableMetricsCounter(XAxiPmon *InstancePtr)
*/
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(InstancePtr->Mode == XAPM_MODE_PROFILE ||
Xil_AssertVoid((InstancePtr->Mode == XAPM_MODE_PROFILE) ||
((InstancePtr->Mode == XAPM_MODE_ADVANCED) &&
(InstancePtr->Config.IsEventCount == 1)));
(InstancePtr->Config.IsEventCount == 1U)));
RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
XAPM_CTL_OFFSET);
(u32)XAPM_CTL_OFFSET);
XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET,
XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, (u32)XAPM_CTL_OFFSET,
RegVal & ~(XAPM_CR_MCNTR_ENABLE_MASK));
}
@ -1207,17 +1210,17 @@ void XAxiPmon_SetLogEnableRanges(XAxiPmon *InstancePtr, u32 CounterNum,
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(CounterNum < XAPM_MAX_COUNTERS);
Xil_AssertVoid((InstancePtr->Mode == XAPM_MODE_ADVANCED) &&
(InstancePtr->Config.IsEventCount == 1));
(InstancePtr->Config.IsEventCount == 1U));
/*
* Write the specified Ranges to corresponding Metric Counter Log
* Enable Register
*/
RegValue = RangeUpper << 16;
RegValue = (u32)RangeUpper << 16;
RegValue |= RangeLower;
XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress,
(XAPM_MC0LOGEN_OFFSET + (CounterNum * 16)), RegValue);
((u32)XAPM_MC0LOGEN_OFFSET + (CounterNum * (u32)16)), RegValue);
}
@ -1255,14 +1258,14 @@ void XAxiPmon_GetLogEnableRanges(XAxiPmon *InstancePtr, u32 CounterNum,
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(CounterNum < XAPM_MAX_COUNTERS);
Xil_AssertVoid((InstancePtr->Mode == XAPM_MODE_ADVANCED) &&
(InstancePtr->Config.IsEventCount == 1));
(InstancePtr->Config.IsEventCount == 1U));
RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
(XAPM_MC0LOGEN_OFFSET + (CounterNum * 16)));
((u32)XAPM_MC0LOGEN_OFFSET + (CounterNum * (u32)16)));
*RangeLower = RegValue & 0xFFFF;
*RangeUpper = (RegValue >> 16) & 0xFFFF;
*RangeLower = (u16)RegValue & 0xFFFFU;
*RangeUpper = (u16)(RegValue >> 16) & 0xFFFFU;
}
/*****************************************************************************/
@ -1286,9 +1289,9 @@ void XAxiPmon_EnableEventLog(XAxiPmon *InstancePtr)
*/
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(InstancePtr->Mode == XAPM_MODE_TRACE ||
Xil_AssertVoid((InstancePtr->Mode == XAPM_MODE_TRACE) ||
((InstancePtr->Mode == XAPM_MODE_ADVANCED) &&
(InstancePtr->Config.IsEventLog == 1)));
(InstancePtr->Config.IsEventLog == 1U)));
RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
XAPM_CTL_OFFSET);
@ -1533,7 +1536,7 @@ void XAxiPmon_SetWriteId(XAxiPmon *InstancePtr, u32 WriteId)
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
if (InstancePtr->Config.Is32BitFiltering == 0)
if (InstancePtr->Config.Is32BitFiltering == 0U)
{
RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
XAPM_ID_OFFSET);
@ -1572,7 +1575,7 @@ void XAxiPmon_SetReadId(XAxiPmon *InstancePtr, u32 ReadId)
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
if (InstancePtr->Config.Is32BitFiltering == 0)
if (InstancePtr->Config.Is32BitFiltering == 0U)
{
RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
XAPM_ID_OFFSET);
@ -1612,7 +1615,7 @@ u32 XAxiPmon_GetWriteId(XAxiPmon *InstancePtr)
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
if (InstancePtr->Config.Is32BitFiltering == 0)
if (InstancePtr->Config.Is32BitFiltering == 0U)
{
RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
XAPM_ID_OFFSET);
@ -1651,7 +1654,7 @@ u32 XAxiPmon_GetReadId(XAxiPmon *InstancePtr)
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
if (InstancePtr->Config.Is32BitFiltering == 0)
if (InstancePtr->Config.Is32BitFiltering == 0U)
{
RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
XAPM_ID_OFFSET);
@ -1843,14 +1846,14 @@ u8 XAxiPmon_GetWrLatencyStart(XAxiPmon *InstancePtr)
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
XAPM_CTL_OFFSET);
RegVal = (u8)XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
(u32)XAPM_CTL_OFFSET);
RegVal = RegVal & XAPM_CR_WRLATENCY_START_MASK;
if (RegVal != XAPM_LATENCY_ADDR_ISSUE) {
return XAPM_LATENCY_ADDR_ACCEPT;
return (u8)XAPM_LATENCY_ADDR_ACCEPT;
}
else {
return XAPM_LATENCY_ADDR_ISSUE;
return (u8)XAPM_LATENCY_ADDR_ISSUE;
}
}
@ -1877,14 +1880,14 @@ u8 XAxiPmon_GetWrLatencyEnd(XAxiPmon *InstancePtr)
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
XAPM_CTL_OFFSET);
RegVal = (u8)XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
(u32)XAPM_CTL_OFFSET);
RegVal = RegVal & XAPM_CR_WRLATENCY_END_MASK;
if (RegVal != XAPM_LATENCY_LASTWR) {
return XAPM_LATENCY_FIRSTWR;
return (u8)XAPM_LATENCY_FIRSTWR;
}
else {
return XAPM_LATENCY_LASTWR;
return (u8)XAPM_LATENCY_LASTWR;
}
}
@ -1911,15 +1914,15 @@ u8 XAxiPmon_GetRdLatencyStart(XAxiPmon *InstancePtr)
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
XAPM_CTL_OFFSET);
RegVal = (u8)XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
(u32)XAPM_CTL_OFFSET);
RegVal = RegVal & XAPM_CR_RDLATENCY_START_MASK;
if (RegVal != XAPM_LATENCY_ADDR_ISSUE) {
return XAPM_LATENCY_ADDR_ACCEPT;
return (u8)XAPM_LATENCY_ADDR_ACCEPT;
}
else {
return XAPM_LATENCY_ADDR_ISSUE;
return (u8)XAPM_LATENCY_ADDR_ISSUE;
}
}
@ -1946,14 +1949,14 @@ u8 XAxiPmon_GetRdLatencyEnd(XAxiPmon *InstancePtr)
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
XAPM_CTL_OFFSET);
RegVal = (u8)XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
(u32)XAPM_CTL_OFFSET);
RegVal = RegVal & XAPM_CR_RDLATENCY_END_MASK;
if (RegVal != XAPM_LATENCY_LASTRD) {
return XAPM_LATENCY_FIRSTRD;
return (u8)XAPM_LATENCY_FIRSTRD;
}
else {
return XAPM_LATENCY_LASTRD;
return (u8)XAPM_LATENCY_LASTRD;
}
}
@ -1983,7 +1986,7 @@ void XAxiPmon_SetWriteIdMask(XAxiPmon *InstancePtr, u32 WrMask)
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
if (InstancePtr->Config.Is32BitFiltering == 0)
if (InstancePtr->Config.Is32BitFiltering == 0U)
{
RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
XAPM_IDMASK_OFFSET);
@ -2022,7 +2025,7 @@ void XAxiPmon_SetReadIdMask(XAxiPmon *InstancePtr, u32 RdMask)
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
if (InstancePtr->Config.Is32BitFiltering == 0)
if (InstancePtr->Config.Is32BitFiltering == 0U)
{
RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
XAPM_IDMASK_OFFSET);
@ -2063,7 +2066,7 @@ u32 XAxiPmon_GetWriteIdMask(XAxiPmon *InstancePtr)
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
if (InstancePtr->Config.Is32BitFiltering == 0)
if (InstancePtr->Config.Is32BitFiltering == 0U)
{
RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
XAPM_IDMASK_OFFSET);
@ -2103,7 +2106,7 @@ u32 XAxiPmon_GetReadIdMask(XAxiPmon *InstancePtr)
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
if (InstancePtr->Config.Is32BitFiltering == 0)
if (InstancePtr->Config.Is32BitFiltering == 0U)
{
RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress,
XAPM_IDMASK_OFFSET);

189
XilinxProcessorIPLib/drivers/axipmon/src/xaxipmon.h
View file

@ -250,6 +250,7 @@
* Added XAPM_RID_OFFSET and XAPM_RIDMASK_OFFSET in
* xaxipmon_hw.h
*
* 6.3 kvn 07/02/15 Modified code according to MISRA-C:2012 guidelines.
* </pre>
*
*****************************************************************************/
@ -275,8 +276,8 @@ extern "C" {
*
* @{
*/
#define XAPM_MAX_COUNTERS 10 /**< Maximum number of Counters */
#define XAPM_MAX_COUNTERS_PROFILE 48 /**< Maximum number of Counters */
#define XAPM_MAX_COUNTERS 10U /**< Maximum number of Counters */
#define XAPM_MAX_COUNTERS_PROFILE 48U /**< Maximum number of Counters */
/*@}*/
@ -287,16 +288,16 @@ extern "C" {
* @{
*/
#define XAPM_METRIC_COUNTER_0 0 /**< Metric Counter 0 Register Index */
#define XAPM_METRIC_COUNTER_1 1 /**< Metric Counter 1 Register Index */
#define XAPM_METRIC_COUNTER_2 2 /**< Metric Counter 2 Register Index */
#define XAPM_METRIC_COUNTER_3 3 /**< Metric Counter 3 Register Index */
#define XAPM_METRIC_COUNTER_4 4 /**< Metric Counter 4 Register Index */
#define XAPM_METRIC_COUNTER_5 5 /**< Metric Counter 5 Register Index */
#define XAPM_METRIC_COUNTER_6 6 /**< Metric Counter 6 Register Index */
#define XAPM_METRIC_COUNTER_7 7 /**< Metric Counter 7 Register Index */
#define XAPM_METRIC_COUNTER_8 8 /**< Metric Counter 8 Register Index */
#define XAPM_METRIC_COUNTER_9 9 /**< Metric Counter 9 Register Index */
#define XAPM_METRIC_COUNTER_0 0U /**< Metric Counter 0 Register Index */
#define XAPM_METRIC_COUNTER_1 1U /**< Metric Counter 1 Register Index */
#define XAPM_METRIC_COUNTER_2 2U /**< Metric Counter 2 Register Index */
#define XAPM_METRIC_COUNTER_3 3U /**< Metric Counter 3 Register Index */
#define XAPM_METRIC_COUNTER_4 4U /**< Metric Counter 4 Register Index */
#define XAPM_METRIC_COUNTER_5 5U /**< Metric Counter 5 Register Index */
#define XAPM_METRIC_COUNTER_6 6U /**< Metric Counter 6 Register Index */
#define XAPM_METRIC_COUNTER_7 7U /**< Metric Counter 7 Register Index */
#define XAPM_METRIC_COUNTER_8 8U /**< Metric Counter 8 Register Index */
#define XAPM_METRIC_COUNTER_9 9U /**< Metric Counter 9 Register Index */
/*@}*/
@ -306,16 +307,16 @@ extern "C" {
* @{
*/
#define XAPM_INCREMENTER_0 0 /**< Metric Counter 0 Register Index */
#define XAPM_INCREMENTER_1 1 /**< Metric Counter 0 Register Index */
#define XAPM_INCREMENTER_2 2 /**< Metric Counter 0 Register Index */
#define XAPM_INCREMENTER_3 3 /**< Metric Counter 0 Register Index */
#define XAPM_INCREMENTER_4 4 /**< Metric Counter 0 Register Index */
#define XAPM_INCREMENTER_5 5 /**< Metric Counter 0 Register Index */
#define XAPM_INCREMENTER_6 6 /**< Metric Counter 0 Register Index */
#define XAPM_INCREMENTER_7 7 /**< Metric Counter 0 Register Index */
#define XAPM_INCREMENTER_8 8 /**< Metric Counter 0 Register Index */
#define XAPM_INCREMENTER_9 9 /**< Metric Counter 0 Register Index */
#define XAPM_INCREMENTER_0 0U /**< Metric Counter 0 Register Index */
#define XAPM_INCREMENTER_1 1U /**< Metric Counter 0 Register Index */
#define XAPM_INCREMENTER_2 2U /**< Metric Counter 0 Register Index */
#define XAPM_INCREMENTER_3 3U /**< Metric Counter 0 Register Index */
#define XAPM_INCREMENTER_4 4U /**< Metric Counter 0 Register Index */
#define XAPM_INCREMENTER_5 5U /**< Metric Counter 0 Register Index */
#define XAPM_INCREMENTER_6 6U /**< Metric Counter 0 Register Index */
#define XAPM_INCREMENTER_7 7U /**< Metric Counter 0 Register Index */
#define XAPM_INCREMENTER_8 8U /**< Metric Counter 0 Register Index */
#define XAPM_INCREMENTER_9 9U /**< Metric Counter 0 Register Index */
/*@}*/
@ -324,30 +325,30 @@ extern "C" {
* @{
*/
#define XAPM_METRIC_SET_0 0 /**< Write Transaction Count */
#define XAPM_METRIC_SET_1 1 /**< Read Transaction Count */
#define XAPM_METRIC_SET_2 2 /**< Write Byte Count */
#define XAPM_METRIC_SET_3 3 /**< Read Byte Count */
#define XAPM_METRIC_SET_4 4 /**< Write Beat Count */
#define XAPM_METRIC_SET_5 5 /**< Total Read Latency */
#define XAPM_METRIC_SET_6 6 /**< Total Write Latency */
#define XAPM_METRIC_SET_7 7 /**< Slv_Wr_Idle_Cnt */
#define XAPM_METRIC_SET_8 8 /**< Mst_Rd_Idle_Cnt */
#define XAPM_METRIC_SET_9 9 /**< Num_BValids */
#define XAPM_METRIC_SET_10 10 /**< Num_WLasts */
#define XAPM_METRIC_SET_11 11 /**< Num_RLasts */
#define XAPM_METRIC_SET_12 12 /**< Minimum Write Latency */
#define XAPM_METRIC_SET_13 13 /**< Maximum Write Latency */
#define XAPM_METRIC_SET_14 14 /**< Minimum Read Latency */
#define XAPM_METRIC_SET_15 15 /**< Maximum Read Latency */
#define XAPM_METRIC_SET_16 16 /**< Transfer Cycle Count */
#define XAPM_METRIC_SET_17 17 /**< Packet Count */
#define XAPM_METRIC_SET_18 18 /**< Data Byte Count */
#define XAPM_METRIC_SET_19 19 /**< Position Byte Count */
#define XAPM_METRIC_SET_20 20 /**< Null Byte Count */
#define XAPM_METRIC_SET_21 21 /**< Slv_Idle_Cnt */
#define XAPM_METRIC_SET_22 22 /**< Mst_Idle_Cnt */
#define XAPM_METRIC_SET_30 30 /**< External event count */
#define XAPM_METRIC_SET_0 0U /**< Write Transaction Count */
#define XAPM_METRIC_SET_1 1U /**< Read Transaction Count */
#define XAPM_METRIC_SET_2 2U /**< Write Byte Count */
#define XAPM_METRIC_SET_3 3U /**< Read Byte Count */
#define XAPM_METRIC_SET_4 4U /**< Write Beat Count */
#define XAPM_METRIC_SET_5 5U /**< Total Read Latency */
#define XAPM_METRIC_SET_6 6U /**< Total Write Latency */
#define XAPM_METRIC_SET_7 7U /**< Slv_Wr_Idle_Cnt */
#define XAPM_METRIC_SET_8 8U /**< Mst_Rd_Idle_Cnt */
#define XAPM_METRIC_SET_9 9U /**< Num_BValids */
#define XAPM_METRIC_SET_10 10U /**< Num_WLasts */
#define XAPM_METRIC_SET_11 11U /**< Num_RLasts */
#define XAPM_METRIC_SET_12 12U /**< Minimum Write Latency */
#define XAPM_METRIC_SET_13 13U /**< Maximum Write Latency */
#define XAPM_METRIC_SET_14 14U /**< Minimum Read Latency */
#define XAPM_METRIC_SET_15 15U /**< Maximum Read Latency */
#define XAPM_METRIC_SET_16 16U /**< Transfer Cycle Count */
#define XAPM_METRIC_SET_17 17U /**< Packet Count */
#define XAPM_METRIC_SET_18 18U /**< Data Byte Count */
#define XAPM_METRIC_SET_19 19U /**< Position Byte Count */
#define XAPM_METRIC_SET_20 20U /**< Null Byte Count */
#define XAPM_METRIC_SET_21 21U /**< Slv_Idle_Cnt */
#define XAPM_METRIC_SET_22 22U /**< Mst_Idle_Cnt */
#define XAPM_METRIC_SET_30 30U /**< External event count */
/*@}*/
@ -358,7 +359,7 @@ extern "C" {
* @{
*/
#define XAPM_MAX_AGENTS 8 /**< Maximum number of Agents */
#define XAPM_MAX_AGENTS 8U /**< Maximum number of Agents */
/*@}*/
@ -381,16 +382,16 @@ extern "C" {
#define XAPM_FLAG_GCCOVF 0x00100000 /**< Global Clock Counter Overflow
* Flag */
#define XAPM_FLAG_SCLAPSE 0x00200000 /**< Sample Counter Lapse Flag */
#define XAPM_FLAG_MC0 0x00400000 /**< Metric Counter 0 Flag */
#define XAPM_FLAG_MC1 0x00800000 /**< Metric Counter 1 Flag */
#define XAPM_FLAG_MC2 0x01000000 /**< Metric Counter 2 Flag */
#define XAPM_FLAG_MC3 0x02000000 /**< Metric Counter 3 Flag */
#define XAPM_FLAG_MC4 0x04000000 /**< Metric Counter 4 Flag */
#define XAPM_FLAG_MC5 0x08000000 /**< Metric Counter 5 Flag */
#define XAPM_FLAG_MC6 0x10000000 /**< Metric Counter 6 Flag */
#define XAPM_FLAG_MC7 0x20000000 /**< Metric Counter 7 Flag */
#define XAPM_FLAG_MC8 0x40000000 /**< Metric Counter 8 Flag */
#define XAPM_FLAG_MC9 0x80000000 /**< Metric Counter 9 Flag */
#define XAPM_FLAG_MC0 0x00400000U /**< Metric Counter 0 Flag */
#define XAPM_FLAG_MC1 0x00800000U /**< Metric Counter 1 Flag */
#define XAPM_FLAG_MC2 0x01000000U /**< Metric Counter 2 Flag */
#define XAPM_FLAG_MC3 0x02000000U /**< Metric Counter 3 Flag */
#define XAPM_FLAG_MC4 0x04000000U /**< Metric Counter 4 Flag */
#define XAPM_FLAG_MC5 0x08000000U /**< Metric Counter 5 Flag */
#define XAPM_FLAG_MC6 0x10000000U /**< Metric Counter 6 Flag */
#define XAPM_FLAG_MC7 0x20000000U /**< Metric Counter 7 Flag */
#define XAPM_FLAG_MC8 0x40000000U /**< Metric Counter 8 Flag */
#define XAPM_FLAG_MC9 0x80000000U /**< Metric Counter 9 Flag */
/*@}*/
@ -398,17 +399,17 @@ extern "C" {
* @name Macros for Read/Write Latency Start and End points
* @{
*/
#define XAPM_LATENCY_ADDR_ISSUE 0 /**< Address Issue as start
#define XAPM_LATENCY_ADDR_ISSUE 0U /**< Address Issue as start
point for Latency calculation*/
#define XAPM_LATENCY_ADDR_ACCEPT 1 /**< Address Acceptance as start
#define XAPM_LATENCY_ADDR_ACCEPT 1U /**< Address Acceptance as start
point for Latency calculation*/
#define XAPM_LATENCY_LASTRD 0 /**< Last Read as end point for
#define XAPM_LATENCY_LASTRD 0U /**< Last Read as end point for
Latency calculation */
#define XAPM_LATENCY_LASTWR 0 /**< Last Write as end point for
#define XAPM_LATENCY_LASTWR 0U /**< Last Write as end point for
Latency calculation */
#define XAPM_LATENCY_FIRSTRD 1 /**< First Read as end point for
#define XAPM_LATENCY_FIRSTRD 1U /**< First Read as end point for
Latency calculation */
#define XAPM_LATENCY_FIRSTWR 1 /**< First Write as end point for
#define XAPM_LATENCY_FIRSTWR 1U /**< First Write as end point for
Latency calculation */
/*@}*/
@ -418,11 +419,11 @@ extern "C" {
* @{
*/
#define XAPM_MODE_TRACE 2 /**< APM in Trace mode */
#define XAPM_MODE_TRACE 2U /**< APM in Trace mode */
#define XAPM_MODE_PROFILE 1 /**< APM in Profile mode */
#define XAPM_MODE_PROFILE 1U /**< APM in Profile mode */
#define XAPM_MODE_ADVANCED 0 /**< APM in Advanced mode */
#define XAPM_MODE_ADVANCED 0U /**< APM in Advanced mode */
/*@}*/
@ -435,8 +436,8 @@ extern "C" {
typedef struct {
u16 DeviceId; /**< Unique ID of device */
u32 BaseAddress; /**< Device base address */
int GlobalClkCounterWidth; /**< Global Clock Counter Width */
int MetricSampleCounterWidth ; /**< Metric Sample Counters Width */
s32 GlobalClkCounterWidth; /**< Global Clock Counter Width */
s32 MetricSampleCounterWidth ; /**< Metric Sample Counters Width */
u8 IsEventCount; /**< Event Count Enabled 1 - enabled
0 - not enabled */
u8 NumberofSlots; /**< Number of Monitor Slots */
@ -526,7 +527,7 @@ typedef struct {
#define XAxiPmon_IntrEnable(InstancePtr, Mask) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_IE_OFFSET, \
XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
XAPM_IE_OFFSET) | Mask);
XAPM_IE_OFFSET) | (Mask));
/****************************************************************************/
@ -550,7 +551,7 @@ typedef struct {
#define XAxiPmon_IntrDisable(InstancePtr, Mask) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_IE_OFFSET, \
XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
XAPM_IE_OFFSET) | Mask);
XAPM_IE_OFFSET) | (Mask));
/****************************************************************************/
/**
@ -571,7 +572,7 @@ typedef struct {
#define XAxiPmon_IntrClear(InstancePtr, Mask) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_IS_OFFSET, \
XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
XAPM_IS_OFFSET) | Mask);
XAPM_IS_OFFSET) | (Mask));
/****************************************************************************/
/**
@ -600,7 +601,7 @@ typedef struct {
* @return None
*
* @note C-Style signature:
* void XAxiPmon_EnableGlobalClkCounter(XAxiPmon *InstancePtr);
* void XAxiPmon_EnableGlobalClkCounter(XAxiPmon *InstancePtr)
*
*****************************************************************************/
#define XAxiPmon_EnableGlobalClkCounter(InstancePtr) \
@ -618,7 +619,7 @@ typedef struct {
* @return None
*
* @note C-Style signature:
* void XAxiPmon_DisableGlobalClkCounter(XAxiPmon *InstancePtr);
* void XAxiPmon_DisableGlobalClkCounter(XAxiPmon *InstancePtr)
*
*****************************************************************************/
#define XAxiPmon_DisableGlobalClkCounter(InstancePtr) \
@ -637,13 +638,13 @@ typedef struct {
* @return None
*
* @note C-Style signature:
* void XAxiPmon_EnableFlag(XAxiPmon *InstancePtr);
* void XAxiPmon_EnableFlag(XAxiPmon *InstancePtr)
*
*****************************************************************************/
#define XAxiPmon_EnableFlag(InstancePtr, Flag) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_FEC_OFFSET, \
XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
XAPM_FEC_OFFSET) | Flag);
XAPM_FEC_OFFSET) | (Flag));
/****************************************************************************/
/**
@ -655,7 +656,7 @@ typedef struct {
* @return None
*
* @note C-Style signature:
* void XAxiPmon_DisableFlag(XAxiPmon *InstancePtr);
* void XAxiPmon_DisableFlag(XAxiPmon *InstancePtr)
*
*****************************************************************************/
#define XAxiPmon_DisableFlag(InstancePtr, Flag) \
@ -674,7 +675,7 @@ typedef struct {
* @return None
*
* @note C-Style signature:
* void XAxiPmon_LoadSampleIntervalCounter(XAxiPmon *InstancePtr);
* void XAxiPmon_LoadSampleIntervalCounter(XAxiPmon *InstancePtr)
*
*****************************************************************************/
#define XAxiPmon_LoadSampleIntervalCounter(InstancePtr) \
@ -693,7 +694,7 @@ typedef struct {
* @return None
*
* @note C-Style signature:
* void XAxiPmon_EnableSampleIntervalCounter(XAxiPmon *InstancePtr);
* void XAxiPmon_EnableSampleIntervalCounter(XAxiPmon *InstancePtr)
*
*****************************************************************************/
#define XAxiPmon_EnableSampleIntervalCounter(InstancePtr) \
@ -711,7 +712,7 @@ typedef struct {
* @return None
*
* @note C-Style signature:
* void XAxiPmon_DisableSampleIntervalCounter(XAxiPmon *InstancePtr);
* void XAxiPmon_DisableSampleIntervalCounter(XAxiPmon *InstancePtr)
*
*****************************************************************************/
#define XAxiPmon_DisableSampleIntervalCounter(InstancePtr) \
@ -729,7 +730,7 @@ typedef struct {
* @return None
*
* @note C-Style signature:
* void XAxiPmon_EnableMetricCounterReset(XAxiPmon *InstancePtr);
* void XAxiPmon_EnableMetricCounterReset(XAxiPmon *InstancePtr)
*
*****************************************************************************/
#define XAxiPmon_EnableMetricCounterReset(InstancePtr) \
@ -746,7 +747,7 @@ typedef struct {
* @return None
*
* @note C-Style signature:
* void XAxiPmon_DisableMetricCounterReset(XAxiPmon *InstancePtr);
* void XAxiPmon_DisableMetricCounterReset(XAxiPmon *InstancePtr)
*
*****************************************************************************/
#define XAxiPmon_DisableMetricCounterReset(InstancePtr) \
@ -764,7 +765,7 @@ typedef struct {
* @return None
*
* @note C-Style signature:
* void XAxiPmon_EnableIDFilter(XAxiPmon *InstancePtr);
* void XAxiPmon_EnableIDFilter(XAxiPmon *InstancePtr)
*
*****************************************************************************/
#define XAxiPmon_EnableIDFilter(InstancePtr) \
@ -782,7 +783,7 @@ typedef struct {
* @return None
*
* @note C-Style signature:
* void XAxiPmon_DisableIDFilter(XAxiPmon *InstancePtr);
* void XAxiPmon_DisableIDFilter(XAxiPmon *InstancePtr)
*
*****************************************************************************/
#define XAxiPmon_DisableIDFilter(InstancePtr) \
@ -803,7 +804,7 @@ typedef struct {
* read to the current read of sample register.
*
* @note C-Style signature:
* u32 XAxiPmon_SampleMetrics(XAxiPmon *InstancePtr);
* u32 XAxiPmon_SampleMetrics(XAxiPmon *InstancePtr)
*
*****************************************************************************/
#define XAxiPmon_SampleMetrics(InstancePtr) \
@ -820,14 +821,14 @@ XAxiPmon_Config *XAxiPmon_LookupConfig(u16 DeviceId);
/**
* Functions in xaxipmon.c
*/
int XAxiPmon_CfgInitialize(XAxiPmon *InstancePtr,
s32 XAxiPmon_CfgInitialize(XAxiPmon *InstancePtr,
XAxiPmon_Config *ConfigPtr, u32 EffectiveAddr);
int XAxiPmon_ResetMetricCounter(XAxiPmon *InstancePtr);
s32 XAxiPmon_ResetMetricCounter(XAxiPmon *InstancePtr);
void XAxiPmon_ResetGlobalClkCounter(XAxiPmon *InstancePtr);
int XAxiPmon_ResetFifo(XAxiPmon *InstancePtr);
s32 XAxiPmon_ResetFifo(XAxiPmon *InstancePtr);
void XAxiPmon_SetIncrementerRange(XAxiPmon *InstancePtr, u8 IncrementerNum,
u16 RangeUpper, u16 RangeLower);
@ -839,10 +840,10 @@ void XAxiPmon_SetSampleInterval(XAxiPmon *InstancePtr, u32 SampleInterval);
void XAxiPmon_GetSampleInterval(XAxiPmon *InstancePtr, u32 *SampleInterval);
int XAxiPmon_SetMetrics(XAxiPmon *InstancePtr, u8 Slot, u8 Metrics,
s32 XAxiPmon_SetMetrics(XAxiPmon *InstancePtr, u8 Slot, u8 Metrics,
u8 CounterNum);
int XAxiPmon_GetMetrics(XAxiPmon *InstancePtr, u8 CounterNum, u8 *Metrics,
s32 XAxiPmon_GetMetrics(XAxiPmon *InstancePtr, u8 CounterNum, u8 *Metrics,
u8 *Slot);
void XAxiPmon_GetGlobalClkCounter(XAxiPmon *InstancePtr,u32 *CntHighValue,
u32 *CntLowValue);
@ -859,13 +860,13 @@ void XAxiPmon_SetSwDataReg(XAxiPmon *InstancePtr, u32 SwData);
u32 XAxiPmon_GetSwDataReg(XAxiPmon *InstancePtr);
int XAxiPmon_StartEventLog(XAxiPmon *InstancePtr, u32 FlagEnables);
s32 XAxiPmon_StartEventLog(XAxiPmon *InstancePtr, u32 FlagEnables);
int XAxiPmon_StopEventLog(XAxiPmon *InstancePtr);
s32 XAxiPmon_StopEventLog(XAxiPmon *InstancePtr);
int XAxiPmon_StartCounters(XAxiPmon *InstancePtr, u32 SampleInterval);
s32 XAxiPmon_StartCounters(XAxiPmon *InstancePtr, u32 SampleInterval);
int XAxiPmon_StopCounters(XAxiPmon *InstancePtr);
s32 XAxiPmon_StopCounters(XAxiPmon *InstancePtr);
void XAxiPmon_EnableMetricsCounter(XAxiPmon *InstancePtr);
@ -925,7 +926,7 @@ u32 XAxiPmon_GetReadIdMask(XAxiPmon *InstancePtr);
/**
* Functions in xaxipmon_selftest.c
*/
int XAxiPmon_SelfTest(XAxiPmon *InstancePtr);
s32 XAxiPmon_SelfTest(XAxiPmon *InstancePtr);
#ifdef __cplusplus
}

378
XilinxProcessorIPLib/drivers/axipmon/src/xaxipmon_hw.h
View file

@ -78,6 +78,8 @@
*
* 6.2 bss 03/02/15 Added XAPM_RID_OFFSET and XAPM_RIDMASK_OFFSET to support
* Zynq MP APM.
*
* 6.3 kvn 07/02/15 Modified code according to MISRA-C:2012 guidelines.
* </pre>
*
*****************************************************************************/
@ -104,288 +106,288 @@ extern "C" {
* @{
*/
#define XAPM_GCC_HIGH_OFFSET 0x0000 /**< Global Clock Counter
#define XAPM_GCC_HIGH_OFFSET 0x00000000U /**< Global Clock Counter
32 to 63 bits */
#define XAPM_GCC_LOW_OFFSET 0x0004 /**< Global Clock Counter Lower
#define XAPM_GCC_LOW_OFFSET 0x00000004U /**< Global Clock Counter Lower
0-31 bits */
#define XAPM_SI_HIGH_OFFSET 0x0020 /**< Sample Interval MSB */
#define XAPM_SI_LOW_OFFSET 0x0024 /**< Sample Interval LSB */
#define XAPM_SICR_OFFSET 0x0028 /**< Sample Interval Control
#define XAPM_SI_HIGH_OFFSET 0x00000020U /**< Sample Interval MSB */
#define XAPM_SI_LOW_OFFSET 0x00000024U /**< Sample Interval LSB */
#define XAPM_SICR_OFFSET 0x00000028U /**< Sample Interval Control
Register */
#define XAPM_SR_OFFSET 0x002C /**< Sample Register */
#define XAPM_GIE_OFFSET 0x0030 /**< Global Interrupt Enable
#define XAPM_SR_OFFSET 0x0000002CU /**< Sample Register */
#define XAPM_GIE_OFFSET 0x00000030U /**< Global Interrupt Enable
Register */
#define XAPM_IE_OFFSET 0x0034 /**< Interrupt Enable Register */
#define XAPM_IS_OFFSET 0x0038 /**< Interrupt Status Register */
#define XAPM_IE_OFFSET 0x00000034U /**< Interrupt Enable Register */
#define XAPM_IS_OFFSET 0x00000038U /**< Interrupt Status Register */
#define XAPM_MSR0_OFFSET 0x0044 /**< Metric Selector 0 Register */
#define XAPM_MSR1_OFFSET 0x0048 /**< Metric Selector 1 Register */
#define XAPM_MSR2_OFFSET 0x004C /**< Metric Selector 2 Register */
#define XAPM_MSR0_OFFSET 0x00000044U /**< Metric Selector 0 Register */
#define XAPM_MSR1_OFFSET 0x00000048U /**< Metric Selector 1 Register */
#define XAPM_MSR2_OFFSET 0x0000004CU /**< Metric Selector 2 Register */
#define XAPM_MC0_OFFSET 0x0100 /**< Metric Counter 0 Register */
#define XAPM_INC0_OFFSET 0x0104 /**< Incrementer 0 Register */
#define XAPM_RANGE0_OFFSET 0x0108 /**< Range 0 Register */
#define XAPM_MC0LOGEN_OFFSET 0x010C /**< Metric Counter 0
#define XAPM_MC0_OFFSET 0x00000100U /**< Metric Counter 0 Register */
#define XAPM_INC0_OFFSET 0x00000104U /**< Incrementer 0 Register */
#define XAPM_RANGE0_OFFSET 0x00000108U /**< Range 0 Register */
#define XAPM_MC0LOGEN_OFFSET 0x0000010CU /**< Metric Counter 0
Log Enable Register */
#define XAPM_MC1_OFFSET 0x0110 /**< Metric Counter 1 Register */
#define XAPM_INC1_OFFSET 0x0114 /**< Incrementer 1 Register */
#define XAPM_RANGE1_OFFSET 0x0118 /**< Range 1 Register */
#define XAPM_MC1LOGEN_OFFSET 0x011C /**< Metric Counter 1
#define XAPM_MC1_OFFSET 0x00000110U /**< Metric Counter 1 Register */
#define XAPM_INC1_OFFSET 0x00000114U /**< Incrementer 1 Register */
#define XAPM_RANGE1_OFFSET 0x00000118U /**< Range 1 Register */
#define XAPM_MC1LOGEN_OFFSET 0x0000011CU /**< Metric Counter 1
Log Enable Register */
#define XAPM_MC2_OFFSET 0x0120 /**< Metric Counter 2 Register */
#define XAPM_INC2_OFFSET 0x0124 /**< Incrementer 2 Register */
#define XAPM_RANGE2_OFFSET 0x0128 /**< Range 2 Register */
#define XAPM_MC2LOGEN_OFFSET 0x012C /**< Metric Counter 2
#define XAPM_MC2_OFFSET 0x00000120U /**< Metric Counter 2 Register */
#define XAPM_INC2_OFFSET 0x00000124U /**< Incrementer 2 Register */
#define XAPM_RANGE2_OFFSET 0x00000128U /**< Range 2 Register */
#define XAPM_MC2LOGEN_OFFSET 0x0000012CU /**< Metric Counter 2
Log Enable Register */
#define XAPM_MC3_OFFSET 0x0130 /**< Metric Counter 3 Register */
#define XAPM_INC3_OFFSET 0x0134 /**< Incrementer 3 Register */
#define XAPM_RANGE3_OFFSET 0x0138 /**< Range 3 Register */
#define XAPM_MC3LOGEN_OFFSET 0x013C /**< Metric Counter 3
#define XAPM_MC3_OFFSET 0x00000130U /**< Metric Counter 3 Register */
#define XAPM_INC3_OFFSET 0x00000134U /**< Incrementer 3 Register */
#define XAPM_RANGE3_OFFSET 0x00000138U /**< Range 3 Register */
#define XAPM_MC3LOGEN_OFFSET 0x0000013CU /**< Metric Counter 3
Log Enable Register */
#define XAPM_MC4_OFFSET 0x0140 /**< Metric Counter 4 Register */
#define XAPM_INC4_OFFSET 0x0144 /**< Incrementer 4 Register */
#define XAPM_RANGE4_OFFSET 0x0148 /**< Range 4 Register */
#define XAPM_MC4LOGEN_OFFSET 0x014C /**< Metric Counter 4
#define XAPM_MC4_OFFSET 0x00000140U /**< Metric Counter 4 Register */
#define XAPM_INC4_OFFSET 0x00000144U /**< Incrementer 4 Register */
#define XAPM_RANGE4_OFFSET 0x00000148U /**< Range 4 Register */
#define XAPM_MC4LOGEN_OFFSET 0x0000014CU /**< Metric Counter 4
Log Enable Register */
#define XAPM_MC5_OFFSET 0x0150 /**< Metric Counter 5
#define XAPM_MC5_OFFSET 0x00000150U /**< Metric Counter 5
Register */
#define XAPM_INC5_OFFSET 0x0154 /**< Incrementer 5 Register */
#define XAPM_RANGE5_OFFSET 0x0158 /**< Range 5 Register */
#define XAPM_MC5LOGEN_OFFSET 0x015C /**< Metric Counter 5
#define XAPM_INC5_OFFSET 0x00000154U /**< Incrementer 5 Register */
#define XAPM_RANGE5_OFFSET 0x00000158U /**< Range 5 Register */
#define XAPM_MC5LOGEN_OFFSET 0x0000015CU /**< Metric Counter 5
Log Enable Register */
#define XAPM_MC6_OFFSET 0x0160 /**< Metric Counter 6
#define XAPM_MC6_OFFSET 0x00000160U /**< Metric Counter 6
Register */
#define XAPM_INC6_OFFSET 0x0164 /**< Incrementer 6 Register */
#define XAPM_RANGE6_OFFSET 0x0168 /**< Range 6 Register */
#define XAPM_MC6LOGEN_OFFSET 0x016C /**< Metric Counter 6
#define XAPM_INC6_OFFSET 0x00000164U /**< Incrementer 6 Register */
#define XAPM_RANGE6_OFFSET 0x00000168U /**< Range 6 Register */
#define XAPM_MC6LOGEN_OFFSET 0x0000016CU /**< Metric Counter 6
Log Enable Register */
#define XAPM_MC7_OFFSET 0x0170 /**< Metric Counter 7
#define XAPM_MC7_OFFSET 0x00000170U /**< Metric Counter 7
Register */
#define XAPM_INC7_OFFSET 0x0174 /**< Incrementer 7 Register */
#define XAPM_RANGE7_OFFSET 0x0178 /**< Range 7 Register */
#define XAPM_MC7LOGEN_OFFSET 0x017C /**< Metric Counter 7
#define XAPM_INC7_OFFSET 0x00000174U /**< Incrementer 7 Register */
#define XAPM_RANGE7_OFFSET 0x00000178U /**< Range 7 Register */
#define XAPM_MC7LOGEN_OFFSET 0x0000017CU /**< Metric Counter 7
Log Enable Register */
#define XAPM_MC8_OFFSET 0x0180 /**< Metric Counter 8
#define XAPM_MC8_OFFSET 0x00000180U /**< Metric Counter 8
Register */
#define XAPM_INC8_OFFSET 0x0184 /**< Incrementer 8 Register */
#define XAPM_RANGE8_OFFSET 0x0188 /**< Range 8 Register */
#define XAPM_MC8LOGEN_OFFSET 0x018C /**< Metric Counter 8
#define XAPM_INC8_OFFSET 0x00000184U /**< Incrementer 8 Register */
#define XAPM_RANGE8_OFFSET 0x00000188U /**< Range 8 Register */
#define XAPM_MC8LOGEN_OFFSET 0x0000018CU /**< Metric Counter 8
Log Enable Register */
#define XAPM_MC9_OFFSET 0x0190 /**< Metric Counter 9
#define XAPM_MC9_OFFSET 0x00000190U /**< Metric Counter 9
Register */
#define XAPM_INC9_OFFSET 0x0194 /**< Incrementer 9 Register */
#define XAPM_RANGE9_OFFSET 0x0198 /**< Range 9 Register */
#define XAPM_MC9LOGEN_OFFSET 0x019C /**< Metric Counter 9
#define XAPM_INC9_OFFSET 0x00000194U /**< Incrementer 9 Register */
#define XAPM_RANGE9_OFFSET 0x00000198U /**< Range 9 Register */
#define XAPM_MC9LOGEN_OFFSET 0x0000019CU /**< Metric Counter 9
Log Enable Register */
#define XAPM_SMC0_OFFSET 0x0200 /**< Sampled Metric Counter
#define XAPM_SMC0_OFFSET 0x00000200U /**< Sampled Metric Counter
0 Register */
#define XAPM_SINC0_OFFSET 0x0204 /**< Sampled Incrementer
#define XAPM_SINC0_OFFSET 0x00000204U /**< Sampled Incrementer
0 Register */
#define XAPM_SMC1_OFFSET 0x0210 /**< Sampled Metric Counter
#define XAPM_SMC1_OFFSET 0x00000210U /**< Sampled Metric Counter
1 Register */
#define XAPM_SINC1_OFFSET 0x0214 /**< Sampled Incrementer
#define XAPM_SINC1_OFFSET 0x00000214U /**< Sampled Incrementer
1 Register */
#define XAPM_SMC2_OFFSET 0x0220 /**< Sampled Metric Counter
#define XAPM_SMC2_OFFSET 0x00000220U /**< Sampled Metric Counter
2 Register */
#define XAPM_SINC2_OFFSET 0x0224 /**< Sampled Incrementer
#define XAPM_SINC2_OFFSET 0x00000224U /**< Sampled Incrementer
2 Register */
#define XAPM_SMC3_OFFSET 0x0230 /**< Sampled Metric Counter
#define XAPM_SMC3_OFFSET 0x00000230U /**< Sampled Metric Counter
3 Register */
#define XAPM_SINC3_OFFSET 0x0234 /**< Sampled Incrementer
#define XAPM_SINC3_OFFSET 0x00000234U /**< Sampled Incrementer
3 Register */
#define XAPM_SMC4_OFFSET 0x0240 /**< Sampled Metric Counter
#define XAPM_SMC4_OFFSET 0x00000240U /**< Sampled Metric Counter
4 Register */
#define XAPM_SINC4_OFFSET 0x0244 /**< Sampled Incrementer
#define XAPM_SINC4_OFFSET 0x00000244U /**< Sampled Incrementer
4 Register */
#define XAPM_SMC5_OFFSET 0x0250 /**< Sampled Metric Counter
#define XAPM_SMC5_OFFSET 0x00000250U /**< Sampled Metric Counter
5 Register */
#define XAPM_SINC5_OFFSET 0x0254 /**< Sampled Incrementer
#define XAPM_SINC5_OFFSET 0x00000254U /**< Sampled Incrementer
5 Register */
#define XAPM_SMC6_OFFSET 0x0260 /**< Sampled Metric Counter
#define XAPM_SMC6_OFFSET 0x00000260U /**< Sampled Metric Counter
6 Register */
#define XAPM_SINC6_OFFSET 0x0264 /**< Sampled Incrementer
#define XAPM_SINC6_OFFSET 0x00000264U /**< Sampled Incrementer
6 Register */
#define XAPM_SMC7_OFFSET 0x0270 /**< Sampled Metric Counter
#define XAPM_SMC7_OFFSET 0x00000270U /**< Sampled Metric Counter
7 Register */
#define XAPM_SINC7_OFFSET 0x0274 /**< Sampled Incrementer
#define XAPM_SINC7_OFFSET 0x00000274U /**< Sampled Incrementer
7 Register */
#define XAPM_SMC8_OFFSET 0x0280 /**< Sampled Metric Counter
#define XAPM_SMC8_OFFSET 0x00000280U /**< Sampled Metric Counter
8 Register */
#define XAPM_SINC8_OFFSET 0x0284 /**< Sampled Incrementer
#define XAPM_SINC8_OFFSET 0x00000284U /**< Sampled Incrementer
8 Register */
#define XAPM_SMC9_OFFSET 0x0290 /**< Sampled Metric Counter
#define XAPM_SMC9_OFFSET 0x00000290U /**< Sampled Metric Counter
9 Register */
#define XAPM_SINC9_OFFSET 0x0294 /**< Sampled Incrementer
#define XAPM_SINC9_OFFSET 0x00000294U /**< Sampled Incrementer
9 Register */
#define XAPM_MC10_OFFSET 0x01A0 /**< Metric Counter 10
#define XAPM_MC10_OFFSET 0x000001A0U /**< Metric Counter 10
Register */
#define XAPM_MC11_OFFSET 0x01B0 /**< Metric Counter 11
#define XAPM_MC11_OFFSET 0x000001B0U /**< Metric Counter 11
Register */
#define XAPM_MC12_OFFSET 0x0500 /**< Metric Counter 12
#define XAPM_MC12_OFFSET 0x00000500U /**< Metric Counter 12
Register */
#define XAPM_MC13_OFFSET 0x0510 /**< Metric Counter 13
#define XAPM_MC13_OFFSET 0x00000510U /**< Metric Counter 13
Register */
#define XAPM_MC14_OFFSET 0x0520 /**< Metric Counter 14
#define XAPM_MC14_OFFSET 0x00000520U /**< Metric Counter 14
Register */
#define XAPM_MC15_OFFSET 0x0530 /**< Metric Counter 15
#define XAPM_MC15_OFFSET 0x00000530U /**< Metric Counter 15
Register */
#define XAPM_MC16_OFFSET 0x0540 /**< Metric Counter 16
#define XAPM_MC16_OFFSET 0x00000540U /**< Metric Counter 16
Register */
#define XAPM_MC17_OFFSET 0x0550 /**< Metric Counter 17
#define XAPM_MC17_OFFSET 0x00000550U /**< Metric Counter 17
Register */
#define XAPM_MC18_OFFSET 0x0560 /**< Metric Counter 18
#define XAPM_MC18_OFFSET 0x00000560U /**< Metric Counter 18
Register */
#define XAPM_MC19_OFFSET 0x0570 /**< Metric Counter 19
#define XAPM_MC19_OFFSET 0x00000570U /**< Metric Counter 19
Register */
#define XAPM_MC20_OFFSET 0x0580 /**< Metric Counter 20
#define XAPM_MC20_OFFSET 0x00000580U /**< Metric Counter 20
Register */
#define XAPM_MC21_OFFSET 0x0590 /**< Metric Counter 21
#define XAPM_MC21_OFFSET 0x00000590U /**< Metric Counter 21
Register */
#define XAPM_MC22_OFFSET 0x05A0 /**< Metric Counter 22
#define XAPM_MC22_OFFSET 0x000005A0U /**< Metric Counter 22
Register */
#define XAPM_MC23_OFFSET 0x05B0 /**< Metric Counter 23
#define XAPM_MC23_OFFSET 0x000005B0U /**< Metric Counter 23
Register */
#define XAPM_MC24_OFFSET 0x0700 /**< Metric Counter 24
#define XAPM_MC24_OFFSET 0x00000700U /**< Metric Counter 24
Register */
#define XAPM_MC25_OFFSET 0x0710 /**< Metric Counter 25
#define XAPM_MC25_OFFSET 0x00000710U /**< Metric Counter 25
Register */
#define XAPM_MC26_OFFSET 0x0720 /**< Metric Counter 26
#define XAPM_MC26_OFFSET 0x00000720U /**< Metric Counter 26
Register */
#define XAPM_MC27_OFFSET 0x0730 /**< Metric Counter 27
#define XAPM_MC27_OFFSET 0x00000730U /**< Metric Counter 27
Register */
#define XAPM_MC28_OFFSET 0x0740 /**< Metric Counter 28
#define XAPM_MC28_OFFSET 0x00000740U /**< Metric Counter 28
Register */
#define XAPM_MC29_OFFSET 0x0750 /**< Metric Counter 29
#define XAPM_MC29_OFFSET 0x00000750U /**< Metric Counter 29
Register */
#define XAPM_MC30_OFFSET 0x0760 /**< Metric Counter 30
#define XAPM_MC30_OFFSET 0x00000760U /**< Metric Counter 30
Register */
#define XAPM_MC31_OFFSET 0x0770 /**< Metric Counter 31
#define XAPM_MC31_OFFSET 0x00000770U /**< Metric Counter 31
Register */
#define XAPM_MC32_OFFSET 0x0780 /**< Metric Counter 32
#define XAPM_MC32_OFFSET 0x00000780U /**< Metric Counter 32
Register */
#define XAPM_MC33_OFFSET 0x0790 /**< Metric Counter 33
#define XAPM_MC33_OFFSET 0x00000790U /**< Metric Counter 33
Register */
#define XAPM_MC34_OFFSET 0x07A0 /**< Metric Counter 34
#define XAPM_MC34_OFFSET 0x000007A0U /**< Metric Counter 34
Register */
#define XAPM_MC35_OFFSET 0x07B0 /**< Metric Counter 35
#define XAPM_MC35_OFFSET 0x000007B0U /**< Metric Counter 35
Register */
#define XAPM_MC36_OFFSET 0x0900 /**< Metric Counter 36
#define XAPM_MC36_OFFSET 0x00000900U /**< Metric Counter 36
Register */
#define XAPM_MC37_OFFSET 0x0910 /**< Metric Counter 37
#define XAPM_MC37_OFFSET 0x00000910U /**< Metric Counter 37
Register */
#define XAPM_MC38_OFFSET 0x0920 /**< Metric Counter 38
#define XAPM_MC38_OFFSET 0x00000920U /**< Metric Counter 38
Register */
#define XAPM_MC39_OFFSET 0x0930 /**< Metric Counter 39
#define XAPM_MC39_OFFSET 0x00000930U /**< Metric Counter 39
Register */
#define XAPM_MC40_OFFSET 0x0940 /**< Metric Counter 40
#define XAPM_MC40_OFFSET 0x00000940U /**< Metric Counter 40
Register */
#define XAPM_MC41_OFFSET 0x0950 /**< Metric Counter 41
#define XAPM_MC41_OFFSET 0x00000950U /**< Metric Counter 41
Register */
#define XAPM_MC42_OFFSET 0x0960 /**< Metric Counter 42
#define XAPM_MC42_OFFSET 0x00000960U /**< Metric Counter 42
Register */
#define XAPM_MC43_OFFSET 0x0970 /**< Metric Counter 43
#define XAPM_MC43_OFFSET 0x00000970U /**< Metric Counter 43
Register */
#define XAPM_MC44_OFFSET 0x0980 /**< Metric Counter 44
#define XAPM_MC44_OFFSET 0x00000980U /**< Metric Counter 44
Register */
#define XAPM_MC45_OFFSET 0x0990 /**< Metric Counter 45
#define XAPM_MC45_OFFSET 0x00000990U /**< Metric Counter 45
Register */
#define XAPM_MC46_OFFSET 0x09A0 /**< Metric Counter 46
#define XAPM_MC46_OFFSET 0x000009A0U /**< Metric Counter 46
Register */
#define XAPM_MC47_OFFSET 0x09B0 /**< Metric Counter 47
#define XAPM_MC47_OFFSET 0x000009B0U /**< Metric Counter 47
Register */
#define XAPM_SMC10_OFFSET 0x02A0 /**< Sampled Metric Counter
#define XAPM_SMC10_OFFSET 0x000002A0U /**< Sampled Metric Counter
10 Register */
#define XAPM_SMC11_OFFSET 0x02B0 /**< Sampled Metric Counter
#define XAPM_SMC11_OFFSET 0x000002B0U /**< Sampled Metric Counter
11 Register */
#define XAPM_SMC12_OFFSET 0x0600 /**< Sampled Metric Counter
#define XAPM_SMC12_OFFSET 0x00000600U /**< Sampled Metric Counter
12 Register */
#define XAPM_SMC13_OFFSET 0x0610 /**< Sampled Metric Counter
#define XAPM_SMC13_OFFSET 0x00000610U /**< Sampled Metric Counter
13 Register */
#define XAPM_SMC14_OFFSET 0x0620 /**< Sampled Metric Counter
#define XAPM_SMC14_OFFSET 0x00000620U /**< Sampled Metric Counter
14 Register */
#define XAPM_SMC15_OFFSET 0x0630 /**< Sampled Metric Counter
#define XAPM_SMC15_OFFSET 0x00000630U /**< Sampled Metric Counter
15 Register */
#define XAPM_SMC16_OFFSET 0x0640 /**< Sampled Metric Counter
#define XAPM_SMC16_OFFSET 0x00000640U /**< Sampled Metric Counter
16 Register */
#define XAPM_SMC17_OFFSET 0x0650 /**< Sampled Metric Counter
#define XAPM_SMC17_OFFSET 0x00000650U /**< Sampled Metric Counter
17 Register */
#define XAPM_SMC18_OFFSET 0x0660 /**< Sampled Metric Counter
#define XAPM_SMC18_OFFSET 0x00000660U /**< Sampled Metric Counter
18 Register */
#define XAPM_SMC19_OFFSET 0x0670 /**< Sampled Metric Counter
#define XAPM_SMC19_OFFSET 0x00000670U /**< Sampled Metric Counter
19 Register */
#define XAPM_SMC20_OFFSET 0x0680 /**< Sampled Metric Counter
#define XAPM_SMC20_OFFSET 0x00000680U /**< Sampled Metric Counter
20 Register */
#define XAPM_SMC21_OFFSET 0x0690 /**< Sampled Metric Counter
#define XAPM_SMC21_OFFSET 0x00000690U /**< Sampled Metric Counter
21 Register */
#define XAPM_SMC22_OFFSET 0x06A0 /**< Sampled Metric Counter
#define XAPM_SMC22_OFFSET 0x000006A0U /**< Sampled Metric Counter
22 Register */
#define XAPM_SMC23_OFFSET 0x06B0 /**< Sampled Metric Counter
#define XAPM_SMC23_OFFSET 0x000006B0U /**< Sampled Metric Counter
23 Register */
#define XAPM_SMC24_OFFSET 0x0800 /**< Sampled Metric Counter
#define XAPM_SMC24_OFFSET 0x00000800U /**< Sampled Metric Counter
24 Register */
#define XAPM_SMC25_OFFSET 0x0810 /**< Sampled Metric Counter
#define XAPM_SMC25_OFFSET 0x00000810U /**< Sampled Metric Counter
25 Register */
#define XAPM_SMC26_OFFSET 0x0820 /**< Sampled Metric Counter
#define XAPM_SMC26_OFFSET 0x00000820U /**< Sampled Metric Counter
26 Register */
#define XAPM_SMC27_OFFSET 0x0830 /**< Sampled Metric Counter
#define XAPM_SMC27_OFFSET 0x00000830U /**< Sampled Metric Counter
27 Register */
#define XAPM_SMC28_OFFSET 0x0840 /**< Sampled Metric Counter
#define XAPM_SMC28_OFFSET 0x00000840U /**< Sampled Metric Counter
28 Register */
#define XAPM_SMC29_OFFSET 0x0850 /**< Sampled Metric Counter
#define XAPM_SMC29_OFFSET 0x00000850U /**< Sampled Metric Counter
29 Register */
#define XAPM_SMC30_OFFSET 0x0860 /**< Sampled Metric Counter
#define XAPM_SMC30_OFFSET 0x00000860U /**< Sampled Metric Counter
30 Register */
#define XAPM_SMC31_OFFSET 0x0870 /**< Sampled Metric Counter
#define XAPM_SMC31_OFFSET 0x00000870U /**< Sampled Metric Counter
31 Register */
#define XAPM_SMC32_OFFSET 0x0880 /**< Sampled Metric Counter
#define XAPM_SMC32_OFFSET 0x00000880U /**< Sampled Metric Counter
32 Register */
#define XAPM_SMC33_OFFSET 0x0890 /**< Sampled Metric Counter
#define XAPM_SMC33_OFFSET 0x00000890U /**< Sampled Metric Counter
33 Register */
#define XAPM_SMC34_OFFSET 0x08A0 /**< Sampled Metric Counter
#define XAPM_SMC34_OFFSET 0x000008A0U /**< Sampled Metric Counter
34 Register */
#define XAPM_SMC35_OFFSET 0x08B0 /**< Sampled Metric Counter
#define XAPM_SMC35_OFFSET 0x000008B0U /**< Sampled Metric Counter
35 Register */
#define XAPM_SMC36_OFFSET 0x0A00 /**< Sampled Metric Counter
#define XAPM_SMC36_OFFSET 0x00000A00U /**< Sampled Metric Counter
36 Register */
#define XAPM_SMC37_OFFSET 0x0A10 /**< Sampled Metric Counter
#define XAPM_SMC37_OFFSET 0x00000A10U /**< Sampled Metric Counter
37 Register */
#define XAPM_SMC38_OFFSET 0x0A20 /**< Sampled Metric Counter
#define XAPM_SMC38_OFFSET 0x00000A20U /**< Sampled Metric Counter
38 Register */
#define XAPM_SMC39_OFFSET 0x0A30 /**< Sampled Metric Counter
#define XAPM_SMC39_OFFSET 0x00000A30U /**< Sampled Metric Counter
39 Register */
#define XAPM_SMC40_OFFSET 0x0A40 /**< Sampled Metric Counter
#define XAPM_SMC40_OFFSET 0x00000A40U /**< Sampled Metric Counter
40 Register */
#define XAPM_SMC41_OFFSET 0x0A50 /**< Sampled Metric Counter
#define XAPM_SMC41_OFFSET 0x00000A50U /**< Sampled Metric Counter
41 Register */
#define XAPM_SMC42_OFFSET 0x0A60 /**< Sampled Metric Counter
#define XAPM_SMC42_OFFSET 0x00000A60U /**< Sampled Metric Counter
42 Register */
#define XAPM_SMC43_OFFSET 0x0A70 /**< Sampled Metric Counter
#define XAPM_SMC43_OFFSET 0x00000A70U /**< Sampled Metric Counter
43 Register */
#define XAPM_SMC44_OFFSET 0x0A80 /**< Sampled Metric Counter
#define XAPM_SMC44_OFFSET 0x00000A80U /**< Sampled Metric Counter
44 Register */
#define XAPM_SMC45_OFFSET 0x0A90 /**< Sampled Metric Counter
#define XAPM_SMC45_OFFSET 0x00000A90U /**< Sampled Metric Counter
45 Register */
#define XAPM_SMC46_OFFSET 0x0AA0 /**< Sampled Metric Counter
#define XAPM_SMC46_OFFSET 0x00000AA0U /**< Sampled Metric Counter
46 Register */
#define XAPM_SMC47_OFFSET 0x0AB0 /**< Sampled Metric Counter
#define XAPM_SMC47_OFFSET 0x00000AB0U /**< Sampled Metric Counter
47 Register */
#define XAPM_CTL_OFFSET 0x0300 /**< Control Register */
#define XAPM_CTL_OFFSET 0x00000300U /**< Control Register */
#define XAPM_ID_OFFSET 0x0304 /**< Latency ID Register */
#define XAPM_ID_OFFSET 0x00000304U /**< Latency ID Register */
#define XAPM_IDMASK_OFFSET 0x0308 /**< ID Mask Register */
#define XAPM_IDMASK_OFFSET 0x00000308U /**< ID Mask Register */
#define XAPM_RID_OFFSET 0x030C /**< Latency Write ID Register */
#define XAPM_RID_OFFSET 0x0000030CU /**< Latency Write ID Register */
#define XAPM_RIDMASK_OFFSET 0x0310 /**< Read ID Mask Register */
#define XAPM_RIDMASK_OFFSET 0x00000310U /**< Read ID Mask Register */
#define XAPM_FEC_OFFSET 0x0400 /**< Flag Enable
#define XAPM_FEC_OFFSET 0x00000400U /**< Flag Enable
Control Register */
#define XAPM_SWD_OFFSET 0x0404 /**< Software-written
#define XAPM_SWD_OFFSET 0x00000404U /**< Software-written
Data Register */
/* @} */
@ -395,12 +397,12 @@ extern "C" {
* @{
*/
#define XAPM_SICR_MCNTR_RST_MASK 0x00000100 /**< Enable the Metric
#define XAPM_SICR_MCNTR_RST_MASK 0x00000100U /**< Enable the Metric
Counter Reset */
#define XAPM_SICR_LOAD_MASK 0x00000002 /**< Load the Sample Interval
#define XAPM_SICR_LOAD_MASK 0x00000002U /**< Load the Sample Interval
* Register Value into the
* counter */
#define XAPM_SICR_ENABLE_MASK 0x00000001 /**< Enable the downcounter */
#define XAPM_SICR_ENABLE_MASK 0x00000001U /**< Enable the downcounter */
/*@}*/
@ -409,31 +411,31 @@ extern "C" {
* @{
*/
#define XAPM_IXR_MC9_OVERFLOW_MASK 0x00001000 /**< Metric Counter 9
#define XAPM_IXR_MC9_OVERFLOW_MASK 0x00001000U /**< Metric Counter 9
* Overflow> */
#define XAPM_IXR_MC8_OVERFLOW_MASK 0x00000800 /**< Metric Counter 8
#define XAPM_IXR_MC8_OVERFLOW_MASK 0x00000800U /**< Metric Counter 8
* Overflow> */
#define XAPM_IXR_MC7_OVERFLOW_MASK 0x00000400 /**< Metric Counter 7
#define XAPM_IXR_MC7_OVERFLOW_MASK 0x00000400U /**< Metric Counter 7
* Overflow> */
#define XAPM_IXR_MC6_OVERFLOW_MASK 0x00000200 /**< Metric Counter 6
#define XAPM_IXR_MC6_OVERFLOW_MASK 0x00000200U /**< Metric Counter 6
* Overflow> */
#define XAPM_IXR_MC5_OVERFLOW_MASK 0x00000100 /**< Metric Counter 5
#define XAPM_IXR_MC5_OVERFLOW_MASK 0x00000100U /**< Metric Counter 5
* Overflow> */
#define XAPM_IXR_MC4_OVERFLOW_MASK 0x00000080 /**< Metric Counter 4
#define XAPM_IXR_MC4_OVERFLOW_MASK 0x00000080U /**< Metric Counter 4
* Overflow> */
#define XAPM_IXR_MC3_OVERFLOW_MASK 0x00000040 /**< Metric Counter 3
#define XAPM_IXR_MC3_OVERFLOW_MASK 0x00000040U /**< Metric Counter 3
* Overflow> */
#define XAPM_IXR_MC2_OVERFLOW_MASK 0x00000020 /**< Metric Counter 2
#define XAPM_IXR_MC2_OVERFLOW_MASK 0x00000020U /**< Metric Counter 2
* Overflow> */
#define XAPM_IXR_MC1_OVERFLOW_MASK 0x00000010 /**< Metric Counter 1
#define XAPM_IXR_MC1_OVERFLOW_MASK 0x00000010U /**< Metric Counter 1
* Overflow> */
#define XAPM_IXR_MC0_OVERFLOW_MASK 0x00000008 /**< Metric Counter 0
#define XAPM_IXR_MC0_OVERFLOW_MASK 0x00000008U /**< Metric Counter 0
* Overflow> */
#define XAPM_IXR_FIFO_FULL_MASK 0x00000004 /**< Event Log FIFO
#define XAPM_IXR_FIFO_FULL_MASK 0x00000004U /**< Event Log FIFO
* full> */
#define XAPM_IXR_SIC_OVERFLOW_MASK 0x00000002 /**< Sample Interval
#define XAPM_IXR_SIC_OVERFLOW_MASK 0x00000002U /**< Sample Interval
* Counter Overflow> */
#define XAPM_IXR_GCC_OVERFLOW_MASK 0x00000001 /**< Global Clock Counter
#define XAPM_IXR_GCC_OVERFLOW_MASK 0x00000001U /**< Global Clock Counter
* Overflow> */
#define XAPM_IXR_ALL_MASK (XAPM_IXR_SIC_OVERFLOW_MASK | \
XAPM_IXR_GCC_OVERFLOW_MASK | \
@ -455,43 +457,43 @@ extern "C" {
* @{
*/
#define XAPM_CR_FIFO_RESET_MASK 0x02000000
#define XAPM_CR_FIFO_RESET_MASK 0x02000000U
/**< FIFO Reset */
#define XAPM_CR_GCC_RESET_MASK 0x00020000
#define XAPM_CR_GCC_RESET_MASK 0x00020000U
/**< Global Clk
Counter Reset */
#define XAPM_CR_GCC_ENABLE_MASK 0x00010000
#define XAPM_CR_GCC_ENABLE_MASK 0x00010000U
/**< Global Clk
Counter Enable */
#define XAPM_CR_EVTLOG_EXTTRIGGER_MASK 0x00000200
#define XAPM_CR_EVTLOG_EXTTRIGGER_MASK 0x00000200U
/**< Enable External trigger
to start event Log */
#define XAPM_CR_EVENTLOG_ENABLE_MASK 0x00000100
#define XAPM_CR_EVENTLOG_ENABLE_MASK 0x00000100U
/**< Event Log Enable */
#define XAPM_CR_RDLATENCY_END_MASK 0x00000080
#define XAPM_CR_RDLATENCY_END_MASK 0x00000080U
/**< Write Latency
End point */
#define XAPM_CR_RDLATENCY_START_MASK 0x00000040
#define XAPM_CR_RDLATENCY_START_MASK 0x00000040U
/**< Read Latency
Start point */
#define XAPM_CR_WRLATENCY_END_MASK 0x00000020
#define XAPM_CR_WRLATENCY_END_MASK 0x00000020U
/**< Write Latency
End point */
#define XAPM_CR_WRLATENCY_START_MASK 0x00000010
#define XAPM_CR_WRLATENCY_START_MASK 0x00000010U
/**< Write Latency
Start point */
#define XAPM_CR_IDFILTER_ENABLE_MASK 0x00000008
#define XAPM_CR_IDFILTER_ENABLE_MASK 0x00000008U
/**< ID Filter Enable */
#define XAPM_CR_MCNTR_EXTTRIGGER_MASK 0x00000004
#define XAPM_CR_MCNTR_EXTTRIGGER_MASK 0x00000004U
/**< Enable External
trigger to start
Metric Counters */
#define XAPM_CR_MCNTR_RESET_MASK 0x00000002
#define XAPM_CR_MCNTR_RESET_MASK 0x00000002U
/**< Metrics Counter
Reset */
#define XAPM_CR_MCNTR_ENABLE_MASK 0x00000001
#define XAPM_CR_MCNTR_ENABLE_MASK 0x00000001U
/**< Metrics Counter
Enable */
/*@}*/
@ -501,9 +503,9 @@ extern "C" {
* @{
*/
#define XAPM_ID_RID_MASK 0xFFFF0000 /**< Read ID */
#define XAPM_ID_RID_MASK 0xFFFF0000U /**< Read ID */
#define XAPM_ID_WID_MASK 0x0000FFFF /**< Write ID */
#define XAPM_ID_WID_MASK 0x0000FFFFU /**< Write ID */
/*@}*/
@ -512,9 +514,9 @@ extern "C" {
* @{
*/
#define XAPM_MASKID_RID_MASK 0xFFFF0000 /**< Read ID Mask */
#define XAPM_MASKID_RID_MASK 0xFFFF0000U /**< Read ID Mask */
#define XAPM_MASKID_WID_MASK 0x0000FFFF /**< Write ID Mask*/
#define XAPM_MASKID_WID_MASK 0x0000FFFFU /**< Write ID Mask*/
/*@}*/

17
XilinxProcessorIPLib/drivers/axipmon/src/xaxipmon_selftest.c
View file

@ -53,6 +53,7 @@
* ----- ----- -------- -----------------------------------------------------
* 1.00a bss 02/24/12 First release
* 2.00a bss 06/23/12 Updated to support v2_00a version of IP.
* 6.3 kvn 07/02/15 Modified code according to MISRA-C:2012 guidelines.
* </pre>
*
*****************************************************************************/
@ -68,8 +69,8 @@
* to the Range Registers of Incrementers
*/
#define XAPM_TEST_RANGEUPPER_VALUE 16 /**< Test Value for Upper Range */
#define XAPM_TEST_RANGELOWER_VALUE 8 /**< Test Value for Lower Range */
#define XAPM_TEST_RANGEUPPER_VALUE 16U /**< Test Value for Upper Range */
#define XAPM_TEST_RANGELOWER_VALUE 8U /**< Test Value for Lower Range */
/**************************** Type Definitions ******************************/
@ -101,11 +102,11 @@
* device status after the reset operation.
*
******************************************************************************/
int XAxiPmon_SelfTest(XAxiPmon *InstancePtr)
s32 XAxiPmon_SelfTest(XAxiPmon *InstancePtr)
{
int Status;
u16 RangeUpper;
u16 RangeLower;
s32 Status;
u16 RangeUpper = 0U;
u16 RangeLower = 0U;
/*
* Assert the argument
@ -117,7 +118,7 @@ int XAxiPmon_SelfTest(XAxiPmon *InstancePtr)
/*
* Reset the device to get it back to its default state
*/
XAxiPmon_ResetMetricCounter(InstancePtr);
(void)XAxiPmon_ResetMetricCounter(InstancePtr);
XAxiPmon_ResetGlobalClkCounter(InstancePtr);
/*
@ -141,7 +142,7 @@ int XAxiPmon_SelfTest(XAxiPmon *InstancePtr)
/*
* Reset the device again to its default state.
*/
XAxiPmon_ResetMetricCounter(InstancePtr);
(void)XAxiPmon_ResetMetricCounter(InstancePtr);
XAxiPmon_ResetGlobalClkCounter(InstancePtr);
/*

5
XilinxProcessorIPLib/drivers/axipmon/src/xaxipmon_sinit.c
View file

@ -50,6 +50,7 @@
* ----- ----- -------- -----------------------------------------------------
* 1.00a bss 02/27/12 First release
* 2.00a bss 06/23/12 Updated to support v2_00a version of IP.
* 6.3 kvn 07/02/15 Modified code according to MISRA-C:2012 guidelines.
* </pre>
*
******************************************************************************/
@ -92,13 +93,13 @@ XAxiPmon_Config *XAxiPmon_LookupConfig(u16 DeviceId)
XAxiPmon_Config *CfgPtr = NULL;
u32 Index;
for (Index=0; Index < XPAR_XAXIPMON_NUM_INSTANCES; Index++) {
for (Index=0U; Index < (u32)XPAR_XAXIPMON_NUM_INSTANCES; Index++) {
if (XAxiPmon_ConfigTable[Index].DeviceId == DeviceId) {
CfgPtr = &XAxiPmon_ConfigTable[Index];
break;
}
}
return CfgPtr;
return (XAxiPmon_Config *)CfgPtr;
}
/** @} */