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sdps: Use ChangeClkFreq API to change the clock.

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This patch use ChangeClkFreq API whenever changing the clock.

Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
This commit is contained in:
P L Sai Krishna 2014-09-29 11:13:22 +05:30 • committed by Suneel Garapati
parent c8ab773a4d
commit 659878f9aa
3 changed files with 26 additions and 47 deletions
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34
XilinxProcessorIPLib/drivers/sdps/src/xsdps.c
View file

@ -48,6 +48,8 @@
* 2.2 hk 07/28/14 Make changes to enable use of data cache.
* 2.3 sk 09/23/14 Send command for relative card address
* when re-initialization is done.CR# 819614.
* Use XSdPs_Change_ClkFreq API whenever changing
* clock.CR# 816586.
*
* </pre>
*
@ -126,6 +128,7 @@ int XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
u32 EffectiveAddr)
{
u32 ClockReg;
u32 Status;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(ConfigPtr != NULL);
@ -157,26 +160,13 @@ int XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
XSDPS_CAPS_OFFSET);
/*
* SD clock frequency divider 128
* Enable the internal clock
* Change the clock frequency to 400 KHz
*/
XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
XSDPS_CLK_CTRL_OFFSET,
XSDPS_CC_SDCLK_FREQ_D128_MASK | XSDPS_CC_INT_CLK_EN_MASK);
/*
* Wait for internal clock to stabilize
*/
while ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
XSDPS_CLK_CTRL_OFFSET) & XSDPS_CC_INT_CLK_STABLE_MASK) == 0);
/*
* Enable SD clock
*/
ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
XSDPS_CLK_CTRL_OFFSET);
XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
XSDPS_CLK_CTRL_OFFSET, ClockReg | XSDPS_CC_SD_CLK_EN_MASK);
Status = XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_400_KHZ);
if (Status != XST_SUCCESS) {
Status = XST_FAILURE;
goto RETURN_PATH ;
}
/*
* Select voltage and enable bus power.
@ -223,7 +213,11 @@ int XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
XSDPS_BLK_SIZE_OFFSET, XSDPS_BLK_SIZE_512_MASK);
return XST_SUCCESS;
Status = XST_SUCCESS;
RETURN_PATH:
return Status;
}
/*****************************************************************************/

4
XilinxProcessorIPLib/drivers/sdps/src/xsdps.h
View file

@ -106,6 +106,8 @@
* 2.2 hk 07/28/14 Make changes to enable use of data cache.
* 2.3 sk 09/23/14 Send command for relative card address
* when re-initialization is done.CR# 819614.
* Use XSdPs_Change_ClkFreq API whenever changing
* clock.CR# 816586.
*
* </pre>
*
@ -125,6 +127,8 @@ extern "C" {
/************************** Constant Definitions *****************************/
#define XSDPS_CLK_400_KHZ 400000 /**< 400 KHZ */
#define XSDPS_CLK_50_MHZ 50000000 /**< 50 MHZ */
/**************************** Type Definitions *******************************/
/**
* This typedef contains configuration information for the device.

35
XilinxProcessorIPLib/drivers/sdps/src/xsdps_options.c
View file

@ -45,6 +45,8 @@
* 1.00a hk/sg 10/17/13 Initial release
* 2.1 hk 04/18/14 Increase sleep for eMMC switch command.
* Add sleep for microblaze designs. CR# 781117.
* 2.3 sk 09/23/14 Use XSdPs_Change_ClkFreq API whenever changing
* clock.CR# 816586.
*
* </pre>
*
@ -510,35 +512,14 @@ int XSdPs_Change_BusSpeed(XSdPs *InstancePtr)
XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
XSDPS_CLK_CTRL_OFFSET);
ClockReg &= ~(XSDPS_CC_INT_CLK_EN_MASK | XSDPS_CC_SD_CLK_EN_MASK);
XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
XSDPS_CLK_CTRL_OFFSET, ClockReg);
ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
XSDPS_CLK_CTRL_OFFSET);
ClockReg &= (~XSDPS_CC_SDCLK_FREQ_SEL_MASK);
ClockReg |= XSDPS_CC_SDCLK_FREQ_BASE_MASK | XSDPS_CC_INT_CLK_EN_MASK;
XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
XSDPS_CLK_CTRL_OFFSET, ClockReg);
/*
* Wait for internal clock to stabilize
* Change the clock frequency to 50 MHz
*/
while((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
XSDPS_CLK_CTRL_OFFSET) & XSDPS_CC_INT_CLK_STABLE_MASK) == 0);
/*
* Enable SD clock
*/
ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
XSDPS_CLK_CTRL_OFFSET);
XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
XSDPS_CLK_CTRL_OFFSET,
ClockReg | XSDPS_CC_SD_CLK_EN_MASK);
Status = XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_50_MHZ);
if (Status != XST_SUCCESS) {
Status = XST_FAILURE;
goto RETURN_PATH;
}
StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
XSDPS_HOST_CTRL1_OFFSET);