standalone : Modified L2CacheInvalidate API for flushing stack region in A9.
This patch modifies cortex-a9 L2CacheInvalidate API for calculating stack region and flushing out to memory before cache invalidation. This safeguards link register value in stack from being corrupted due to cache invalidation. Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
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1 changed files with 12 additions and 1 deletions
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@ -79,7 +79,9 @@
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* 4.01 asa 05/09/14 Made changes in cortexa9/xil_cache.c to fix CR# 798230.
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* 4.02 pkp 06/27/14 Added notes to Xil_L1DCacheInvalidateRange function for
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* explanation of CR#785243
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*
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* 5.00 kvn 12/15/14 Xil_L2CacheInvalidate was modified to fix CR# 838835. L2 Cache
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* has stack memory which has return address. Before invalidating
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* cache, stack memory was flushed first and L2 Cache is invalidated.
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* </pre>
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*
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******************************************************************************/
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@ -1354,6 +1356,15 @@ void Xil_L2CacheDisable(void)
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****************************************************************************/
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void Xil_L2CacheInvalidate(void)
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{
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#ifdef __GNUC__
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u32 stack_start,stack_end,stack_size;
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stack_end = (u32)&_stack_end;
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stack_start = (u32)&_stack;
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stack_size=stack_start-stack_end;
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/*Flush stack memory to save return address*/
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Xil_DCacheFlushRange(stack_end, stack_size);
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#endif
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u32 ResultDCache;
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/* Invalidate the caches */
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Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET,
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