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standalone : Modified L2CacheInvalidate API for flushing stack region in A9.

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This patch modifies cortex-a9 L2CacheInvalidate API for calculating stack
region and flushing out to memory before cache invalidation. This safeguards link
register value in stack from being corrupted due to cache invalidation.

Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
This commit is contained in:
Venkata Naga Sai Krishna Kolapalli 2014-12-15 17:40:26 +05:30 • committed by Nava kishore Manne
parent 205b80bc40
commit 6bc29be8b6
1 changed files with 12 additions and 1 deletions
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13
lib/bsp/standalone/src/cortexa9/xil_cache.c
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@ -79,7 +79,9 @@
* 4.01 asa 05/09/14 Made changes in cortexa9/xil_cache.c to fix CR# 798230.
* 4.02 pkp 06/27/14 Added notes to Xil_L1DCacheInvalidateRange function for
* explanation of CR#785243
*
* 5.00 kvn 12/15/14 Xil_L2CacheInvalidate was modified to fix CR# 838835. L2 Cache
* has stack memory which has return address. Before invalidating
* cache, stack memory was flushed first and L2 Cache is invalidated.
* </pre>
*
******************************************************************************/
@ -1354,6 +1356,15 @@ void Xil_L2CacheDisable(void)
****************************************************************************/
void Xil_L2CacheInvalidate(void)
{
#ifdef __GNUC__
u32 stack_start,stack_end,stack_size;
stack_end = (u32)&_stack_end;
stack_start = (u32)&_stack;
stack_size=stack_start-stack_end;
/*Flush stack memory to save return address*/
Xil_DCacheFlushRange(stack_end, stack_size);
#endif
u32 ResultDCache;
/* Invalidate the caches */
Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET,