BSP: Added IAR support for cortexa9
This patch adds support for iar compiler into standalone BSP for cortexa9 Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com> Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
This commit is contained in:
Kinjal Pravinbhai Patel
Jagannadha Sutradharudu Teki
parent
b84c029fc6
commit
6ef2a1bae2
26 changed files with 1822 additions and 28 deletions
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@ -89,6 +89,8 @@ proc generate {os_handle} {
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set compiler [get_property CONFIG.compiler $procdrv]
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if {[string compare -nocase $compiler "armcc"] == 0} {
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set ccdir "./src/cortexa9/armcc"
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} elseif {[string compare -nocase $compiler "iccarm"] == 0} {
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set ccdir "./src/cortexa9/iccarm"
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} else {
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set ccdir "./src/cortexa9/gcc"
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}
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@ -100,7 +102,12 @@ proc generate {os_handle} {
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}
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file delete -force "./src/armcc"
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file delete -force "./src/gcc"
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file delete -force "./src/iccarm"
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if {[string compare -nocase $compiler "armcc"] == 0} {
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file delete -force "./src/profile"
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set enable_sw_profile "false"
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}
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if {[string compare -nocase $compiler "iccarm"] == 0} {
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file delete -force "./src/profile"
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set enable_sw_profile "false"
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}
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@ -120,6 +127,8 @@ proc generate {os_handle} {
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puts $makeconfig "PROFILE_ARCH_OBJS = profile_mcount_mb.o"
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} elseif { $proctype == "ps7_cortexa9" } {
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if {[string compare -nocase $compiler "armcc"] == 0} {
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puts $makeconfig "LIBSOURCES = *.c *.s"
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} elseif {[string compare -nocase $compiler "iccarm"] == 0} {
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puts $makeconfig "LIBSOURCES = *.c *.s"
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} else {
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puts $makeconfig "LIBSOURCES = *.c *.s *.S"
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@ -171,5 +171,6 @@
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* 4.1 asa 05/09/14 Fix for CR#798230. Made changes in cortexa9/xil_cache.c and
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* common/xil_testcache.c
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* Fix for CR#764881.
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*
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* 4.2 pkp 06/27/14 Added support for IAR compiler in src/cortexa9/iccarm.
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* Also added explanatory notes in cortexa9/xil_cache.c for CR#785243.
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*****************************************************************************************/
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@ -58,7 +58,13 @@ extern void xil_printf(const char *ctrl1, ...);
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#define DATA_LENGTH 128
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#ifdef __GNUC__
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static u32 Data[DATA_LENGTH] __attribute__ ((aligned(32)));
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#elif defined (__ICCARM__)
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static u32 Data[DATA_LENGTH];
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#else
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static u32 Data[DATA_LENGTH] __attribute__ ((aligned(32)));
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#endif
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/**
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* Perform DCache range related API test such as Xil_DCacheFlushRange and
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@ -43,7 +43,7 @@
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; ----- ------- -------- ---------------------------------------------------
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; 1.00a ecm/sdm 10/20/09 Initial version
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; 3.11a asa 9/17/13 Added support for neon.
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; 4.00a pkp 22/01/14 Modified return addresses for interrupt
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; 4.00 pkp 01/22/14 Modified return addresses for interrupt
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; handlers
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;</pre>
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;
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86
lib/bsp/standalone/src/cortexa9/iccarm/Makefile
Executable file
86
lib/bsp/standalone/src/cortexa9/iccarm/Makefile
Executable file
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@ -0,0 +1,86 @@
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###############################################################################
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#
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# Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
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#
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# Permission is hereby granted, free of charge, to any person obtaining a copy
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# of this software and associated documentation files (the "Software"), to deal
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# in the Software without restriction, including without limitation the rights
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# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
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# copies of the Software, and to permit persons to whom the Software is
|
||||
# furnished to do so, subject to the following conditions:
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#
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# The above copyright notice and this permission notice shall be included in
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# all copies or substantial portions of the Software.
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#
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# Use of the Software is limited solely to applications:
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# (a) running on a Xilinx device, or
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# (b) that interact with a Xilinx device through a bus or interconnect.
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#
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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# XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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# SOFTWARE.
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#
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# Except as contained in this notice, the name of the Xilinx shall not be used
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# in advertising or otherwise to promote the sale, use or other dealings in
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# this Software without prior written authorization from Xilinx.
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#
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###############################################################################
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include config.make
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AS=iasmarm
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COMPILER=iccarm
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ARCHIVER=iarchive
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CP=cp
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COMPILER_FLAGS=
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EXTRA_COMPILER_FLAGS=
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LIB=libxil.a
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CC_FLAGS = $(COMPILER_FLAGS)
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ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
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ECC_FLAGS += --cpu=Cortex-A9 --fpu=VFPv3_d16
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RELEASEDIR=../../../lib
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INCLUDEDIR=../../../include
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INCLUDES=-I./. -I${INCLUDEDIR}
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INCLUDEFILES=*.h
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OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
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OBJECTS += $(addsuffix .o, $(basename $(wildcard *.s)))
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#OBJECTS += boot.o
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libs: banner $(LIBS) clean
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#boot.s: boot.S
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# ${COMPILER} $(INCLUDES) -E -o $@ $<
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# rm -f boot.S
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%.o: %.s
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${AS} --cpu Cortex-A9 --fpu VFPv3_d16 $(INCLUDES) -o $@ $<
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%.o: %.c
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${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
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banner:
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echo "Compiling standalone"
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echo "${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<"
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standalone_libs: ${OBJECTS}
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$(ARCHIVER) --create ${RELEASEDIR}/${LIB} ${OBJECTS}
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.PHONY: include
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include: standalone_includes
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standalone_includes:
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${CP} ${INCLUDEFILES} ${INCLUDEDIR}
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clean:
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rm -rf ${OBJECTS}
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41
lib/bsp/standalone/src/cortexa9/iccarm/abort.c
Executable file
41
lib/bsp/standalone/src/cortexa9/iccarm/abort.c
Executable file
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@ -0,0 +1,41 @@
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/******************************************************************************
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*
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* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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#include <stdlib.h>
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#include <yfuns.h>
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void abort(void)
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{
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__exit(1);
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}
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151
lib/bsp/standalone/src/cortexa9/iccarm/asm_vectors.s
Executable file
151
lib/bsp/standalone/src/cortexa9/iccarm/asm_vectors.s
Executable file
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@ -0,0 +1,151 @@
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;******************************************************************************
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;
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; Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
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;
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; Permission is hereby granted, free of charge, to any person obtaining a copy
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; of this software and associated documentation files (the "Software"), to deal
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; in the Software without restriction, including without limitation the rights
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; to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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; copies of the Software, and to permit persons to whom the Software is
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; furnished to do so, subject to the following conditions:
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;
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; The above copyright notice and this permission notice shall be included in
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; all copies or substantial portions of the Software.
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;
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; Use of the Software is limited solely to applications:
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; (a) running on a Xilinx device, or
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; (b) that interact with a Xilinx device through a bus or interconnect.
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;
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; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
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; XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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; WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
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; OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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; SOFTWARE.
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;
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; Except as contained in this notice, the name of the Xilinx shall not be used
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; in advertising or otherwise to promote the sale, use or other dealings in
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; this Software without prior written authorization from Xilinx.
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;
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;*****************************************************************************
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;****************************************************************************
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;**
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; @file asm_vectors.s
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;
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; This file contains the initial vector table for the Cortex A9 processor
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;
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; <pre>
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; MODIFICATION HISTORY:
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;
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; Ver Who Date Changes
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; ----- ------- -------- ---------------------------------------------------
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; 1.00a Initial version
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; 4.2 pkp 06/27/14 Modified return addresses for interrupt
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; handlers
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; </pre>
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;
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; @note
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;
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; None.
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;
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;****************************************************************************
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MODULE ?asm_vectors
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;; Forward declaration of sections.
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SECTION IRQ_STACK:DATA:NOROOT(3)
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SECTION FIQ_STACK:DATA:NOROOT(3)
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SECTION SVC_STACK:DATA:NOROOT(3)
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SECTION ABT_STACK:DATA:NOROOT(3)
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SECTION UND_STACK:DATA:NOROOT(3)
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SECTION CSTACK:DATA:NOROOT(3)
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#include "xparameters.h"
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;#include "xtime_l.h"
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#define UART_BAUDRATE 115200
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IMPORT _prestart
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IMPORT __iar_program_start
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SECTION .intvec:CODE:NOROOT(2)
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PUBLIC _vector_table
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IMPORT IRQInterrupt
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IMPORT FIQInterrupt
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IMPORT SWInterrupt
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IMPORT DataAbortInterrupt
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IMPORT PrefetchAbortInterrupt
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_vector_table
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ARM
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B __iar_program_start
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B Undefined
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B SVCHandler
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B PrefetchAbortHandler
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B DataAbortHandler
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NOP ; Placeholder for address exception vector
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B IRQHandler
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B FIQHandler
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SECTION .text:CODE:NOROOT(2)
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REQUIRE _vector_table
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ARM
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IRQHandler ; IRQ vector handler
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stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
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bl IRQInterrupt ; IRQ vector
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ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
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subs pc, lr, #4 ; adjust return
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FIQHandler ; FIQ vector handler
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stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
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FIQLoop
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bl FIQInterrupt ; FIQ vector
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ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
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subs pc, lr, #4 ; adjust return
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Undefined ; Undefined handler
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stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
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ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
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b _prestart
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movs pc, lr
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SVCHandler ; SWI handler
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stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
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tst r0, #0x20 ; check the T bit
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ldrneh r0, [lr,#-2] ; Thumb mode
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bicne r0, r0, #0xff00 ; Thumb mode
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ldreq r0, [lr,#-4] ; ARM mode
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biceq r0, r0, #0xff000000 ; ARM mode
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bl SWInterrupt ; SWInterrupt: call C function here
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ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
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movs pc, lr ; adjust return
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DataAbortHandler ; Data Abort handler
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stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
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bl DataAbortInterrupt ;DataAbortInterrupt :call C function here
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ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
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subs pc, lr, #8 ; adjust return
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PrefetchAbortHandler ; Prefetch Abort handler
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stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
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bl PrefetchAbortInterrupt ; PrefetchAbortInterrupt: call C function here
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ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
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subs pc, lr, #4 ; adjust return
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END
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462
lib/bsp/standalone/src/cortexa9/iccarm/boot.s
Executable file
462
lib/bsp/standalone/src/cortexa9/iccarm/boot.s
Executable file
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@ -0,0 +1,462 @@
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;******************************************************************************
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;
|
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; Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
|
||||
;
|
||||
; Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
; of this software and associated documentation files (the "Software"), to deal
|
||||
; in the Software without restriction, including without limitation the rights
|
||||
; to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
; copies of the Software, and to permit persons to whom the Software is
|
||||
; furnished to do so, subject to the following conditions:
|
||||
;
|
||||
; The above copyright notice and this permission notice shall be included in
|
||||
; all copies or substantial portions of the Software.
|
||||
;
|
||||
; Use of the Software is limited solely to applications:
|
||||
; (a) running on a Xilinx device, or
|
||||
; (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
;
|
||||
; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
; XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
; WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
; OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
; SOFTWARE.
|
||||
;
|
||||
; Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
; in advertising or otherwise to promote the sale, use or other dealings in
|
||||
; this Software without prior written authorization from Xilinx.
|
||||
;
|
||||
;*****************************************************************************
|
||||
;****************************************************************************
|
||||
;**
|
||||
; @file boot.s
|
||||
;
|
||||
; This file contains the initial vector table for the Cortex A9 processor
|
||||
;
|
||||
; <pre>
|
||||
; MODIFICATION HISTORY:
|
||||
;
|
||||
; Ver Who Date Changes
|
||||
; ----- ------- -------- ---------------------------------------------------
|
||||
; 1.00a Initial version
|
||||
; </pre>
|
||||
;
|
||||
; @note
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||||
;
|
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; None.
|
||||
;
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||||
;****************************************************************************
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|
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MODULE ?boot
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;; Forward declaration of sections.
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||||
SECTION IRQ_STACK:DATA:NOROOT(3)
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SECTION FIQ_STACK:DATA:NOROOT(3)
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SECTION SVC_STACK:DATA:NOROOT(3)
|
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SECTION ABT_STACK:DATA:NOROOT(3)
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SECTION UND_STACK:DATA:NOROOT(3)
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SECTION CSTACK:DATA:NOROOT(3)
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||||
|
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#include "xparameters.h"
|
||||
;#include "xtime_l.h"
|
||||
|
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#define UART_BAUDRATE 115200
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|
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PUBLIC _prestart
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PUBLIC __iar_program_start
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IMPORT _vector_table
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IMPORT MMUTable
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IMPORT __cmain
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IMPORT Xil_ExceptionInit
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IMPORT XSmc_NorInit
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IMPORT XSmc_SramInit
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IMPORT Init_Uart
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IMPORT XTime_SetTime
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PSS_L2CC_BASE_ADDR EQU 0xF8F02000
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PSS_SLCR_BASE_ADDR EQU 0xF8000000
|
||||
|
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RESERVED EQU 0x0fffff00
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TblBase EQU MMUTable
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LRemap EQU 0xFE00000F ; set the base address of the peripheral block as not shared
|
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L2CCWay EQU (PSS_L2CC_BASE_ADDR + 0x077C) ;(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_INVLD_WAY_OFFSET)
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L2CCSync EQU (PSS_L2CC_BASE_ADDR + 0x0730) ;(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_SYNC_OFFSET)
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L2CCCrtl EQU (PSS_L2CC_BASE_ADDR + 0x0100) ;(PSS_L2CC_BASE_ADDR + PSS_L2CC_CNTRL_OFFSET)
|
||||
L2CCAuxCrtl EQU (PSS_L2CC_BASE_ADDR + 0x0104) ;(PSS_L2CC_BASE_ADDR + XPSS_L2CC_AUX_CNTRL_OFFSET)
|
||||
L2CCTAGLatReg EQU (PSS_L2CC_BASE_ADDR + 0x0108) ;(PSS_L2CC_BASE_ADDR + XPSS_L2CC_TAG_RAM_CNTRL_OFFSET)
|
||||
L2CCDataLatReg EQU (PSS_L2CC_BASE_ADDR + 0x010C) ;(PSS_L2CC_BASE_ADDR + XPSS_L2CC_DATA_RAM_CNTRL_OFFSET)
|
||||
L2CCIntClear EQU (PSS_L2CC_BASE_ADDR + 0x0220) ;(PSS_L2CC_BASE_ADDR + XPSS_L2CC_IAR_OFFSET)
|
||||
L2CCIntRaw EQU (PSS_L2CC_BASE_ADDR + 0x021C) ;(PSS_L2CC_BASE_ADDR + XPSS_L2CC_ISR_OFFSET)
|
||||
|
||||
SLCRlockReg EQU (PSS_SLCR_BASE_ADDR + 0x04) ;(PSS_SLCR_BASE_ADDR + XPSS_SLCR_LOCK_OFFSET)
|
||||
SLCRUnlockReg EQU (PSS_SLCR_BASE_ADDR + 0x08) ;(PSS_SLCR_BASE_ADDR + XPSS_SLCR_UNLOCK_OFFSET)
|
||||
SLCRL2cRamReg EQU (PSS_SLCR_BASE_ADDR + 0xA1C) ;(PSS_SLCR_BASE_ADDR + XPSS_SLCR_L2C_RAM_OFFSET)
|
||||
|
||||
/* workaround for simulation not working when L1 D and I caches,MMU and L2 cache enabled - DT568997 */
|
||||
#if SIM_MODE == 1
|
||||
CRValMmuCac EQU 00000000000000b ; Disable IDC, and MMU
|
||||
#else
|
||||
CRValMmuCac EQU 01000000000101b ; Enable IDC, and MMU
|
||||
#endif
|
||||
CRValHiVectorAddr EQU 10000000000000b ; Set the Vector address to high, 0xFFFF0000
|
||||
|
||||
L2CCAuxControl EQU 0x72360000 ; Enable all prefetching, Way Size (16 KB) and High Priority for SO and Dev Reads Enable
|
||||
L2CCControl EQU 0x01 ; Enable L2CC
|
||||
L2CCTAGLatency EQU 0x0111 ; 7 Cycles of latency for TAG RAM
|
||||
L2CCDataLatency EQU 0x0121 ; 7 Cycles of latency for DATA RAM
|
||||
|
||||
SLCRlockKey EQU 0x767B ; SLCR lock key
|
||||
SLCRUnlockKey EQU 0xDF0D ; SLCR unlock key
|
||||
SLCRL2cRamConfig EQU 0x00020202 ; SLCR L2C ram configuration
|
||||
|
||||
|
||||
vector_base EQU _vector_table
|
||||
|
||||
FPEXC_EN EQU 0x40000000 ; FPU enable bit, (1 << 30)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
|
||||
; this initializes the various processor modes
|
||||
|
||||
_prestart
|
||||
__iar_program_start
|
||||
|
||||
#if XPAR_CPU_ID==0
|
||||
; only allow cp0 through
|
||||
mrc p15,0,r1,c0,c0,5
|
||||
and r1, r1, #0xf
|
||||
cmp r1, #0
|
||||
beq OKToRun
|
||||
EndlessLoop0
|
||||
wfe
|
||||
b EndlessLoop0
|
||||
|
||||
#elif XPAR_CPU_ID==1
|
||||
; only allow cp1 through
|
||||
mrc p15,0,r1,c0,c0,5
|
||||
and r1, r1, #0xf
|
||||
cmp r1, #1
|
||||
beq OKToRun
|
||||
EndlessLoop1
|
||||
wfe
|
||||
b EndlessLoop1
|
||||
#endif
|
||||
|
||||
OKToRun
|
||||
mrc p15, 0, r0, c0, c0, 0 ; Get the revision
|
||||
and r5, r0, #0x00f00000
|
||||
and r6, r0, #0x0000000f
|
||||
orr r6, r6, r5, lsr #20-4
|
||||
|
||||
#ifdef CONFIG_ARM_ERRATA_742230
|
||||
cmp r6, #0x22 ; only present up to r2p2
|
||||
mrcle p15, 0, r10, c15, c0, 1 ; read diagnostic register
|
||||
orrle r10, r10, #1 << 4 ; set bit #4
|
||||
mcrle p15, 0, r10, c15, c0, 1 ; write diagnostic register
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARM_ERRATA_743622
|
||||
teq r5, #0x00200000 ; only present in r2p*
|
||||
mrceq p15, 0, r10, c15, c0, 1 ; read diagnostic register
|
||||
orreq r10, r10, #1 << 6 ; set bit #6
|
||||
mcreq p15, 0, r10, c15, c0, 1 ; write diagnostic register
|
||||
#endif
|
||||
|
||||
; set VBAR to the _vector_table address in linker script
|
||||
ldr r0, =vector_base
|
||||
mcr p15, 0, r0, c12, c0, 0
|
||||
|
||||
;set scu enable bit in scu
|
||||
ldr r7, =0xf8f00000
|
||||
ldr r0, [r7]
|
||||
orr r0, r0, #0x1
|
||||
str r0, [r7]
|
||||
|
||||
;invalidate scu
|
||||
ldr r7, =0xf8f0000c
|
||||
ldr r6, =0xffff
|
||||
str r6, [r7]
|
||||
|
||||
; Write to ACTLR
|
||||
mrc p15, 0,r0, c1, c0, 1 ; Read ACTLR
|
||||
orr r0, r0, #(0x01 << 6) ; SMP bit
|
||||
orr r0, r0, #(0x01 ) ; Cache/TLB maintenance broadcast
|
||||
mcr p15, 0,r0, c1, c0, 1 ; Write ACTLR
|
||||
|
||||
; Invalidate caches and TLBs
|
||||
mov r0,#0 ; r0 = 0
|
||||
mcr p15, 0, r0, c8, c7, 0 ; invalidate TLBs
|
||||
mcr p15, 0, r0, c7, c5, 0 ; invalidate icache
|
||||
mcr p15, 0, r0, c7, c5, 6 ; Invalidate branch predictor array
|
||||
bl invalidate_dcache ; invalidate dcache
|
||||
|
||||
; Invalidate L2c Cache
|
||||
; For AMP, assume running on CPU1. Don't initialize L2 Cache (up to Linux)
|
||||
#if USE_AMP!=1
|
||||
ldr r0,=L2CCCrtl ; Load L2CC base address base + control register
|
||||
mov r1, #0 ; force the disable bit
|
||||
str r1, [r0] ; disable the L2 Caches
|
||||
|
||||
ldr r0,=L2CCAuxCrtl ; Load L2CC base address base + Aux control register
|
||||
ldr r1,[r0] ; read the register
|
||||
ldr r2,=L2CCAuxControl ; set the default bits
|
||||
orr r1,r1,r2
|
||||
str r1, [r0] ; store the Aux Control Register
|
||||
|
||||
ldr r0,=L2CCTAGLatReg ; Load L2CC base address base + TAG Latency address
|
||||
ldr r1,=L2CCTAGLatency ; set the latencies for the TAG
|
||||
str r1, [r0] ; store the TAG Latency register Register
|
||||
|
||||
ldr r0,=L2CCDataLatReg ; Load L2CC base address base + Data Latency address
|
||||
ldr r1,=L2CCDataLatency ; set the latencies for the Data
|
||||
str r1, [r0] ; store the Data Latency register Register
|
||||
|
||||
ldr r0,=L2CCWay ; Load L2CC base address base + way register
|
||||
ldr r2, =0xFFFF
|
||||
str r2, [r0] ; force invalidate
|
||||
|
||||
ldr r0,=L2CCSync ; need to poll 0x730, PSS_L2CC_CACHE_SYNC_OFFSET
|
||||
; Load L2CC base address base + sync register
|
||||
; poll for completion
|
||||
Sync
|
||||
ldr r1, [r0]
|
||||
cmp r1, #0
|
||||
bne Sync
|
||||
|
||||
ldr r0,=L2CCIntRaw ; clear pending interrupts
|
||||
ldr r1,[r0]
|
||||
ldr r0,=L2CCIntClear
|
||||
str r1,[r0]
|
||||
#endif
|
||||
|
||||
; Disable MMU, if enabled
|
||||
mrc p15, 0, r0, c1, c0, 0 ; read CP15 register 1
|
||||
bic r0, r0, #0x1 ; clear bit 0
|
||||
mcr p15, 0, r0, c1, c0, 0 ; write value back
|
||||
|
||||
#ifdef SHAREABLE_DDR
|
||||
; Mark the entire DDR memory as shareable
|
||||
ldr r3, =0x3ff ; 1024 entries to cover 1G DDR
|
||||
ldr r0, =TblBase ; MMU Table address in memory
|
||||
ldr r2, =0x15de6 ; S=1, TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1
|
||||
shareable_loop
|
||||
str r2, [r0] ; write the entry to MMU table
|
||||
add r0, r0, #0x4 ; next entry in the table
|
||||
add r2, r2, #0x100000 ; next section
|
||||
subs r3, r3, #1
|
||||
bge shareable_loop ; loop till 1G is covered
|
||||
#endif
|
||||
|
||||
; In case of AMP, map virtual address 0x20000000 to 0x00000000 and mark it as non-cacheable
|
||||
#if USE_AMP==1
|
||||
ldr r3, =0x1ff ; 512 entries to cover 512MB DDR
|
||||
ldr r0, =TblBase ; MMU Table address in memory
|
||||
add r0, r0, #0x800 ; Address of entry in MMU table, for 0x20000000
|
||||
ldr r2, =0x0c02 ; S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b0
|
||||
mmu_loop
|
||||
str r2, [r0] ; write the entry to MMU table
|
||||
add r0, r0, #0x4 ; next entry in the table
|
||||
add r2, r2, #0x100000 ; next section
|
||||
subs r3, r3, #1
|
||||
bge mmu_loop ; loop till 512MB is covered
|
||||
#endif
|
||||
|
||||
mrs r0, cpsr ; get the current PSR
|
||||
mvn r1, #0x1f ; set up the irq stack pointer
|
||||
and r2, r1, r0
|
||||
orr r2, r2, #0x12 ; IRQ mode
|
||||
msr cpsr, r2 ; was cpsr, apsr is considered synonym
|
||||
ldr r13,=SFE(IRQ_STACK) ; IRQ stack pointer
|
||||
|
||||
mrs r0, cpsr ; get the current PSR
|
||||
mvn r1, #0x1f ; set up the supervisor stack pointer
|
||||
and r2, r1, r0
|
||||
orr r2, r2, #0x13 ; supervisor mode
|
||||
msr cpsr, r2 ; was cpsr, apsr is considered synonym
|
||||
ldr r13,=SFE(SVC_STACK) ; Supervisor stack pointer
|
||||
|
||||
mrs r0, cpsr ; get the current PSR
|
||||
mvn r1, #0x1f ; set up the Abort stack pointer
|
||||
and r2, r1, r0
|
||||
orr r2, r2, #0x17 ; Abort mode
|
||||
msr cpsr, r2 ; was cpsr, apsr is considered synonym
|
||||
ldr r13,=SFE(ABT_STACK) ; Abort stack pointer
|
||||
|
||||
mrs r0, cpsr ; was cpsr, get the current PSR
|
||||
mvn r1, #0x1f ; set up the FIQ stack pointer
|
||||
and r2, r1, r0
|
||||
orr r2, r2, #0x11 ; FIQ mode
|
||||
msr cpsr, r2 ; was cpsr
|
||||
ldr r13,=SFE(FIQ_STACK) ; FIQ stack pointer
|
||||
|
||||
mrs r0, cpsr ; was cpsr, get the current PSR
|
||||
mvn r1, #0x1f ; set up the Undefine stack pointer
|
||||
and r2, r1, r0
|
||||
orr r2, r2, #0x1b ; Undefine mode
|
||||
msr cpsr, r2 ; was cpsr
|
||||
ldr r13,=SFE(UND_STACK) ; Undefine stack pointer
|
||||
|
||||
mrs r0, cpsr ; was cpsr, get the current PSR
|
||||
mvn r1, #0x1f ; set up the system stack pointer
|
||||
and r2, r1, r0
|
||||
orr r2, r2, #0x1f ; SYS mode
|
||||
msr cpsr, r2 ; was cpsr, apsr is considered synonym
|
||||
ldr r13,=SFE(CSTACK) ; SYS stack pointer
|
||||
|
||||
; enable MMU and cache
|
||||
|
||||
ldr r0,=TblBase ; Load MMU translation table base
|
||||
orr r0, r0, #0x5B ; Outer-cacheable, WB
|
||||
mcr p15, 0, r0, c2, c0, 0 ; TTB0
|
||||
|
||||
mvn r0,#0 ; Load MMU domains -- all ones=manager
|
||||
mcr p15,0,r0,c3,c0,0
|
||||
|
||||
; Enable mmu, icahce and dcache
|
||||
ldr r0,=CRValMmuCac
|
||||
|
||||
mcr p15,0,r0,c1,c0,0 ; Enable cache and MMU
|
||||
dsb ; dsb allow the MMU to start up
|
||||
isb ; isb flush prefetch buffer
|
||||
|
||||
; For AMP, assume running on CPU1. Don't initialize L2 Cache (up to Linux)
|
||||
#if USE_AMP!=1
|
||||
ldr r0,=SLCRUnlockReg ; Load SLCR base address base + unlock register
|
||||
ldr r1,=SLCRUnlockKey ; set unlock key
|
||||
str r1, [r0] ; Unlock SLCR
|
||||
|
||||
ldr r0,=SLCRL2cRamReg ; Load SLCR base address base + l2c Ram Control register ldr r1,=SLCRL2cRamConfig ; set the configuration value */
|
||||
str r1, [r0] ; store the L2c Ram Control Register
|
||||
|
||||
ldr r0,=SLCRlockReg ; Load SLCR base address base + lock register
|
||||
ldr r1,=SLCRlockKey ; set lock key
|
||||
str r1, [r0] ; lock SLCR
|
||||
ldr r0,=L2CCCrtl ; Load L2CC base address base + control register
|
||||
ldr r1,[r0] ; read the register
|
||||
mov r2, #L2CCControl ; set the enable bit
|
||||
orr r1,r1,r2
|
||||
str r1, [r0] ; enable the L2 Caches
|
||||
#endif
|
||||
|
||||
mov r0, r0
|
||||
mrc p15, 0, r1, c1, c0, 2 ; read cp access control register (CACR) into r1
|
||||
orr r1, r1, #(0xf << 20) ; enable full access for p10 & p11
|
||||
mcr p15, 0, r1, c1, c0, 2 ; write back into CACR
|
||||
|
||||
; enable vfp
|
||||
fmrx r1, FPEXC ; read the exception register
|
||||
orr r1,r1, #FPEXC_EN ; set VFP enable bit, leave the others in orig state
|
||||
fmxr FPEXC, r1 ; write back the exception register
|
||||
|
||||
mrc p15, 0, r0, c1, c0, 0 ; flow prediction enable
|
||||
orr r0, r0, #(0x01 << 11) ; #0x8000
|
||||
mcr p15,0,r0,c1,c0,0
|
||||
|
||||
mrc p15, 0, r0, c1, c0, 1 ; read Auxiliary Control Register
|
||||
orr r0, r0, #(0x1 << 2) ; enable Dside prefetch
|
||||
orr r0, r0, #(0x1 << 1) ; enable L2 prefetch
|
||||
mcr p15, 0, r0, c1, c0, 1 ; write Auxiliary Control Register
|
||||
|
||||
; Initialize the vector table
|
||||
;bl Xil_ExceptionInit
|
||||
#ifdef PEEP
|
||||
; Initialize STDOUT to 115200bps
|
||||
bl Init_Uart
|
||||
|
||||
bl XSmc_NorInit
|
||||
|
||||
bl XSmc_SramInit
|
||||
#endif
|
||||
|
||||
; Clear cp15 regs with unknown reset values
|
||||
mov r0, #0x0
|
||||
mcr p15, 0, r0, c5, c0, 0 ; DFSR
|
||||
mcr p15, 0, r0, c5, c0, 1 ; IFSR
|
||||
mcr p15, 0, r0, c6, c0, 0 ; DFAR
|
||||
mcr p15, 0, r0, c6, c0, 2 ; IFAR
|
||||
mcr p15, 0, r0, c9, c13, 2 ; PMXEVCNTR
|
||||
mcr p15, 0, r0, c13, c0, 2 ; TPIDRURW
|
||||
mcr p15, 0, r0, c13, c0, 3 ; TPIDRURO
|
||||
mcr p15, 5, r0, c15, c5, 2 ; Write Lockdown TLB VA
|
||||
|
||||
; Reset and start Cycle Counter
|
||||
mov r2, #0x80000000 ; clear overflow
|
||||
mcr p15, 0, r2, c9, c12, 3
|
||||
mov r2, #0xd ; D, C, E
|
||||
mcr p15, 0, r2, c9, c12, 0
|
||||
mov r2, #0x80000000 ; enable cycle counter
|
||||
mcr p15, 0, r2, c9, c12, 1
|
||||
|
||||
; Reset and start Global Timer
|
||||
mov r0, #0x0
|
||||
mov r1, #0x0
|
||||
bl XTime_SetTime
|
||||
|
||||
; make sure argc and argv are valid
|
||||
mov r0, #0
|
||||
mov r1, #0
|
||||
b __cmain ; jump to C startup code
|
||||
|
||||
and r0, r0, r0 ; no op
|
||||
|
||||
Ldone b Ldone ; Paranoia: we should never get here
|
||||
|
||||
|
||||
; *************************************************************************
|
||||
; *
|
||||
; * invalidate_dcache - invalidate the entire d-cache by set/way
|
||||
; *
|
||||
; * Note: for Cortex-A9, there is no cp instruction for invalidating
|
||||
; * the whole D-cache. Need to invalidate each line.
|
||||
; *
|
||||
; *************************************************************************
|
||||
|
||||
invalidate_dcache
|
||||
mrc p15, 1, r0, c0, c0, 1 ; read CLIDR
|
||||
ands r3, r0, #0x7000000
|
||||
mov r3, r3, lsr #23 ; cache level value (naturally aligned)
|
||||
beq finished
|
||||
mov r10, #0 ; start with level 0
|
||||
loop1
|
||||
add r2, r10, r10, lsr #1 ; work out 3xcachelevel
|
||||
mov r1, r0, lsr r2 ; bottom 3 bits are the Cache type for this level
|
||||
and r1, r1, #7 ; get those 3 bits alone
|
||||
cmp r1, #2
|
||||
blt skip ; no cache or only instruction cache at this level
|
||||
mcr p15, 2, r10, c0, c0, 0 ; write the Cache Size selection register
|
||||
isb ; isb to sync the change to the CacheSizeID reg
|
||||
mrc p15, 1, r1, c0, c0, 0 ; reads current Cache Size ID register
|
||||
and r2, r1, #7 ; extract the line length field
|
||||
add r2, r2, #4 ; add 4 for the line length offset (log2 16 bytes)
|
||||
ldr r4, =0x3ff
|
||||
ands r4, r4, r1, lsr #3 ; r4 is the max number on the way size (right aligned)
|
||||
clz r5, r4 ; r5 is the bit position of the way size increment
|
||||
ldr r7, =0x7fff
|
||||
ands r7, r7, r1, lsr #13 ; r7 is the max number of the index size (right aligned)
|
||||
loop2
|
||||
mov r9, r4 ; r9 working copy of the max way size (right aligned)
|
||||
loop3
|
||||
orr r11, r10, r9, lsl r5 ; factor in the way number and cache number into r11
|
||||
orr r11, r11, r7, lsl r2 ; factor in the index number
|
||||
mcr p15, 0, r11, c7, c6, 2 ; invalidate by set/way
|
||||
subs r9, r9, #1 ; decrement the way number
|
||||
bge loop3
|
||||
subs r7, r7, #1 ; decrement the index
|
||||
bge loop2
|
||||
skip
|
||||
add r10, r10, #2 ; increment the cache number
|
||||
cmp r3, r10
|
||||
bgt loop1
|
||||
|
||||
finished
|
||||
mov r10, #0 ; swith back to cache level 0
|
||||
mcr p15, 2, r10, c0, c0, 0 ; select current cache level in cssr
|
||||
dsb
|
||||
isb
|
||||
|
||||
bx lr
|
||||
|
||||
|
||||
END
|
||||
56
lib/bsp/standalone/src/cortexa9/iccarm/clock.c
Executable file
56
lib/bsp/standalone/src/cortexa9/iccarm/clock.c
Executable file
|
|
@ -0,0 +1,56 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/*
|
||||
* This is the default implementation of the "clock" function of the
|
||||
* standard library. It can be replaced with a system-specific
|
||||
* implementation.
|
||||
*
|
||||
* The "clock" function should return the processor time used by the
|
||||
* program from some implementation-defined start time. The value
|
||||
* should be such that if divided by the macro CLOCKS_PER_SEC the
|
||||
* result should yield the time in seconds.
|
||||
*
|
||||
* The value "(clock_t)-1" means that the processor time is not
|
||||
* available.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <time.h>
|
||||
|
||||
|
||||
clock_t (clock)(void)
|
||||
{
|
||||
return ((clock_t) -1);
|
||||
}
|
||||
|
||||
|
||||
41
lib/bsp/standalone/src/cortexa9/iccarm/close.c
Executable file
41
lib/bsp/standalone/src/cortexa9/iccarm/close.c
Executable file
|
|
@ -0,0 +1,41 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include <yfuns.h>
|
||||
|
||||
int __close(int fd)
|
||||
{
|
||||
(void)fd;
|
||||
return (0);
|
||||
|
||||
}
|
||||
|
||||
39
lib/bsp/standalone/src/cortexa9/iccarm/exit.c
Executable file
39
lib/bsp/standalone/src/cortexa9/iccarm/exit.c
Executable file
|
|
@ -0,0 +1,39 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <yfuns.h>
|
||||
|
||||
void exit(int arg)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
74
lib/bsp/standalone/src/cortexa9/iccarm/low_level_init.c
Executable file
74
lib/bsp/standalone/src/cortexa9/iccarm/low_level_init.c
Executable file
|
|
@ -0,0 +1,74 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/*
|
||||
* This module contains the function `__low_level_init', a function
|
||||
* that is called before the `main' function of the program. Normally
|
||||
* low-level initializations - such as setting the prefered interrupt
|
||||
* level or setting the watchdog - can be performed here.
|
||||
*
|
||||
* Note that this function is called before the data segments are
|
||||
* initialized, this means that this function cannot rely on the
|
||||
* values of global or static variables.
|
||||
*
|
||||
* When this function returns zero, the startup code will inhibit the
|
||||
* initialization of the data segments. The result is faster startup,
|
||||
* the drawback is that neither global nor static data will be
|
||||
* initialized.
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
int __low_level_init(void);
|
||||
|
||||
int __low_level_init(void)
|
||||
{
|
||||
/*==================================*/
|
||||
/* Initialize hardware. */
|
||||
/*==================================*/
|
||||
|
||||
/*==================================*/
|
||||
/* Choose if segment initialization */
|
||||
/* should be done or not. */
|
||||
/* Return: 0 to omit seg_init */
|
||||
/* 1 to run seg_init */
|
||||
/*==================================*/
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
58
lib/bsp/standalone/src/cortexa9/iccarm/lseek.c
Executable file
58
lib/bsp/standalone/src/cortexa9/iccarm/lseek.c
Executable file
|
|
@ -0,0 +1,58 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/*
|
||||
*
|
||||
* This is a template implementation of the "__lseek" function used by
|
||||
* the standard library. Replace it with a system-specific
|
||||
* implementation.
|
||||
*
|
||||
* The "__lseek" function makes the next file operation (__read or
|
||||
* __write) act on a new location. The parameter "whence" specifies
|
||||
* how the "offset" parameter should be interpreted according to the
|
||||
* following table:
|
||||
*
|
||||
* 0 (=SEEK_SET) - Goto location "offset".
|
||||
* 1 (=SEEK_CUR) - Go "offset" bytes from the current location.
|
||||
* 2 (=SEEK_END) - Go to "offset" bytes from the end.
|
||||
*
|
||||
* This function should return the current file position, or -1 on
|
||||
* failure.
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
#include <yfuns.h>
|
||||
|
||||
long __lseek(int handle, long offset, int whence)
|
||||
{
|
||||
return (-1);
|
||||
}
|
||||
54
lib/bsp/standalone/src/cortexa9/iccarm/open.c
Executable file
54
lib/bsp/standalone/src/cortexa9/iccarm/open.c
Executable file
|
|
@ -0,0 +1,54 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/*
|
||||
*
|
||||
* This is a template implementation of the "__open" function used by
|
||||
* the standard library. Replace it with a system-specific
|
||||
* implementation.
|
||||
*
|
||||
* The "__open" function opens the file named "filename" as specified
|
||||
* by "mode".
|
||||
* open -- open a file descriptor. We don't have a filesystem, so
|
||||
* we return an error.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <yfuns.h>
|
||||
|
||||
|
||||
int __open(const char * filename, int mode)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
54
lib/bsp/standalone/src/cortexa9/iccarm/read.c
Executable file
54
lib/bsp/standalone/src/cortexa9/iccarm/read.c
Executable file
|
|
@ -0,0 +1,54 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*
|
||||
*
|
||||
*
|
||||
* The "__read" function reads a number of bytes, at most "size" into
|
||||
* the memory area pointed to by "buffer". It returns the number of
|
||||
* bytes read, 0 at the end of the file, or _LLIO_ERROR if failure
|
||||
* occurs.
|
||||
*
|
||||
* The template implementation below should return a
|
||||
* character value, or -1 on failure.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <yfuns.h>
|
||||
|
||||
|
||||
size_t __read(int handle, unsigned char * buffer, size_t size)
|
||||
{
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
|
||||
48
lib/bsp/standalone/src/cortexa9/iccarm/remove.c
Executable file
48
lib/bsp/standalone/src/cortexa9/iccarm/remove.c
Executable file
|
|
@ -0,0 +1,48 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/*
|
||||
*
|
||||
* The "remove" function should remove the file named "filename". It
|
||||
* should return 0 on success and nonzero on failure.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
|
||||
|
||||
int remove(const char * filename)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
139
lib/bsp/standalone/src/cortexa9/iccarm/translation_table.s
Executable file
139
lib/bsp/standalone/src/cortexa9/iccarm/translation_table.s
Executable file
|
|
@ -0,0 +1,139 @@
|
|||
;******************************************************************************
|
||||
;
|
||||
; Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
|
||||
;
|
||||
; Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
; of this software and associated documentation files (the "Software"), to deal
|
||||
; in the Software without restriction, including without limitation the rights
|
||||
; to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
; copies of the Software, and to permit persons to whom the Software is
|
||||
; furnished to do so, subject to the following conditions:
|
||||
;
|
||||
; The above copyright notice and this permission notice shall be included in
|
||||
; all copies or substantial portions of the Software.
|
||||
;
|
||||
; Use of the Software is limited solely to applications:
|
||||
; (a) running on a Xilinx device, or
|
||||
; (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
;
|
||||
; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
; XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
; WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
; OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
; SOFTWARE.
|
||||
;
|
||||
; Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
; in advertising or otherwise to promote the sale, use or other dealings in
|
||||
; this Software without prior written authorization from Xilinx.
|
||||
;
|
||||
;*****************************************************************************
|
||||
;****************************************************************************
|
||||
;**
|
||||
; @file translation_table.s
|
||||
;
|
||||
; This file contains the initialization for the MMU table in RAM
|
||||
; needed by the Cortex A9 processor
|
||||
;
|
||||
; <pre>
|
||||
; MODIFICATION HISTORY:
|
||||
;
|
||||
; Ver Who Date Changes
|
||||
; ----- ---- -------- ---------------------------------------------------
|
||||
; 1.00a ecm 10/20/09 Initial version
|
||||
; 3.07a sgd 07/05/2012 Configuring device address spaces as shareable device
|
||||
; instead of strongly-ordered.
|
||||
; </pre>
|
||||
;
|
||||
; @note
|
||||
;
|
||||
; None.
|
||||
;
|
||||
;****************************************************************************
|
||||
EXPORT MMUTable
|
||||
|
||||
;ARMCC AREA |.mmu_tbl|,CODE,ALIGN=14
|
||||
; RSEG mmu_tbl:CODE:ROOT (14)
|
||||
SECTION .mmu_tbl:CODE:ROOT(14)
|
||||
|
||||
MMUTable
|
||||
; Each table entry occupies one 32-bit word and there are
|
||||
; 4096 entries, so the entire table takes up 16KB.
|
||||
; Each entry covers a 1MB section.
|
||||
|
||||
|
||||
; 0x00000000 - 0x3ffffff (DDR Cacheable)
|
||||
count SETA 0
|
||||
sect SETA 0
|
||||
REPT 0x400
|
||||
DCD sect + 0x15de6 ; S=1, TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1
|
||||
sect SETA sect+0x100000
|
||||
count SETA count+1
|
||||
ENDR
|
||||
|
||||
; 0x40000000 - 0x7fffffff (GpAxi0)
|
||||
count SETA 0
|
||||
REPT 0x400
|
||||
DCD sect + 0xc06 ; S=0, TEX=b010 AP=b11, Domain=b0, C=b0, B=b0
|
||||
sect SETA sect+0x100000
|
||||
count SETA count+1
|
||||
ENDR
|
||||
|
||||
; 0x80000000 - 0xbfffffff (GpAxi1)
|
||||
count SETA 0
|
||||
REPT 0x400
|
||||
DCD sect + 0xc06 ; S=0, TEX=b010 AP=b11, Domain=b0, C=b0, B=b0
|
||||
sect SETA sect+0x100000
|
||||
count SETA count+1
|
||||
ENDR
|
||||
|
||||
; 0xc0000000 - 0xdfffffff (undef)
|
||||
count SETA 0
|
||||
REPT 0x200
|
||||
DCD sect ; S=0, TEX=b000 AP=b00, Domain=b0, C=b0, B=b0
|
||||
sect SETA sect+0x100000
|
||||
count SETA count+1
|
||||
ENDR
|
||||
|
||||
; 0xe0000000 - 0xefffffff (IOP dev)
|
||||
count SETA 0
|
||||
REPT 0x100
|
||||
DCD sect + 0xc06 ; S=0, TEX=b010 AP=b11, Domain=b0, C=b0, B=b0
|
||||
sect SETA sect+0x100000
|
||||
count SETA count+1
|
||||
ENDR
|
||||
|
||||
; 0xf0000000 - 0xf7ffffff (reserved)
|
||||
count SETA 0
|
||||
REPT 0x80
|
||||
DCD sect ; S=0, TEX=b000 AP=b00, Domain=b0, C=b0, B=b0
|
||||
sect SETA sect+0x100000
|
||||
count SETA count+1
|
||||
ENDR
|
||||
|
||||
; 0xf8000000 - 0xf9ffffff (APB device regs)
|
||||
count SETA 0
|
||||
REPT 0x20
|
||||
DCD sect + 0xc06 ; S=0, TEX=b010 AP=b11, Domain=b0, C=b0, B=b0
|
||||
sect SETA sect+0x100000
|
||||
count SETA count+1
|
||||
ENDR
|
||||
|
||||
; 0xfa000000 - 0xfbffffff (reserved)
|
||||
count SETA 0
|
||||
REPT 0x20
|
||||
DCD sect ; S=0, TEX=b000 AP=b00, Domain=b0, C=b0, B=b0
|
||||
sect SETA sect+0x100000
|
||||
count SETA count+1
|
||||
ENDR
|
||||
|
||||
; 0xfc000000 - 0xfffffff (OCM/QSPI)
|
||||
count SETA 0
|
||||
REPT 0x40
|
||||
DCD sect + 0x15de6 ; S=1, TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1
|
||||
sect SETA sect+0x100000
|
||||
count SETA count+1
|
||||
ENDR
|
||||
|
||||
END
|
||||
132
lib/bsp/standalone/src/cortexa9/iccarm/write.c
Executable file
132
lib/bsp/standalone/src/cortexa9/iccarm/write.c
Executable file
|
|
@ -0,0 +1,132 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/*
|
||||
* The "__write" function should output "size" number of bytes from
|
||||
* "buffer" in some application-specific way. It should return the
|
||||
* number of characters written, or _LLIO_ERROR on failure.
|
||||
*
|
||||
* If "buffer" is zero then __write should perform flushing of
|
||||
* internal buffers, if any. In this case "handle" can be -1 to
|
||||
* indicate that all handles should be flushed.
|
||||
*
|
||||
* The template implementation below assumes that the application
|
||||
* provides the function "MyLowLevelPutchar". It should return the
|
||||
* character written, or -1 on failure.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <yfuns.h>
|
||||
|
||||
|
||||
#if 0
|
||||
/*
|
||||
* If the __write implementation uses internal buffering, uncomment
|
||||
* the following line to ensure that we are called with "buffer" as 0
|
||||
* (i.e. flush) when the application terminates.
|
||||
*/
|
||||
|
||||
size_t __write(int handle, const unsigned char * buffer, size_t size)
|
||||
{
|
||||
unsigned int volatile *uart_base = (unsigned int *)0xE0001000;
|
||||
int i;
|
||||
|
||||
for (i =0; i < size;i++) {
|
||||
/* wait if TNFUL */
|
||||
while (*(uart_base + 11) & (1 << 14)) ;
|
||||
*(uart_base + 12) = buffer[i];
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#include "xparameters.h"
|
||||
#include "xil_printf.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
int _write (int fd, char* buf, int nbytes);
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* write -- write bytes to the serial port. Ignore fd, since
|
||||
* stdout and stderr are the same. Since we have no filesystem,
|
||||
* open will only return an error.
|
||||
*/
|
||||
int
|
||||
write (int fd, char* buf, int nbytes)
|
||||
|
||||
{
|
||||
#ifdef STDOUT_BASEADDRESS
|
||||
int i;
|
||||
|
||||
(void)fd;
|
||||
for (i = 0; i < nbytes; i++) {
|
||||
if (*(buf + i) == '\n') {
|
||||
outbyte ('\r');
|
||||
}
|
||||
outbyte (*(buf + i));
|
||||
}
|
||||
return (nbytes);
|
||||
#else
|
||||
(void)fd;
|
||||
(void)buf;
|
||||
(void)nbytes;
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
size_t
|
||||
__write (int fd, const unsigned char* buf, size_t nbytes)
|
||||
{
|
||||
#ifdef STDOUT_BASEADDRESS
|
||||
int i;
|
||||
|
||||
(void)fd;
|
||||
for (i = 0; i < nbytes; i++) {
|
||||
if (*(buf + i) == '\n') {
|
||||
outbyte ('\r');
|
||||
}
|
||||
outbyte (*(buf + i));
|
||||
}
|
||||
return (nbytes);
|
||||
#else
|
||||
(void)fd;
|
||||
(void)buf;
|
||||
(void)nbytes;
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
69
lib/bsp/standalone/src/cortexa9/iccarm/xpseudo_asm_iccarm.c
Executable file
69
lib/bsp/standalone/src/cortexa9/iccarm/xpseudo_asm_iccarm.c
Executable file
|
|
@ -0,0 +1,69 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xpseudo_asm_iccarm.c
|
||||
*
|
||||
* This file contains functions for ARM register handling.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -----------------------------------------------
|
||||
* 3.12a asa 11/2/13 First Release
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/***************************** Include Files ********************************/
|
||||
|
||||
#include "xpseudo_asm_iccarm.h"
|
||||
|
||||
/************************** Constant Definitions ****************************/
|
||||
|
||||
/**************************** Type Definitions ******************************/
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions ********************/
|
||||
|
||||
/************************** Variable Definitions ****************************/
|
||||
|
||||
/************************** Function Prototypes *****************************/
|
||||
|
||||
/* embedded assembler instructions */
|
||||
int mfcpsr (void)
|
||||
{
|
||||
int rval;
|
||||
asm("mrs %0, cpsr" : "=r"(rval));
|
||||
return rval;
|
||||
}
|
||||
170
lib/bsp/standalone/src/cortexa9/iccarm/xpseudo_asm_iccarm.h
Executable file
170
lib/bsp/standalone/src/cortexa9/iccarm/xpseudo_asm_iccarm.h
Executable file
|
|
@ -0,0 +1,170 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xpseudo_asm_iccarm.h
|
||||
*
|
||||
* This header file contains macros for using inline assembler code. It is
|
||||
* written specifically for the IAR C/C++ compiler.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- -------- -------- -----------------------------------------------
|
||||
* 1.00a ecm/sdm 10/28/09 First release
|
||||
* 3.12a asa 11/02/13 Removed the macro mfcpsr to make it a function.
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef XPSEUDO_ASM_ICCARM_H /* prevent circular inclusions */
|
||||
#define XPSEUDO_ASM_ICCARM_H /* by using protection macros */
|
||||
|
||||
/***************************** Include Files ********************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/************************** Constant Definitions ****************************/
|
||||
|
||||
/**************************** Type Definitions ******************************/
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions ********************/
|
||||
|
||||
/* necessary for pre-processor */
|
||||
#define stringify(s) tostring(s)
|
||||
#define tostring(s) #s
|
||||
|
||||
/* pseudo assembler instructions */
|
||||
|
||||
#define mtcpsr(v) __asm volatile(\
|
||||
"msr cpsr,%0\n"\
|
||||
: : "r" (v)\
|
||||
)
|
||||
|
||||
#define cpsiei() __asm volatile("cpsie i\n")
|
||||
#define cpsidi() __asm volatile("cpsid i\n")
|
||||
|
||||
#define cpsief() __asm volatile("cpsie f\n")
|
||||
#define cpsidf() __asm volatile("cpsid f\n")
|
||||
|
||||
|
||||
|
||||
#define mtgpr(rn, v) __asm volatile(\
|
||||
"mov r" stringify(rn) ", %0 \n"\
|
||||
: : "r" (v)\
|
||||
)
|
||||
|
||||
#define mfgpr(rn) ({unsigned int rval; \
|
||||
__asm volatile(\
|
||||
"mov %0,r" stringify(rn) "\n"\
|
||||
: "=r" (rval)\
|
||||
);\
|
||||
rval;\
|
||||
})
|
||||
|
||||
/* memory synchronization operations */
|
||||
|
||||
/* Instruction Synchronization Barrier */
|
||||
#define isb() __asm volatile ("isb" : : : "memory")
|
||||
|
||||
/* Data Synchronization Barrier */
|
||||
#define dsb() __asm volatile ("dsb" : : : "memory")
|
||||
|
||||
/* Data Memory Barrier */
|
||||
#define dmb() __asm volatile ("dmb" : : : "memory")
|
||||
|
||||
|
||||
/* Memory Operations */
|
||||
#define ldr(adr) ({unsigned long rval; \
|
||||
__asm volatile(\
|
||||
"ldr %0,[%1]"\
|
||||
: "=r" (rval) : "r" (adr)\
|
||||
);\
|
||||
rval;\
|
||||
})
|
||||
|
||||
#define ldrb(adr) ({unsigned char rval; \
|
||||
__asm volatile(\
|
||||
"ldrb %0,[%1]"\
|
||||
: "=r" (rval) : "r" (adr)\
|
||||
);\
|
||||
rval;\
|
||||
})
|
||||
|
||||
#define str(adr, val) __asm volatile(\
|
||||
"str %0,[%1]\n"\
|
||||
: : "r" (val), "r" (adr)\
|
||||
)
|
||||
|
||||
#define strb(adr, val) __asm volatile(\
|
||||
"strb %0,[%1]\n"\
|
||||
: : "r" (val), "r" (adr)\
|
||||
)
|
||||
|
||||
/* Count leading zeroes (clz) */
|
||||
#define clz(arg) ({unsigned char rval; \
|
||||
__asm volatile(\
|
||||
"clz %0,%1"\
|
||||
: "=r" (rval) : "r" (arg)\
|
||||
);\
|
||||
rval;\
|
||||
})
|
||||
|
||||
/* CP15 operations */
|
||||
#define mtcp(rn, v) __asm volatile(\
|
||||
"mcr " rn "\n"\
|
||||
: : "r" (v)\
|
||||
);
|
||||
|
||||
/*#define mfcp(rn) ({unsigned int rval; \
|
||||
__asm volatile(\
|
||||
"mrc " rn "\n"\
|
||||
: "=r" (rval)\
|
||||
);\
|
||||
rval;\
|
||||
}) */
|
||||
|
||||
#define mfcp(rn, v) __asm volatile ("mrc " rn : "=r" (v));
|
||||
|
||||
/************************** Variable Definitions ****************************/
|
||||
|
||||
/************************** Function Prototypes *****************************/
|
||||
int mfcpsr (void);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* XPSEUDO_ASM_ICCARM_H */
|
||||
|
|
@ -43,40 +43,43 @@
|
|||
* ----- ---- -------- -----------------------------------------------
|
||||
* 1.00a ecm 01/29/10 First release
|
||||
* 1.00a ecm 06/24/10 Moved the L1 and L2 specific function prototypes
|
||||
* to xil_cache_mach.h to give access to sophisticated users
|
||||
* to xil_cache_mach.h to give access to sophisticated users
|
||||
* 3.02a sdm 04/07/11 Updated Flush/InvalidateRange APIs to flush/invalidate
|
||||
* L1 and L2 caches in a single loop and used dsb, L2 sync
|
||||
* at the end of the loop.
|
||||
* L1 and L2 caches in a single loop and used dsb, L2 sync
|
||||
* at the end of the loop.
|
||||
* 3.04a sdm 01/02/12 Remove redundant dsb/dmb instructions in cache maintenance
|
||||
* APIs.
|
||||
* APIs.
|
||||
* 3.07a asa 07/16/12 Corrected the L1 and L2 cache invalidation order.
|
||||
* 3.07a sgd 09/18/12 Corrected the L2 cache enable and disable sequence.
|
||||
* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
|
||||
* 'xil_errata.h' for errata description
|
||||
* 'xil_errata.h' for errata description
|
||||
* 3.10a asa 05/13/13 Modified cache disable APIs. The L2 cache disable
|
||||
* operation was being done with L1 Data cache disabled. This is
|
||||
* fixed so that L2 cache disable operation happens independent of
|
||||
* L1 cache disable operation. This fixes CR #706464.
|
||||
* Changes are done to do a L2 cache sync (poll reg7_?cache_?sync).
|
||||
* This is done to fix the CR #700542.
|
||||
* operation was being done with L1 Data cache disabled. This is
|
||||
* fixed so that L2 cache disable operation happens independent of
|
||||
* L1 cache disable operation. This fixes CR #706464.
|
||||
* Changes are done to do a L2 cache sync (poll reg7_?cache_?sync).
|
||||
* This is done to fix the CR #700542.
|
||||
* 3.11a asa 09/23/13 Modified the Xil_DCacheFlushRange and
|
||||
* Xil_DCacheInvalidateRange to fix potential issues. Fixed other
|
||||
* relevant cache APIs to disable and enable back the interrupts.
|
||||
* This fixes CR #663885.
|
||||
* Xil_DCacheInvalidateRange to fix potential issues. Fixed other
|
||||
* relevant cache APIs to disable and enable back the interrupts.
|
||||
* This fixes CR #663885.
|
||||
* 3.11a asa 09/28/13 Made changes for L2 cache sync operation. It is found
|
||||
* out that for L2 cache flush/clean/invalidation by cache lines
|
||||
* does not need a cache sync as these are atomic nature. Similarly
|
||||
* figured out that for complete L2 cache flush/invalidation by way
|
||||
* we need to wait for some more time in a loop till the status
|
||||
* shows that the cache operation is completed.
|
||||
* out that for L2 cache flush/clean/invalidation by cache lines
|
||||
* does not need a cache sync as these are atomic nature. Similarly
|
||||
* figured out that for complete L2 cache flush/invalidation by way
|
||||
* we need to wait for some more time in a loop till the status
|
||||
* shows that the cache operation is completed.
|
||||
* 4.00 pkp 24/01/14 Modified Xil_DCacheInvalidateRange to fix the bug. Few
|
||||
* cache lines were missed to invalidate when unaligned address
|
||||
* invalidation was accommodated. That fixes CR #766768.
|
||||
* Also in Xil_L1DCacheInvalidate, while invalidating all L1D cache
|
||||
* stack memory which contains return address was invalidated. So
|
||||
* stack memory was flushed first and then L1D cache is invalidated.
|
||||
* This is done to fix CR #763829
|
||||
* cache lines were missed to invalidate when unaligned address
|
||||
* invalidation was accommodated. That fixes CR #766768.
|
||||
* Also in Xil_L1DCacheInvalidate, while invalidating all L1D cache
|
||||
* stack memory which contains return address was invalidated. So
|
||||
* stack memory was flushed first and then L1D cache is invalidated.
|
||||
* This is done to fix CR #763829
|
||||
* 4.01 asa 05/09/14 Made changes in cortexa9/xil_cache.c to fix CR# 798230.
|
||||
* 4.02 pkp 06/27/14 Added notes to Xil_L1DCacheInvalidateRange function for
|
||||
* explanation of CR#785243
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
|
@ -246,6 +249,51 @@ void Xil_DCacheInvalidateLine(unsigned int adr)
|
|||
* is modified (dirty), the modified contents are lost and are NOT
|
||||
* written to system memory before the line is invalidated.
|
||||
*
|
||||
* In this function, if start address or end address is not aligned to cache-line,
|
||||
* particular cache-line containing unaligned start or end address is flush first
|
||||
* and then invalidated the others as invalidating the same unaligned cache line
|
||||
* may result into loss of data. This issue raises few possibilities.
|
||||
*
|
||||
*
|
||||
* If the address to be invalidated is not cache-line aligned, the
|
||||
* following choices are available:
|
||||
* 1) Invalidate the cache line when required and do not bother much for the
|
||||
* side effects. Though it sounds good, it can result in hard-to-debug issues.
|
||||
* The problem is, if some other variable are allocated in the
|
||||
* same cache line and had been recently updated (in cache), the invalidation
|
||||
* would result in loss of data.
|
||||
*
|
||||
* 2) Flush the cache line first. This will ensure that if any other variable
|
||||
* present in the same cache line and updated recently are flushed out to memory.
|
||||
* Then it can safely be invalidated. Again it sounds good, but this can result
|
||||
* in issues. For example, when the invalidation happens
|
||||
* in a typical ISR (after a DMA transfer has updated the memory), then flushing
|
||||
* the cache line means, loosing data that were updated recently before the ISR
|
||||
* got invoked.
|
||||
*
|
||||
* Linux prefers the second one. To have uniform implementation (across standalone
|
||||
* and Linux), the second option is implemented.
|
||||
* This being the case, follwoing needs to be taken care of:
|
||||
* 1) Whenever possible, the addresses must be cache line aligned. Please nore that,
|
||||
* not just start address, even the end address must be cache line aligned. If that
|
||||
* is taken care of, this will always work.
|
||||
* 2) Avoid situations where invalidation has to be done after the data is updated by
|
||||
* peripheral/DMA directly into the memory. It is not tough to achieve (may be a bit
|
||||
* risky). The common use case to do invalidation is when a DMA happens. Generally
|
||||
* for such use cases, buffers can be allocated first and then start the DMA. The
|
||||
* practice that needs to be followed here is, immediately after buffer allocation
|
||||
* and before starting the DMA, do the invalidation. With this approach, invalidation
|
||||
* need not to be done after the DMA transfer is over.
|
||||
*
|
||||
* This is going to always work if done carefully.
|
||||
* However, the concern is, there is no guarantee that invalidate has not needed to be
|
||||
* done after DMA is complete. For example, because of some reasons if the first cache
|
||||
* line or last cache line (assuming the buffer in question comprises of multiple cache
|
||||
* lines) are brought into cache (between the time it is invalidated and DMA completes)
|
||||
* because of some speculative prefetching or reading data for a variable present
|
||||
* in the same cache line, then we will have to invalidate the cache after DMA is complete.
|
||||
*
|
||||
*
|
||||
* @param Start address of range to be invalidated.
|
||||
* @param Length of range to be invalidated in bytes.
|
||||
*
|
||||
|
|
@ -305,6 +353,9 @@ void Xil_DCacheInvalidateRange(unsigned int adr, unsigned len)
|
|||
/* Invalidate L1 Data cache line */
|
||||
__asm__ __volatile__("mcr " \
|
||||
XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (tempadr));
|
||||
#elif defined (__ICCARM__)
|
||||
__asm volatile ("mcr " \
|
||||
XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (tempadr));
|
||||
#else
|
||||
{ volatile register unsigned int Reg
|
||||
__asm(XREG_CP15_INVAL_DC_LINE_MVA_POC);
|
||||
|
|
@ -413,6 +464,9 @@ void Xil_DCacheFlushRange(unsigned int adr, unsigned len)
|
|||
/* Flush L1 Data cache line */
|
||||
__asm__ __volatile__("mcr " \
|
||||
XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (adr));
|
||||
#elif defined (__ICCARM__)
|
||||
__asm volatile ("mcr " \
|
||||
XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (adr));
|
||||
#else
|
||||
{ volatile register unsigned int Reg
|
||||
__asm(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC);
|
||||
|
|
@ -581,6 +635,9 @@ void Xil_ICacheInvalidateRange(unsigned int adr, unsigned len)
|
|||
/* Invalidate L1 I-cache line */
|
||||
__asm__ __volatile__("mcr " \
|
||||
XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (adr));
|
||||
#elif defined (__ICCARM__)
|
||||
__asm volatile ("mcr " \
|
||||
XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (adr));
|
||||
#else
|
||||
{ volatile register unsigned int Reg
|
||||
__asm(XREG_CP15_INVAL_IC_LINE_MVA_POU);
|
||||
|
|
@ -614,6 +671,8 @@ void Xil_L1DCacheEnable(void)
|
|||
/* enable caches only if they are disabled */
|
||||
#ifdef __GNUC__
|
||||
CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
|
||||
#elif defined (__ICCARM__)
|
||||
mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
|
||||
#else
|
||||
{ volatile register unsigned int Reg __asm(XREG_CP15_SYS_CONTROL);
|
||||
CtrlReg = Reg; }
|
||||
|
|
@ -652,6 +711,8 @@ void Xil_L1DCacheDisable(void)
|
|||
#ifdef __GNUC__
|
||||
/* disable the Data cache */
|
||||
CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
|
||||
#elif defined (__ICCARM__)
|
||||
mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
|
||||
#else
|
||||
{ volatile register unsigned int Reg __asm(XREG_CP15_SYS_CONTROL);
|
||||
CtrlReg = Reg; }
|
||||
|
|
@ -703,6 +764,8 @@ void Xil_L1DCacheInvalidate(void)
|
|||
|
||||
#ifdef __GNUC__
|
||||
CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID);
|
||||
#elif defined (__ICCARM__)
|
||||
mfcp(XREG_CP15_CACHE_SIZE_ID, CsidReg);
|
||||
#else
|
||||
{ volatile register unsigned int Reg __asm(XREG_CP15_CACHE_SIZE_ID);
|
||||
CsidReg = Reg; }
|
||||
|
|
@ -733,6 +796,9 @@ void Xil_L1DCacheInvalidate(void)
|
|||
/* Invalidate by Set/Way */
|
||||
__asm__ __volatile__("mcr " \
|
||||
XREG_CP15_INVAL_DC_LINE_SW :: "r" (C7Reg));
|
||||
#elif defined (__ICCARM__)
|
||||
__asm volatile ("mcr " \
|
||||
XREG_CP15_INVAL_DC_LINE_SW :: "r" (C7Reg));
|
||||
#else
|
||||
//mtcp(XREG_CP15_INVAL_DC_LINE_SW, C7Reg);
|
||||
{ volatile register unsigned int Reg
|
||||
|
|
@ -813,6 +879,9 @@ void Xil_L1DCacheInvalidateRange(unsigned int adr, unsigned len)
|
|||
#ifdef __GNUC__
|
||||
__asm__ __volatile__("mcr " \
|
||||
XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (adr));
|
||||
#elif defined (__ICCARM__)
|
||||
__asm volatile ("mcr " \
|
||||
XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (adr));
|
||||
#else
|
||||
{ volatile register unsigned int Reg
|
||||
__asm(XREG_CP15_INVAL_DC_LINE_MVA_POC);
|
||||
|
|
@ -854,6 +923,8 @@ void Xil_L1DCacheFlush(void)
|
|||
|
||||
#ifdef __GNUC__
|
||||
CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID);
|
||||
#elif defined (__ICCARM__)
|
||||
mfcp(XREG_CP15_CACHE_SIZE_ID, CsidReg);
|
||||
#else
|
||||
{ volatile register unsigned int Reg __asm(XREG_CP15_CACHE_SIZE_ID);
|
||||
CsidReg = Reg; }
|
||||
|
|
@ -886,6 +957,9 @@ void Xil_L1DCacheFlush(void)
|
|||
#ifdef __GNUC__
|
||||
__asm__ __volatile__("mcr " \
|
||||
XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (C7Reg));
|
||||
#elif defined (__ICCARM__)
|
||||
__asm volatile ("mcr " \
|
||||
XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (C7Reg));
|
||||
#else
|
||||
{ volatile register unsigned int Reg
|
||||
__asm(XREG_CP15_CLEAN_INVAL_DC_LINE_SW);
|
||||
|
|
@ -964,6 +1038,9 @@ void Xil_L1DCacheFlushRange(unsigned int adr, unsigned len)
|
|||
#ifdef __GNUC__
|
||||
__asm__ __volatile__("mcr " \
|
||||
XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (adr));
|
||||
#elif defined (__ICCARM__)
|
||||
__asm volatile ("mcr " \
|
||||
XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (adr));
|
||||
#else
|
||||
{ volatile register unsigned int Reg
|
||||
__asm(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC);
|
||||
|
|
@ -1020,6 +1097,8 @@ void Xil_L1ICacheEnable(void)
|
|||
/* enable caches only if they are disabled */
|
||||
#ifdef __GNUC__
|
||||
CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
|
||||
#elif defined (__ICCARM__)
|
||||
mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
|
||||
#else
|
||||
{ volatile register unsigned int Reg __asm(XREG_CP15_SYS_CONTROL);
|
||||
CtrlReg = Reg; }
|
||||
|
|
@ -1060,6 +1139,8 @@ void Xil_L1ICacheDisable(void)
|
|||
/* disable the instruction cache */
|
||||
#ifdef __GNUC__
|
||||
CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
|
||||
#elif defined (__ICCARM__)
|
||||
mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
|
||||
#else
|
||||
{ volatile register unsigned int Reg __asm(XREG_CP15_SYS_CONTROL);
|
||||
CtrlReg = Reg; }
|
||||
|
|
@ -1151,6 +1232,9 @@ void Xil_L1ICacheInvalidateRange(unsigned int adr, unsigned len)
|
|||
#ifdef __GNUC__
|
||||
__asm__ __volatile__("mcr " \
|
||||
XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (adr));
|
||||
#elif defined (__ICCARM__)
|
||||
__asm volatile ("mcr " \
|
||||
XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (adr));
|
||||
#else
|
||||
{ volatile register unsigned int Reg
|
||||
__asm(XREG_CP15_INVAL_IC_LINE_MVA_POU);
|
||||
|
|
|
|||
|
|
@ -106,6 +106,11 @@ typedef void (*Xil_InterruptHandler)(void *data);
|
|||
#ifdef __GNUC__
|
||||
#define Xil_ExceptionEnableMask(Mask) \
|
||||
mtcpsr(mfcpsr() & ~ (Mask & XIL_EXCEPTION_ALL))
|
||||
#elif defined (__ICCARM__)
|
||||
#define Xil_ExceptionEnableMask(Mask) \
|
||||
{ register unsigned int rval; \
|
||||
mfcpsr(rval); \
|
||||
mtcpsr(rval & ~ (Mask & XIL_EXCEPTION_ALL)) ;}
|
||||
#else
|
||||
#define Xil_ExceptionEnableMask(Mask) \
|
||||
{ register unsigned int Reg __asm("cpsr"); \
|
||||
|
|
@ -139,6 +144,11 @@ typedef void (*Xil_InterruptHandler)(void *data);
|
|||
#ifdef __GNUC__
|
||||
#define Xil_ExceptionDisableMask(Mask) \
|
||||
mtcpsr(mfcpsr() | (Mask & XIL_EXCEPTION_ALL))
|
||||
#elif defined (__ICCARM__)
|
||||
#define Xil_ExceptionDisableMask(Mask) \
|
||||
{ register unsigned int rval; \
|
||||
mfcpsr(rval); \
|
||||
mtcpsr(rval | (Mask & XIL_EXCEPTION_ALL)) ;}
|
||||
#else
|
||||
#define Xil_ExceptionDisableMask(Mask) \
|
||||
{ register unsigned int Reg __asm("cpsr"); \
|
||||
|
|
|
|||
|
|
@ -132,6 +132,8 @@ void Xil_EnableMMU(void)
|
|||
|
||||
#ifdef __GNUC__
|
||||
Reg = mfcp(XREG_CP15_SYS_CONTROL);
|
||||
#elif defined (__ICCARM__)
|
||||
mfcp(XREG_CP15_SYS_CONTROL, Reg);
|
||||
#else
|
||||
{ volatile register unsigned int Cp15Reg __asm(XREG_CP15_SYS_CONTROL);
|
||||
Reg = Cp15Reg; }
|
||||
|
|
@ -164,6 +166,8 @@ void Xil_DisableMMU(void)
|
|||
|
||||
#ifdef __GNUC__
|
||||
Reg = mfcp(XREG_CP15_SYS_CONTROL);
|
||||
#elif defined (__ICCARM__)
|
||||
mfcp(XREG_CP15_SYS_CONTROL, Reg);
|
||||
#else
|
||||
{ volatile register unsigned int Cp15Reg __asm(XREG_CP15_SYS_CONTROL);
|
||||
Reg = Cp15Reg; }
|
||||
|
|
|
|||
|
|
@ -215,6 +215,8 @@ void Xpm_ResetEventCounters(void)
|
|||
|
||||
#ifdef __GNUC__
|
||||
Reg = mfcp(XREG_CP15_PERF_MONITOR_CTRL);
|
||||
#elif defined (__ICCARM__)
|
||||
mfcp(XREG_CP15_PERF_MONITOR_CTRL, Reg);
|
||||
#else
|
||||
{ register unsigned int C15Reg __asm(XREG_CP15_PERF_MONITOR_CTRL);
|
||||
Reg = C15Reg; }
|
||||
|
|
@ -283,6 +285,8 @@ void Xpm_GetEventCounters(u32 *PmCtrValue)
|
|||
mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter);
|
||||
#ifdef __GNUC__
|
||||
PmCtrValue[Counter] = mfcp(XREG_CP15_PERF_MONITOR_COUNT);
|
||||
#elif defined (__ICCARM__)
|
||||
mfcp(XREG_CP15_PERF_MONITOR_COUNT, PmCtrValue[Counter]);
|
||||
#else
|
||||
{ register unsigned int Cp15Reg __asm(XREG_CP15_PERF_MONITOR_COUNT);
|
||||
PmCtrValue[Counter] = Cp15Reg; }
|
||||
|
|
|
|||
|
|
@ -49,6 +49,8 @@
|
|||
#include "xreg_cortexa9.h"
|
||||
#ifdef __GNUC__
|
||||
#include "xpseudo_asm_gcc.h"
|
||||
#elif defined (__ICCARM__)
|
||||
#include "xpseudo_asm_iccarm.h"
|
||||
#else
|
||||
#include "xpseudo_asm_rvct.h"
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -132,7 +132,7 @@ extern "C" {
|
|||
|
||||
|
||||
/* CP15 defines */
|
||||
#if defined (__GNUC__)
|
||||
#if defined (__GNUC__) || defined (__ICCARM__)
|
||||
/* C0 Register defines */
|
||||
#define XREG_CP15_MAIN_ID "p15, 0, %0, c0, c0, 0"
|
||||
#define XREG_CP15_CACHE_TYPE "p15, 0, %0, c0, c0, 1"
|
||||
|
|
@ -226,7 +226,7 @@ extern "C" {
|
|||
#define XREG_CP15_CONTROL_A_BIT 0x00000002
|
||||
#define XREG_CP15_CONTROL_M_BIT 0x00000001
|
||||
|
||||
#if defined (__GNUC__)
|
||||
#if defined (__GNUC__) || defined (__ICCARM__)
|
||||
/* C2 Register Defines */
|
||||
#define XREG_CP15_TTBR0 "p15, 0, %0, c2, c0, 0"
|
||||
#define XREG_CP15_TTBR1 "p15, 0, %0, c2, c0, 1"
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue