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qspipsu_v1_1: Modified the code according to MISRAC.

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This patch modifies QSPIPSU source code according to
MISRAC-2012.

Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
This commit is contained in:
P L Sai Krishna 2015-04-28 12:16:27 +05:30 • committed by Nava kishore Manne
parent 380e426371
commit 6fcd63974f
6 changed files with 594 additions and 547 deletions
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433
XilinxProcessorIPLib/drivers/qspipsu_v1_1/src/xqspipsu.c
View file

@ -47,6 +47,7 @@
* hk 03/18/15 Switch to I/O mode before clearing RX FIFO.
* Clear and disbale DMA interrupts/status in abort.
* Use DMA DONE bit instead of BUSY as recommended.
* 1.1 sk 04/24/15 Modified the code according to MISRAC-2012.
*
* </pre>
*
@ -64,20 +65,20 @@
/************************** Function Prototypes ******************************/
static void StubStatusHandler(void *CallBackRef, u32 StatusEvent,
unsigned ByteCount);
u32 ByteCount);
static inline u32 XQspiPsu_SelectSpiMode(u8 SpiMode);
static inline void XQspiPsu_TXRXSetup(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
u32 *GenFifoEntry);
static inline void XQspiPsu_FillTxFifo(XQspiPsu *InstancePtr,
XQspiPsu_Msg *Msg, int Size);
XQspiPsu_Msg *Msg, s32 Size);
static inline void XQspiPsu_SetupRxDma(XQspiPsu *InstancePtr,
XQspiPsu_Msg *Msg);
static inline void XQspiPsu_GenFifoEntryCSAssert(XQspiPsu *InstancePtr);
static inline int XQspiPsu_GenFifoEntryData(XQspiPsu *InstancePtr,
XQspiPsu_Msg *Msg, int Index);
static inline void XQspiPsu_GenFifoEntryData(XQspiPsu *InstancePtr,
XQspiPsu_Msg *Msg, s32 Index);
static inline void XQspiPsu_GenFifoEntryCSDeAssert(XQspiPsu *InstancePtr);
static inline void XQspiPsu_ReadRxFifo(XQspiPsu *InstancePtr,
XQspiPsu_Msg *Msg, int Size);
XQspiPsu_Msg *Msg, s32 Size);
/************************** Variable Definitions *****************************/
@ -108,11 +109,12 @@ static inline void XQspiPsu_ReadRxFifo(XQspiPsu *InstancePtr,
* @note None.
*
******************************************************************************/
int XQspiPsu_CfgInitialize(XQspiPsu *InstancePtr, XQspiPsu_Config *ConfigPtr,
s32 XQspiPsu_CfgInitialize(XQspiPsu *InstancePtr, XQspiPsu_Config *ConfigPtr,
u32 EffectiveAddr)
{
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(ConfigPtr != NULL);
s32 Status;
/*
* If the device is busy, disallow the initialize and return a status
@ -121,41 +123,44 @@ int XQspiPsu_CfgInitialize(XQspiPsu *InstancePtr, XQspiPsu_Config *ConfigPtr,
* initializing. This assumes the busy flag is cleared at startup.
*/
if (InstancePtr->IsBusy == TRUE) {
return XST_DEVICE_IS_STARTED;
Status = (s32)XST_DEVICE_IS_STARTED;
} else {
/* Set some default values. */
InstancePtr->IsBusy = FALSE;
InstancePtr->Config.BaseAddress = EffectiveAddr + XQSPIPSU_OFFSET;
InstancePtr->Config.ConnectionMode = ConfigPtr->ConnectionMode;
InstancePtr->StatusHandler = StubStatusHandler;
/* Other instance variable initializations */
InstancePtr->SendBufferPtr = NULL;
InstancePtr->RecvBufferPtr = NULL;
InstancePtr->GenFifoBufferPtr = NULL;
InstancePtr->TxBytes = 0;
InstancePtr->RxBytes = 0;
InstancePtr->GenFifoEntries = 0;
InstancePtr->ReadMode = XQSPIPSU_READMODE_DMA;
InstancePtr->GenFifoCS = XQSPIPSU_GENFIFO_CS_LOWER;
InstancePtr->GenFifoBus = XQSPIPSU_GENFIFO_BUS_LOWER;
InstancePtr->IsUnaligned = 0;
/* Select QSPIPSU */
XQspiPsu_Select(InstancePtr);
/*
* Reset the QSPIPSU device to get it into its initial state. It is
* expected that device configuration will take place after this
* initialization is done, but before the device is started.
*/
XQspiPsu_Reset(InstancePtr);
InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
Status = XST_SUCCESS;
}
/* Set some default values. */
InstancePtr->IsBusy = FALSE;
InstancePtr->Config.BaseAddress = EffectiveAddr + XQSPIPSU_OFFSET;
InstancePtr->Config.ConnectionMode = ConfigPtr->ConnectionMode;
InstancePtr->StatusHandler = StubStatusHandler;
/* Other instance variable initializations */
InstancePtr->SendBufferPtr = NULL;
InstancePtr->RecvBufferPtr = NULL;
InstancePtr->GenFifoBufferPtr = NULL;
InstancePtr->TxBytes = 0;
InstancePtr->RxBytes = 0;
InstancePtr->GenFifoEntries = 0;
InstancePtr->ReadMode = XQSPIPSU_READMODE_DMA;
InstancePtr->GenFifoCS = XQSPIPSU_GENFIFO_CS_LOWER;
InstancePtr->GenFifoBus = XQSPIPSU_GENFIFO_BUS_LOWER;
InstancePtr->IsUnaligned = 0;
/* Select QSPIPSU */
XQspiPsu_Select(InstancePtr);
/*
* Reset the QSPIPSU device to get it into its initial state. It is
* expected that device configuration will take place after this
* initialization is done, but before the device is started.
*/
XQspiPsu_Reset(InstancePtr);
InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
return XST_SUCCESS;
return Status;
}
/*****************************************************************************/
@ -199,10 +204,10 @@ void XQspiPsu_Reset(XQspiPsu *InstancePtr)
/* Set hold bit */
ConfigReg |= XQSPIPSU_CFG_WP_HOLD_MASK;
/* Clear prescalar by default */
ConfigReg &= ~XQSPIPSU_CFG_BAUD_RATE_DIV_MASK;
ConfigReg &= (u32)(~XQSPIPSU_CFG_BAUD_RATE_DIV_MASK);
/* CPOL CPHA 00 */
ConfigReg &= ~XQSPIPSU_CFG_CLK_PHA_MASK;
ConfigReg &= ~XQSPIPSU_CFG_CLK_POL_MASK;
ConfigReg &= (u32)(~XQSPIPSU_CFG_CLK_PHA_MASK);
ConfigReg &= (u32)(~XQSPIPSU_CFG_CLK_POL_MASK);
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_CFG_OFFSET, ConfigReg);
@ -272,7 +277,7 @@ void XQspiPsu_Abort(XQspiPsu *InstancePtr)
/* Clear FIFO */
if((XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_ISR_OFFSET) & XQSPIPSU_ISR_RXEMPTY_MASK)) {
XQSPIPSU_ISR_OFFSET) & XQSPIPSU_ISR_RXEMPTY_MASK) != FALSE) {
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_FIFO_CTRL_OFFSET,
XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_MASK |
@ -284,7 +289,7 @@ void XQspiPsu_Abort(XQspiPsu *InstancePtr)
* where it waits on RX empty and goes busy assuming there is data
* to be transfered even if there is no request.
*/
if ((IntrStatus & XQSPIPSU_ISR_RXEMPTY_MASK) != 0) {
if ((IntrStatus & XQSPIPSU_ISR_RXEMPTY_MASK) != 0U) {
ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_CFG_OFFSET);
ConfigReg &= ~XQSPIPSU_CFG_MODE_EN_MASK;
@ -329,27 +334,35 @@ void XQspiPsu_Abort(XQspiPsu *InstancePtr)
* @note None.
*
******************************************************************************/
int XQspiPsu_PolledTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
unsigned NumMsg)
s32 XQspiPsu_PolledTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
u32 NumMsg)
{
u32 StatusReg;
u32 ConfigReg;
int Index;
u8 IsManualStart = FALSE;
s32 Index;
u8 IsManualStart;
u32 QspiPsuStatusReg, DmaStatusReg;
u32 BaseAddress;
int Status;
u32 RxThr;
s32 Status;
s32 RxThr;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
for (Index = 0; Index < NumMsg; Index++) {
Xil_AssertNonvoid(Msg[Index].ByteCount > 0);
for (Index = 0; Index < (s32)NumMsg; Index++) {
Xil_AssertNonvoid(Msg[Index].ByteCount > 0U);
}
/* Check whether there is another transfer in progress. Not thread-safe */
if (InstancePtr->IsBusy) {
return XST_DEVICE_BUSY;
if (InstancePtr->IsBusy == TRUE) {
return (s32)XST_DEVICE_BUSY;
}
/* Check for ByteCount upper limit - 2^28 for DMA */
for (Index = 0; Index < (s32)NumMsg; Index++) {
if ((Msg[Index].ByteCount > XQSPIPSU_DMA_BYTES_MAX) &&
(Msg[Index].RxBfrPtr != NULL)) {
return (s32)XST_FAILURE;
}
}
/*
@ -370,15 +383,12 @@ int XQspiPsu_PolledTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
XQspiPsu_GenFifoEntryCSAssert(InstancePtr);
/* list */
for (Index = 0; Index < NumMsg; Index++) {
for (Index = 0; Index < (s32)NumMsg; Index++) {
GENFIFO:
Status = XQspiPsu_GenFifoEntryData(InstancePtr, Msg, Index);
if (Status != XST_SUCCESS) {
return Status;
}
XQspiPsu_GenFifoEntryData(InstancePtr, Msg, Index);
if (IsManualStart) {
if (IsManualStart == TRUE) {
XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_CFG_OFFSET,
XQspiPsu_ReadReg(BaseAddress,
XQSPIPSU_CFG_OFFSET) |
@ -392,7 +402,7 @@ GENFIFO:
XQSPIPSU_ISR_OFFSET);
/* Transmit more data if left */
if ((QspiPsuStatusReg & XQSPIPSU_ISR_TXNOT_FULL_MASK) &&
if (((QspiPsuStatusReg & XQSPIPSU_ISR_TXNOT_FULL_MASK) != FALSE) &&
(Msg[Index].TxBfrPtr != NULL) &&
(InstancePtr->TxBytes > 0)) {
XQspiPsu_FillTxFifo(InstancePtr, &Msg[Index],
@ -405,12 +415,12 @@ GENFIFO:
u32 DmaIntrSts;
DmaIntrSts = XQspiPsu_ReadReg(BaseAddress,
XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET);
if (DmaIntrSts & XQSPIPSU_QSPIDMA_DST_I_STS_DONE_MASK) {
if ((DmaIntrSts & XQSPIPSU_QSPIDMA_DST_I_STS_DONE_MASK) != FALSE) {
XQspiPsu_WriteReg(BaseAddress,
XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET,
DmaIntrSts);
/* Read remaining bytes using IO mode */
if(InstancePtr->RxBytes % 4 != 0 ) {
if((InstancePtr->RxBytes % 4) != 0 ) {
XQspiPsu_WriteReg(BaseAddress,
XQSPIPSU_CFG_OFFSET,
(XQspiPsu_ReadReg(BaseAddress,
@ -426,27 +436,31 @@ GENFIFO:
}
InstancePtr->RxBytes = 0;
}
} else if (Msg[Index].RxBfrPtr != NULL) {
/* Check if PIO RX is complete and update RxBytes */
RxThr = XQspiPsu_ReadReg(BaseAddress,
XQSPIPSU_RX_THRESHOLD_OFFSET);
if ((QspiPsuStatusReg & XQSPIPSU_ISR_RXNEMPTY_MASK)
!= 0U) {
XQspiPsu_ReadRxFifo(InstancePtr,
&Msg[Index], RxThr*4);
} else {
if (Msg[Index].RxBfrPtr != NULL) {
/* Check if PIO RX is complete and update RxBytes */
RxThr = (s32)XQspiPsu_ReadReg(BaseAddress,
XQSPIPSU_RX_THRESHOLD_OFFSET);
if ((QspiPsuStatusReg & XQSPIPSU_ISR_RXNEMPTY_MASK)
!= 0U) {
XQspiPsu_ReadRxFifo(InstancePtr,
&Msg[Index], RxThr*4);
} else if ((QspiPsuStatusReg &
XQSPIPSU_ISR_GENFIFOEMPTY_MASK) != 0U) {
XQspiPsu_ReadRxFifo(InstancePtr,
&Msg[Index], InstancePtr->RxBytes);
} else {
if ((QspiPsuStatusReg &
XQSPIPSU_ISR_GENFIFOEMPTY_MASK) != 0U) {
XQspiPsu_ReadRxFifo(InstancePtr,
&Msg[Index], InstancePtr->RxBytes);
}
}
}
}
} while (!(QspiPsuStatusReg & XQSPIPSU_ISR_GENFIFOEMPTY_MASK) ||
} while (((QspiPsuStatusReg & XQSPIPSU_ISR_GENFIFOEMPTY_MASK) == FALSE) ||
(InstancePtr->TxBytes != 0) ||
!(QspiPsuStatusReg & XQSPIPSU_ISR_TXEMPTY_MASK) ||
((QspiPsuStatusReg & XQSPIPSU_ISR_TXEMPTY_MASK) == FALSE) ||
(InstancePtr->RxBytes != 0));
if(InstancePtr->IsUnaligned) {
if(InstancePtr->IsUnaligned != 0) {
InstancePtr->IsUnaligned = 0;
XQspiPsu_WriteReg(BaseAddress,
XQSPIPSU_CFG_OFFSET, (XQspiPsu_ReadReg(
@ -460,14 +474,14 @@ GENFIFO:
/* De-select slave */
XQspiPsu_GenFifoEntryCSDeAssert(InstancePtr);
if (IsManualStart) {
if (IsManualStart == TRUE) {
XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_CFG_OFFSET,
XQspiPsu_ReadReg(BaseAddress, XQSPIPSU_CFG_OFFSET) |
XQSPIPSU_CFG_START_GEN_FIFO_MASK);
}
QspiPsuStatusReg = XQspiPsu_ReadReg(BaseAddress, XQSPIPSU_ISR_OFFSET);
while (!(QspiPsuStatusReg & XQSPIPSU_ISR_GENFIFOEMPTY_MASK)) {
while ((QspiPsuStatusReg & XQSPIPSU_ISR_GENFIFOEMPTY_MASK) == FALSE) {
QspiPsuStatusReg = XQspiPsu_ReadReg(BaseAddress,
XQSPIPSU_ISR_OFFSET);
}
@ -500,25 +514,33 @@ GENFIFO:
* @note None.
*
******************************************************************************/
int XQspiPsu_InterruptTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
unsigned NumMsg)
s32 XQspiPsu_InterruptTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
u32 NumMsg)
{
u32 StatusReg;
u32 ConfigReg;
int Index;
u8 IsManualStart = FALSE;
s32 Index;
u8 IsManualStart;
u32 BaseAddress;
int Status;
s32 Status;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
for (Index = 0; Index < NumMsg; Index++) {
Xil_AssertNonvoid(Msg[Index].ByteCount > 0);
for (Index = 0; Index < (s32)NumMsg; Index++) {
Xil_AssertNonvoid(Msg[Index].ByteCount > 0U);
}
/* Check whether there is another transfer in progress. Not thread-safe */
if (InstancePtr->IsBusy) {
return XST_DEVICE_BUSY;
if (InstancePtr->IsBusy == TRUE) {
return (s32)XST_DEVICE_BUSY;
}
/* Check for ByteCount upper limit - 2^28 for DMA */
for (Index = 0; Index < (s32)NumMsg; Index++) {
if ((Msg[Index].ByteCount > XQSPIPSU_DMA_BYTES_MAX) &&
(Msg[Index].RxBfrPtr != NULL)) {
return (s32)XST_FAILURE;
}
}
/*
@ -533,7 +555,7 @@ int XQspiPsu_InterruptTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
IsManualStart = XQspiPsu_IsManualStart(InstancePtr);
InstancePtr->Msg = Msg;
InstancePtr->NumMsg = NumMsg;
InstancePtr->NumMsg = (s32)NumMsg;
InstancePtr->MsgCnt = 0;
/* Enable */
@ -544,12 +566,9 @@ int XQspiPsu_InterruptTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
/* This might not work if not manual start */
/* Put first message in FIFO along with the above slave select */
Status = XQspiPsu_GenFifoEntryData(InstancePtr, Msg, 0);
if (Status != XST_SUCCESS) {
return Status;
}
XQspiPsu_GenFifoEntryData(InstancePtr, Msg, 0);
if (IsManualStart) {
if (IsManualStart == TRUE) {
XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_CFG_OFFSET,
XQspiPsu_ReadReg(BaseAddress, XQSPIPSU_CFG_OFFSET) |
XQSPIPSU_CFG_START_GEN_FIFO_MASK);
@ -557,9 +576,9 @@ int XQspiPsu_InterruptTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
/* Enable interrupts */
XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_IER_OFFSET,
XQSPIPSU_IER_TXNOT_FULL_MASK | XQSPIPSU_IER_TXEMPTY_MASK |
XQSPIPSU_IER_RXNEMPTY_MASK | XQSPIPSU_IER_GENFIFOEMPTY_MASK |
XQSPIPSU_IER_RXEMPTY_MASK);
(u32)XQSPIPSU_IER_TXNOT_FULL_MASK | (u32)XQSPIPSU_IER_TXEMPTY_MASK |
(u32)XQSPIPSU_IER_RXNEMPTY_MASK | (u32)XQSPIPSU_IER_GENFIFOEMPTY_MASK |
(u32)XQSPIPSU_IER_RXEMPTY_MASK);
if (InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA) {
XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_QSPIDMA_DST_I_EN_OFFSET,
@ -583,18 +602,18 @@ int XQspiPsu_InterruptTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
* @note None.
*
******************************************************************************/
int XQspiPsu_InterruptHandler(XQspiPsu *InstancePtr)
s32 XQspiPsu_InterruptHandler(XQspiPsu *InstancePtr)
{
u8 IsManualStart = FALSE;
u32 QspiPsuStatusReg, DmaIntrStatusReg;
u8 IsManualStart;
u32 QspiPsuStatusReg, DmaIntrStatusReg = 0;
u32 BaseAddress;
XQspiPsu_Msg *Msg;
u8 *RecvBuffer = InstancePtr->RecvBufferPtr;
u8 *SendBuffer = InstancePtr->SendBufferPtr;
int NumMsg;
int MsgCnt;
s32 NumMsg;
s32 MsgCnt;
u8 DeltaMsgCnt = 0;
u32 RxThr;
s32 RxThr;
Xil_AssertNonvoid(InstancePtr != NULL);
@ -616,8 +635,8 @@ int XQspiPsu_InterruptHandler(XQspiPsu *InstancePtr)
XQspiPsu_WriteReg(BaseAddress,
XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET, DmaIntrStatusReg);
}
if ((QspiPsuStatusReg & XQSPIPSU_ISR_POLL_TIME_EXPIRE_MASK) ||
(DmaIntrStatusReg & XQSPIPSU_QSPIDMA_DST_INTR_ERR_MASK)) {
if (((QspiPsuStatusReg & XQSPIPSU_ISR_POLL_TIME_EXPIRE_MASK) != FALSE) ||
((DmaIntrStatusReg & XQSPIPSU_QSPIDMA_DST_INTR_ERR_MASK) != FALSE)) {
/* Call status handler to indicate error */
InstancePtr->StatusHandler(InstancePtr->StatusRef,
XST_SPI_COMMAND_ERROR, 0);
@ -625,7 +644,7 @@ int XQspiPsu_InterruptHandler(XQspiPsu *InstancePtr)
/* Fill more data to be txed if required */
if ((MsgCnt < NumMsg) && (SendBuffer != NULL) &&
(QspiPsuStatusReg & XQSPIPSU_ISR_TXNOT_FULL_MASK) &&
((QspiPsuStatusReg & XQSPIPSU_ISR_TXNOT_FULL_MASK) != FALSE) &&
(InstancePtr->TxBytes > 0)) {
XQspiPsu_FillTxFifo(InstancePtr, &Msg[MsgCnt],
XQSPIPSU_TXD_DEPTH);
@ -636,19 +655,19 @@ int XQspiPsu_InterruptHandler(XQspiPsu *InstancePtr)
* This is to allow TX and RX together in one entry - corner case.
*/
if ((MsgCnt < NumMsg) && (SendBuffer != NULL) &&
(QspiPsuStatusReg & XQSPIPSU_ISR_TXEMPTY_MASK) &&
(QspiPsuStatusReg & XQSPIPSU_ISR_GENFIFOEMPTY_MASK) &&
((QspiPsuStatusReg & XQSPIPSU_ISR_TXEMPTY_MASK) != FALSE) &&
((QspiPsuStatusReg & XQSPIPSU_ISR_GENFIFOEMPTY_MASK) != FALSE) &&
(InstancePtr->TxBytes == 0) &&
(RecvBuffer == NULL)) {
MsgCnt += 1;
DeltaMsgCnt = 1;
DeltaMsgCnt = 1U;
}
if (InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA &&
if ((InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA) &&
(MsgCnt < NumMsg) && (RecvBuffer != NULL)) {
if ((DmaIntrStatusReg & XQSPIPSU_QSPIDMA_DST_I_STS_DONE_MASK)) {
if ((DmaIntrStatusReg & XQSPIPSU_QSPIDMA_DST_I_STS_DONE_MASK) != FALSE) {
/* Read remaining bytes using IO mode */
if(InstancePtr->RxBytes % 4 != 0 ) {
if((InstancePtr->RxBytes % 4) != 0 ) {
XQspiPsu_WriteReg(BaseAddress,
XQSPIPSU_CFG_OFFSET, (XQspiPsu_ReadReg(
BaseAddress, XQSPIPSU_CFG_OFFSET) &
@ -660,7 +679,7 @@ int XQspiPsu_InterruptHandler(XQspiPsu *InstancePtr)
InstancePtr->IsUnaligned = 1;
XQspiPsu_GenFifoEntryData(InstancePtr, Msg,
MsgCnt);
if(IsManualStart) {
if(IsManualStart == TRUE) {
XQspiPsu_WriteReg(BaseAddress,
XQSPIPSU_CFG_OFFSET,
XQspiPsu_ReadReg(BaseAddress,
@ -671,25 +690,29 @@ int XQspiPsu_InterruptHandler(XQspiPsu *InstancePtr)
else {
InstancePtr->RxBytes = 0;
MsgCnt += 1;
DeltaMsgCnt = 1;
DeltaMsgCnt = 1U;
}
}
} else if ((MsgCnt < NumMsg) && (RecvBuffer != NULL)) {
if (InstancePtr->RxBytes != 0) {
if ((QspiPsuStatusReg & XQSPIPSU_ISR_RXNEMPTY_MASK)
!= 0) {
RxThr = XQspiPsu_ReadReg(BaseAddress,
XQSPIPSU_RX_THRESHOLD_OFFSET);
XQspiPsu_ReadRxFifo(InstancePtr, &Msg[MsgCnt],
RxThr*4);
} else if ((QspiPsuStatusReg & XQSPIPSU_ISR_GENFIFOEMPTY_MASK) &&
(!(QspiPsuStatusReg & XQSPIPSU_ISR_RXEMPTY_MASK))) {
XQspiPsu_ReadRxFifo(InstancePtr, &Msg[MsgCnt],
InstancePtr->RxBytes);
}
if (InstancePtr->RxBytes == 0) {
MsgCnt += 1;
DeltaMsgCnt = 1;
} else {
if ((MsgCnt < NumMsg) && (RecvBuffer != NULL)) {
if (InstancePtr->RxBytes != 0) {
if ((QspiPsuStatusReg & XQSPIPSU_ISR_RXNEMPTY_MASK)
!= FALSE) {
RxThr = (s32)XQspiPsu_ReadReg(BaseAddress,
XQSPIPSU_RX_THRESHOLD_OFFSET);
XQspiPsu_ReadRxFifo(InstancePtr, &Msg[MsgCnt],
RxThr*4);
} else {
if (((QspiPsuStatusReg & XQSPIPSU_ISR_GENFIFOEMPTY_MASK) != FALSE) &&
((QspiPsuStatusReg & XQSPIPSU_ISR_RXEMPTY_MASK) == FALSE)) {
XQspiPsu_ReadRxFifo(InstancePtr, &Msg[MsgCnt],
InstancePtr->RxBytes);
}
}
if (InstancePtr->RxBytes == 0) {
MsgCnt += 1;
DeltaMsgCnt = 1U;
}
}
}
}
@ -700,12 +723,12 @@ int XQspiPsu_InterruptHandler(XQspiPsu *InstancePtr)
* If one of the above conditions increased MsgCnt, then
* the new message is yet to be placed in the FIFO; hence !DeltaMsgCnt.
*/
if ((MsgCnt < NumMsg) && !DeltaMsgCnt &&
if ((MsgCnt < NumMsg) && (DeltaMsgCnt == FALSE) &&
(RecvBuffer == NULL) &&
(SendBuffer == NULL) &&
(QspiPsuStatusReg & XQSPIPSU_ISR_GENFIFOEMPTY_MASK)) {
((QspiPsuStatusReg & XQSPIPSU_ISR_GENFIFOEMPTY_MASK) != FALSE)) {
MsgCnt += 1;
DeltaMsgCnt = 1;
DeltaMsgCnt = 1U;
}
InstancePtr->MsgCnt = MsgCnt;
@ -714,10 +737,10 @@ int XQspiPsu_InterruptHandler(XQspiPsu *InstancePtr)
* while tx is still not empty or rx dma is not yet done.
* MsgCnt > NumMsg indicates CS de-assert entry was also executed.
*/
if ((QspiPsuStatusReg & XQSPIPSU_ISR_GENFIFOEMPTY_MASK) &&
(DeltaMsgCnt || (MsgCnt > NumMsg))) {
if (((QspiPsuStatusReg & XQSPIPSU_ISR_GENFIFOEMPTY_MASK) != FALSE) &&
((DeltaMsgCnt != FALSE) || (MsgCnt > NumMsg))) {
if (MsgCnt < NumMsg) {
if(InstancePtr->IsUnaligned) {
if(InstancePtr->IsUnaligned != 0) {
InstancePtr->IsUnaligned = 0;
XQspiPsu_WriteReg(InstancePtr->Config.
BaseAddress, XQSPIPSU_CFG_OFFSET,
@ -729,7 +752,7 @@ int XQspiPsu_InterruptHandler(XQspiPsu *InstancePtr)
/* This might not work if not manual start */
XQspiPsu_GenFifoEntryData(InstancePtr, Msg, MsgCnt);
if (IsManualStart) {
if (IsManualStart == TRUE) {
XQspiPsu_WriteReg(BaseAddress,
XQSPIPSU_CFG_OFFSET,
XQspiPsu_ReadReg(BaseAddress,
@ -744,7 +767,7 @@ int XQspiPsu_InterruptHandler(XQspiPsu *InstancePtr)
/* De-select slave */
XQspiPsu_GenFifoEntryCSDeAssert(InstancePtr);
if (IsManualStart) {
if (IsManualStart == TRUE) {
XQspiPsu_WriteReg(BaseAddress,
XQSPIPSU_CFG_OFFSET,
XQspiPsu_ReadReg(BaseAddress,
@ -754,11 +777,11 @@ int XQspiPsu_InterruptHandler(XQspiPsu *InstancePtr)
} else {
/* Disable interrupts */
XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_IDR_OFFSET,
XQSPIPSU_IER_TXNOT_FULL_MASK |
XQSPIPSU_IER_TXEMPTY_MASK |
XQSPIPSU_IER_RXNEMPTY_MASK |
XQSPIPSU_IER_GENFIFOEMPTY_MASK |
XQSPIPSU_IER_RXEMPTY_MASK);
(u32)XQSPIPSU_IER_TXNOT_FULL_MASK |
(u32)XQSPIPSU_IER_TXEMPTY_MASK |
(u32)XQSPIPSU_IER_RXNEMPTY_MASK |
(u32)XQSPIPSU_IER_GENFIFOEMPTY_MASK |
(u32)XQSPIPSU_IER_RXEMPTY_MASK);
if (InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA) {
XQspiPsu_WriteReg(BaseAddress,
XQSPIPSU_QSPIDMA_DST_I_DIS_OFFSET,
@ -807,7 +830,7 @@ int XQspiPsu_InterruptHandler(XQspiPsu *InstancePtr)
* @param InstancePtr is a pointer to the XQspiPsu instance.
* @param CallBackRef is the upper layer callback reference passed back
* when the callback function is invoked.
* @param FuncPtr is the pointer to the callback function.
* @param FuncPointer is the pointer to the callback function.
*
* @return None.
*
@ -818,13 +841,13 @@ int XQspiPsu_InterruptHandler(XQspiPsu *InstancePtr)
*
******************************************************************************/
void XQspiPsu_SetStatusHandler(XQspiPsu *InstancePtr, void *CallBackRef,
XQspiPsu_StatusHandler FuncPtr)
XQspiPsu_StatusHandler FuncPointer)
{
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(FuncPtr != NULL);
Xil_AssertVoid(FuncPointer != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
InstancePtr->StatusHandler = FuncPtr;
InstancePtr->StatusHandler = FuncPointer;
InstancePtr->StatusRef = CallBackRef;
}
@ -845,9 +868,9 @@ void XQspiPsu_SetStatusHandler(XQspiPsu *InstancePtr, void *CallBackRef,
*
******************************************************************************/
static void StubStatusHandler(void *CallBackRef, u32 StatusEvent,
unsigned ByteCount)
u32 ByteCount)
{
(void) CallBackRef;
(void *) CallBackRef;
(void) StatusEvent;
(void) ByteCount;
@ -876,8 +899,11 @@ static inline u32 XQspiPsu_SelectSpiMode(u8 SpiMode)
Mask = XQSPIPSU_GENFIFO_MODE_QUADSPI;
break;
case XQSPIPSU_SELECT_MODE_SPI:
Mask = XQSPIPSU_GENFIFO_MODE_SPI;
break;
default:
Mask = XQSPIPSU_GENFIFO_MODE_SPI;
break;
}
return Mask;
@ -909,7 +935,7 @@ static inline void XQspiPsu_TXRXSetup(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
/* Setup data to be TXed */
*GenFifoEntry |= XQSPIPSU_GENFIFO_DATA_XFER;
*GenFifoEntry |= XQSPIPSU_GENFIFO_TX;
InstancePtr->TxBytes = Msg->ByteCount;
InstancePtr->TxBytes = (s32)Msg->ByteCount;
InstancePtr->SendBufferPtr = Msg->TxBfrPtr;
InstancePtr->RecvBufferPtr = NULL;
XQspiPsu_FillTxFifo(InstancePtr, Msg, XQSPIPSU_TXD_DEPTH);
@ -926,7 +952,7 @@ static inline void XQspiPsu_TXRXSetup(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
/* Setup RX */
*GenFifoEntry |= XQSPIPSU_GENFIFO_DATA_XFER;
*GenFifoEntry |= XQSPIPSU_GENFIFO_RX;
InstancePtr->RxBytes = Msg->ByteCount;
InstancePtr->RxBytes = (s32)Msg->ByteCount;
InstancePtr->SendBufferPtr = NULL;
InstancePtr->RecvBufferPtr = Msg->RxBfrPtr;
if (InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA) {
@ -948,8 +974,8 @@ static inline void XQspiPsu_TXRXSetup(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
if ((Msg->TxBfrPtr != NULL) && (Msg->RxBfrPtr != NULL)) {
*GenFifoEntry |= XQSPIPSU_GENFIFO_DATA_XFER;
*GenFifoEntry |= (XQSPIPSU_GENFIFO_TX | XQSPIPSU_GENFIFO_RX);
InstancePtr->TxBytes = Msg->ByteCount;
InstancePtr->RxBytes = Msg->ByteCount;
InstancePtr->TxBytes = (s32)Msg->ByteCount;
InstancePtr->RxBytes = (s32)Msg->ByteCount;
InstancePtr->SendBufferPtr = Msg->TxBfrPtr;
InstancePtr->RecvBufferPtr = Msg->RxBfrPtr;
XQspiPsu_FillTxFifo(InstancePtr, Msg, XQSPIPSU_TXD_DEPTH);
@ -976,24 +1002,25 @@ static inline void XQspiPsu_TXRXSetup(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
*
******************************************************************************/
static inline void XQspiPsu_FillTxFifo(XQspiPsu *InstancePtr,
XQspiPsu_Msg *Msg, int Size)
XQspiPsu_Msg *Msg, s32 Size)
{
int Count = 0;
s32 Count = 0;
u32 Data;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(Msg->TxBfrPtr != NULL);
while ((InstancePtr->TxBytes > 0) && (Count < Size)) {
Data = *((u32*)Msg->TxBfrPtr);
Data = *((u32*)(Msg->TxBfrPtr));
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_TXD_OFFSET, Data);
Msg->TxBfrPtr += 4;
InstancePtr->TxBytes -= 4;
Count++;
}
if (InstancePtr->TxBytes < 0)
if (InstancePtr->TxBytes < 0) {
InstancePtr->TxBytes = 0;
}
}
/*****************************************************************************/
@ -1012,22 +1039,22 @@ static inline void XQspiPsu_FillTxFifo(XQspiPsu *InstancePtr,
static inline void XQspiPsu_SetupRxDma(XQspiPsu *InstancePtr,
XQspiPsu_Msg *Msg)
{
int Remainder;
int DmaRxBytes;
s32 Remainder;
s32 DmaRxBytes;
u64 AddrTemp;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(Msg->RxBfrPtr != NULL);
AddrTemp = (u64)(INTPTR)(Msg->RxBfrPtr) &
XQSPIPSU_QSPIDMA_DST_ADDR_MASK;
AddrTemp = (u64)((INTPTR)(Msg->RxBfrPtr) &
XQSPIPSU_QSPIDMA_DST_ADDR_MASK);
/* Check for RXBfrPtr to be word aligned */
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET,
(u32)AddrTemp);
AddrTemp = AddrTemp >> 32;
if (AddrTemp & 0xFFF) {
if ((AddrTemp & 0xFFFU) != FALSE) {
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_QSPIDMA_DST_ADDR_MSB_OFFSET,
(u32)AddrTemp &
@ -1039,14 +1066,14 @@ static inline void XQspiPsu_SetupRxDma(XQspiPsu *InstancePtr,
if (Remainder != 0) {
/* This is done to make Dma bytes aligned */
DmaRxBytes = InstancePtr->RxBytes - Remainder;
Msg->ByteCount = DmaRxBytes;
Msg->ByteCount = (u32)DmaRxBytes;
}
Xil_DCacheInvalidateRange(InstancePtr->RecvBufferPtr, Msg->ByteCount);
Xil_DCacheInvalidateRange((INTPTR)InstancePtr->RecvBufferPtr, Msg->ByteCount);
/* Write no. of words to DMA DST SIZE */
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_QSPIDMA_DST_SIZE_OFFSET, DmaRxBytes);
XQSPIPSU_QSPIDMA_DST_SIZE_OFFSET, (u32)DmaRxBytes);
}
@ -1066,12 +1093,12 @@ static inline void XQspiPsu_GenFifoEntryCSAssert(XQspiPsu *InstancePtr)
{
u32 GenFifoEntry;
GenFifoEntry = 0x0;
GenFifoEntry &= ~(XQSPIPSU_GENFIFO_DATA_XFER | XQSPIPSU_GENFIFO_EXP);
GenFifoEntry &= ~XQSPIPSU_GENFIFO_MODE_MASK;
GenFifoEntry = 0x0U;
GenFifoEntry &= ~((u32)XQSPIPSU_GENFIFO_DATA_XFER | (u32)XQSPIPSU_GENFIFO_EXP);
GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_MODE_MASK);
GenFifoEntry |= XQSPIPSU_GENFIFO_MODE_SPI;
GenFifoEntry |= InstancePtr->GenFifoCS;
GenFifoEntry &= ~XQSPIPSU_GENFIFO_BUS_MASK;
GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_BUS_MASK);
GenFifoEntry |= InstancePtr->GenFifoBus;
GenFifoEntry &= ~(XQSPIPSU_GENFIFO_TX | XQSPIPSU_GENFIFO_RX |
XQSPIPSU_GENFIFO_STRIPE | XQSPIPSU_GENFIFO_POLL);
@ -1098,35 +1125,36 @@ static inline void XQspiPsu_GenFifoEntryCSAssert(XQspiPsu *InstancePtr)
* @note None.
*
******************************************************************************/
static inline int XQspiPsu_GenFifoEntryData(XQspiPsu *InstancePtr,
XQspiPsu_Msg *Msg, int Index)
static inline void XQspiPsu_GenFifoEntryData(XQspiPsu *InstancePtr,
XQspiPsu_Msg *Msg, s32 Index)
{
u32 GenFifoEntry;
u32 BaseAddress;
int TempCount;
int ImmData;
u32 TempCount;
u32 ImmData;
BaseAddress = InstancePtr->Config.BaseAddress;
GenFifoEntry = 0x0;
GenFifoEntry = 0x0U;
/* Bus width */
GenFifoEntry &= ~XQSPIPSU_GENFIFO_MODE_MASK;
GenFifoEntry |= XQspiPsu_SelectSpiMode(Msg[Index].BusWidth);
GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_MODE_MASK);
GenFifoEntry |= XQspiPsu_SelectSpiMode((u8)Msg[Index].BusWidth);
GenFifoEntry |= InstancePtr->GenFifoCS;
GenFifoEntry &= ~XQSPIPSU_GENFIFO_BUS_MASK;
GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_BUS_MASK);
GenFifoEntry |= InstancePtr->GenFifoBus;
/* Data */
if (Msg[Index].Flags & XQSPIPSU_MSG_FLAG_STRIPE)
if (((Msg[Index].Flags) & XQSPIPSU_MSG_FLAG_STRIPE) != FALSE) {
GenFifoEntry |= XQSPIPSU_GENFIFO_STRIPE;
else
} else {
GenFifoEntry &= ~XQSPIPSU_GENFIFO_STRIPE;
}
XQspiPsu_TXRXSetup(InstancePtr, &Msg[Index], &GenFifoEntry);
if (Msg[Index].ByteCount < XQSPIPSU_GENFIFO_IMM_DATA_MASK) {
GenFifoEntry &= ~XQSPIPSU_GENFIFO_IMM_DATA_MASK;
GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_IMM_DATA_MASK);
GenFifoEntry |= Msg[Index].ByteCount;
XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_GEN_FIFO_OFFSET,
GenFifoEntry);
@ -1134,17 +1162,12 @@ static inline int XQspiPsu_GenFifoEntryData(XQspiPsu *InstancePtr,
TempCount = Msg[Index].ByteCount;
u32 Exponent = 8; /* 2^8 = 256 */
/* Check for ByteCount upper limit - 2^28 for DMA */
if (TempCount > XQSPIPSU_DMA_BYTES_MAX) {
return XST_FAILURE;
}
ImmData = TempCount & 0xFF;
ImmData = TempCount & 0xFFU;
/* Exponent entries */
GenFifoEntry |= XQSPIPSU_GENFIFO_EXP;
while (TempCount != 0) {
if (TempCount & XQSPIPSU_GENFIFO_EXP_START) {
GenFifoEntry &= ~XQSPIPSU_GENFIFO_IMM_DATA_MASK;
while (TempCount != 0U) {
if ((TempCount & XQSPIPSU_GENFIFO_EXP_START) != FALSE) {
GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_IMM_DATA_MASK);
GenFifoEntry |= Exponent;
XQspiPsu_WriteReg(BaseAddress,
XQSPIPSU_GEN_FIFO_OFFSET,
@ -1155,16 +1178,14 @@ static inline int XQspiPsu_GenFifoEntryData(XQspiPsu *InstancePtr,
}
/* Immediate entry */
GenFifoEntry &= ~XQSPIPSU_GENFIFO_EXP;
if (ImmData & 0xFF) {
GenFifoEntry &= ~XQSPIPSU_GENFIFO_IMM_DATA_MASK;
GenFifoEntry |= ImmData & 0xFF;
GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_EXP);
if ((ImmData & 0xFFU) != FALSE) {
GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_IMM_DATA_MASK);
GenFifoEntry |= ImmData & 0xFFU;
XQspiPsu_WriteReg(BaseAddress,
XQSPIPSU_GEN_FIFO_OFFSET, GenFifoEntry);
}
}
return XST_SUCCESS;
}
/*****************************************************************************/
@ -1183,11 +1204,11 @@ static inline void XQspiPsu_GenFifoEntryCSDeAssert(XQspiPsu *InstancePtr)
{
u32 GenFifoEntry;
GenFifoEntry = 0x0;
GenFifoEntry &= ~(XQSPIPSU_GENFIFO_DATA_XFER | XQSPIPSU_GENFIFO_EXP);
GenFifoEntry &= ~XQSPIPSU_GENFIFO_MODE_MASK;
GenFifoEntry = 0x0U;
GenFifoEntry &= ~((u32)XQSPIPSU_GENFIFO_DATA_XFER | (u32)XQSPIPSU_GENFIFO_EXP);
GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_MODE_MASK);
GenFifoEntry |= XQSPIPSU_GENFIFO_MODE_SPI;
GenFifoEntry &= ~XQSPIPSU_GENFIFO_BUS_MASK;
GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_BUS_MASK);
GenFifoEntry |= InstancePtr->GenFifoBus;
GenFifoEntry &= ~(XQSPIPSU_GENFIFO_TX | XQSPIPSU_GENFIFO_RX |
XQSPIPSU_GENFIFO_STRIPE | XQSPIPSU_GENFIFO_POLL);
@ -1212,15 +1233,15 @@ static inline void XQspiPsu_GenFifoEntryCSDeAssert(XQspiPsu *InstancePtr)
*
******************************************************************************/
static inline void XQspiPsu_ReadRxFifo(XQspiPsu *InstancePtr,
XQspiPsu_Msg *Msg, int Size)
XQspiPsu_Msg *Msg, s32 Size)
{
int Count = 0;
s32 Count = 0;
u32 Data;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(Msg != NULL);
while (InstancePtr->RxBytes != 0 && Count < Size) {
while ((InstancePtr->RxBytes != 0) && (Count < Size)) {
Data = XQspiPsu_ReadReg(InstancePtr->
Config.BaseAddress, XQSPIPSU_RXD_OFFSET);
if (InstancePtr->RxBytes >= 4) {
@ -1231,11 +1252,11 @@ static inline void XQspiPsu_ReadRxFifo(XQspiPsu *InstancePtr,
} else {
/* Read unaligned bytes (< 4 bytes) */
while (InstancePtr->RxBytes != 0) {
*Msg->RxBfrPtr = Data;
*Msg->RxBfrPtr = (u8)Data;
InstancePtr->RxBytes--;
Msg->RxBfrPtr++;
Msg->RxBfrPtr += 1;
Count++;
Data >>= 8;
Data >>= (u32)8;
}
}
}

112
XilinxProcessorIPLib/drivers/qspipsu_v1_1/src/xqspipsu.h
View file

@ -89,12 +89,13 @@
* hk 03/18/15 Switch to I/O mode before clearing RX FIFO.
* Clear and disbale DMA interrupts/status in abort.
* Use DMA DONE bit instead of BUSY as recommended.
* 1.1 sk 04/24/15 Modified the code according to MISRAC-2012.
*
* </pre>
*
******************************************************************************/
#ifndef _XQSPIPSU_H_ /* prevent circular inclusions */
#define _XQSPIPSU_H_ /* by using protection macros */
#ifndef XQSPIPSU_H_ /* prevent circular inclusions */
#define XQSPIPSU_H_ /* by using protection macros */
#ifdef __cplusplus
extern "C" {
@ -104,6 +105,7 @@ extern "C" {
#include "xstatus.h"
#include "xqspipsu_hw.h"
#include "xil_cache.h"
/**************************** Type Definitions *******************************/
/**
@ -161,16 +163,16 @@ typedef struct {
u8 *SendBufferPtr; /**< Buffer to send (state) */
u8 *RecvBufferPtr; /**< Buffer to receive (state) */
u8 *GenFifoBufferPtr; /**< Gen FIFO entries */
int TxBytes; /**< Number of bytes to transfer (state) */
int RxBytes; /**< Number of bytes left to transfer(state) */
int GenFifoEntries; /**< Number of Gen FIFO entries remaining */
s32 TxBytes; /**< Number of bytes to transfer (state) */
s32 RxBytes; /**< Number of bytes left to transfer(state) */
s32 GenFifoEntries; /**< Number of Gen FIFO entries remaining */
u32 IsBusy; /**< A transfer is in progress (state) */
u32 ReadMode; /**< DMA or IO mode */
u32 GenFifoCS;
u32 GenFifoBus;
int NumMsg;
int MsgCnt;
int IsUnaligned;
s32 NumMsg;
s32 MsgCnt;
s32 IsUnaligned;
XQspiPsu_Msg *Msg;
XQspiPsu_StatusHandler StatusHandler;
void *StatusRef; /**< Callback reference for status handler */
@ -178,86 +180,86 @@ typedef struct {
/***************** Macros (Inline Functions) Definitions *********************/
#define XQSPIPSU_READMODE_DMA 0x0
#define XQSPIPSU_READMODE_IO 0x1
#define XQSPIPSU_READMODE_DMA 0x0U
#define XQSPIPSU_READMODE_IO 0x1U
#define XQSPIPSU_SELECT_FLASH_CS_LOWER 0x1
#define XQSPIPSU_SELECT_FLASH_CS_UPPER 0x2
#define XQSPIPSU_SELECT_FLASH_CS_BOTH 0x3
#define XQSPIPSU_SELECT_FLASH_CS_LOWER 0x1U
#define XQSPIPSU_SELECT_FLASH_CS_UPPER 0x2U
#define XQSPIPSU_SELECT_FLASH_CS_BOTH 0x3U
#define XQSPIPSU_SELECT_FLASH_BUS_LOWER 0x1
#define XQSPIPSU_SELECT_FLASH_BUS_UPPER 0x2
#define XQSPIPSU_SELECT_FLASH_BUS_BOTH 0x3
#define XQSPIPSU_SELECT_FLASH_BUS_LOWER 0x1U
#define XQSPIPSU_SELECT_FLASH_BUS_UPPER 0x2U
#define XQSPIPSU_SELECT_FLASH_BUS_BOTH 0x3U
#define XQSPIPSU_SELECT_MODE_SPI 0x1
#define XQSPIPSU_SELECT_MODE_DUALSPI 0x2
#define XQSPIPSU_SELECT_MODE_QUADSPI 0x4
#define XQSPIPSU_SELECT_MODE_SPI 0x1U
#define XQSPIPSU_SELECT_MODE_DUALSPI 0x2U
#define XQSPIPSU_SELECT_MODE_QUADSPI 0x4U
#define XQSPIPSU_GENFIFO_CS_SETUP 0x04
#define XQSPIPSU_GENFIFO_CS_HOLD 0x03
#define XQSPIPSU_GENFIFO_CS_SETUP 0x04U
#define XQSPIPSU_GENFIFO_CS_HOLD 0x03U
#define XQSPIPSU_CLK_ACTIVE_LOW_OPTION 0x2
#define XQSPIPSU_CLK_PHASE_1_OPTION 0x4
#define XQSPIPSU_MANUAL_START_OPTION 0x8
#define XQSPIPSU_CLK_ACTIVE_LOW_OPTION 0x2U
#define XQSPIPSU_CLK_PHASE_1_OPTION 0x4U
#define XQSPIPSU_MANUAL_START_OPTION 0x8U
#define XQSPIPSU_GENFIFO_EXP_START 0x100
#define XQSPIPSU_GENFIFO_EXP_START 0x100U
#define XQSPIPSU_DMA_BYTES_MAX 0x10000000
#define XQSPIPSU_DMA_BYTES_MAX 0x10000000U
#define XQSPIPSU_CLK_PRESCALE_2 0x00
#define XQSPIPSU_CLK_PRESCALE_4 0x01
#define XQSPIPSU_CLK_PRESCALE_8 0x02
#define XQSPIPSU_CLK_PRESCALE_16 0x03
#define XQSPIPSU_CLK_PRESCALE_32 0x04
#define XQSPIPSU_CLK_PRESCALE_64 0x05
#define XQSPIPSU_CLK_PRESCALE_128 0x06
#define XQSPIPSU_CLK_PRESCALE_256 0x07
#define XQSPIPSU_CR_PRESC_MAXIMUM 7
#define XQSPIPSU_CLK_PRESCALE_2 0x00U
#define XQSPIPSU_CLK_PRESCALE_4 0x01U
#define XQSPIPSU_CLK_PRESCALE_8 0x02U
#define XQSPIPSU_CLK_PRESCALE_16 0x03U
#define XQSPIPSU_CLK_PRESCALE_32 0x04U
#define XQSPIPSU_CLK_PRESCALE_64 0x05U
#define XQSPIPSU_CLK_PRESCALE_128 0x06U
#define XQSPIPSU_CLK_PRESCALE_256 0x07U
#define XQSPIPSU_CR_PRESC_MAXIMUM 7U
#define XQSPIPSU_CONNECTION_MODE_SINGLE 0
#define XQSPIPSU_CONNECTION_MODE_STACKED 1
#define XQSPIPSU_CONNECTION_MODE_PARALLEL 2
#define XQSPIPSU_CONNECTION_MODE_SINGLE 0U
#define XQSPIPSU_CONNECTION_MODE_STACKED 1U
#define XQSPIPSU_CONNECTION_MODE_PARALLEL 2U
/* Add more flags as required */
#define XQSPIPSU_MSG_FLAG_STRIPE 0x1
#define XQSPIPSU_MSG_FLAG_STRIPE 0x1U
#define XQspiPsu_Select(InstancePtr) XQspiPsu_Out32((InstancePtr->Config.BaseAddress) + XQSPIPSU_SEL_OFFSET, XQSPIPSU_SEL_MASK)
#define XQspiPsu_Select(InstancePtr) XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + XQSPIPSU_SEL_OFFSET, XQSPIPSU_SEL_MASK)
#define XQspiPsu_Enable(InstancePtr) XQspiPsu_Out32((InstancePtr->Config.BaseAddress) + XQSPIPSU_EN_OFFSET, XQSPIPSU_EN_MASK)
#define XQspiPsu_Enable(InstancePtr) XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + XQSPIPSU_EN_OFFSET, XQSPIPSU_EN_MASK)
#define XQspiPsu_Disable(InstancePtr) XQspiPsu_Out32((InstancePtr->Config.BaseAddress) + XQSPIPSU_EN_OFFSET, 0x0)
#define XQspiPsu_Disable(InstancePtr) XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + XQSPIPSU_EN_OFFSET, 0x0U)
#define XQspiPsu_IsManualStart(InstancePtr) ((XQspiPsu_GetOptions(InstancePtr) & XQSPIPSU_MANUAL_START_OPTION) ? TRUE : FALSE)
#define XQspiPsu_IsManualStart(InstancePtr) (((XQspiPsu_GetOptions(InstancePtr) & XQSPIPSU_MANUAL_START_OPTION) != FALSE) ? TRUE : FALSE)
/************************** Function Prototypes ******************************/
/* Initialization and reset */
XQspiPsu_Config *XQspiPsu_LookupConfig(u16 DeviceId);
int XQspiPsu_CfgInitialize(XQspiPsu *InstancePtr, XQspiPsu_Config *ConfigPtr,
s32 XQspiPsu_CfgInitialize(XQspiPsu *InstancePtr, XQspiPsu_Config *ConfigPtr,
u32 EffectiveAddr);
void XQspiPsu_Reset(XQspiPsu *InstancePtr);
void XQspiPsu_Abort(XQspiPsu *InstancePtr);
/* Transfer functions and handlers */
int XQspiPsu_PolledTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
unsigned NumMsg);
int XQspiPsu_InterruptTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
unsigned NumMsg);
int XQspiPsu_InterruptHandler(XQspiPsu *InstancePtr);
s32 XQspiPsu_PolledTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
u32 NumMsg);
s32 XQspiPsu_InterruptTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
u32 NumMsg);
s32 XQspiPsu_InterruptHandler(XQspiPsu *InstancePtr);
void XQspiPsu_SetStatusHandler(XQspiPsu *InstancePtr, void *CallBackRef,
XQspiPsu_StatusHandler FuncPtr);
XQspiPsu_StatusHandler FuncPointer);
/* Configuration functions */
int XQspiPsu_SetClkPrescaler(XQspiPsu *InstancePtr, u8 Prescaler);
s32 XQspiPsu_SetClkPrescaler(XQspiPsu *InstancePtr, u8 Prescaler);
void XQspiPsu_SelectFlash(XQspiPsu *InstancePtr, u8 FlashCS, u8 FlashBus);
int XQspiPsu_SetOptions(XQspiPsu *InstancePtr, u32 Options);
int XQspiPsu_ClearOptions(XQspiPsu *InstancePtr, u32 Options);
s32 XQspiPsu_SetOptions(XQspiPsu *InstancePtr, u32 Options);
s32 XQspiPsu_ClearOptions(XQspiPsu *InstancePtr, u32 Options);
u32 XQspiPsu_GetOptions(XQspiPsu *InstancePtr);
int XQspiPsu_SetReadMode(XQspiPsu *InstancePtr, u32 Mode);
s32 XQspiPsu_SetReadMode(XQspiPsu *InstancePtr, u32 Mode);
#ifdef __cplusplus
}
#endif
#endif /* _XQSPIPSU_H_ */
#endif /* XQSPIPSU_H_ */

1
XilinxProcessorIPLib/drivers/qspipsu_v1_1/src/xqspipsu_g.c
View file

@ -43,6 +43,7 @@
* Ver Who Date Changes
* ----- --- -------- -----------------------------------------------
* 1.0 hk 08/21/14 First release
* 1.1 sk 04/24/15 Modified the code according to MISRAC-2012.
* </pre>
*
******************************************************************************/

385
XilinxProcessorIPLib/drivers/qspipsu_v1_1/src/xqspipsu_hw.h
View file

@ -44,6 +44,7 @@
* ----- --- -------- -----------------------------------------------.
* 1.0 hk 08/21/14 First release
* hk 03/18/15 Add DMA status register masks required.
* 1.1 sk 04/24/15 Modified the code according to MISRAC-2012.
*
* </pre>
*
@ -67,727 +68,727 @@ extern "C" {
/**
* QSPI Base Address
*/
#define XQSPIPS_BASEADDR 0XFF0F0000
#define XQSPIPS_BASEADDR 0XFF0F0000U
/**
* GQSPI Base Address
*/
#define XQSPIPSU_BASEADDR 0xFF0F0100
#define XQSPIPSU_OFFSET 0x100
#define XQSPIPSU_BASEADDR 0xFF0F0100U
#define XQSPIPSU_OFFSET 0x100U
/**
* Register: XQSPIPS_EN_REG
*/
#define XQSPIPS_EN_REG ( ( XQSPIPS_BASEADDR ) + 0X00000014 )
#define XQSPIPS_EN_REG ( ( XQSPIPS_BASEADDR ) + 0X00000014U )
#define XQSPIPS_EN_SHIFT 0
#define XQSPIPS_EN_WIDTH 1
#define XQSPIPS_EN_MASK 0X00000001
#define XQSPIPS_EN_MASK 0X00000001U
/**
* Register: XQSPIPSU_CFG
*/
#define XQSPIPSU_CFG_OFFSET 0X00000000
#define XQSPIPSU_CFG_OFFSET 0X00000000U
#define XQSPIPSU_CFG_MODE_EN_SHIFT 30
#define XQSPIPSU_CFG_MODE_EN_WIDTH 2
#define XQSPIPSU_CFG_MODE_EN_MASK 0XC0000000
#define XQSPIPSU_CFG_MODE_EN_DMA_MASK 0X80000000
#define XQSPIPSU_CFG_MODE_EN_MASK 0XC0000000U
#define XQSPIPSU_CFG_MODE_EN_DMA_MASK 0X80000000U
#define XQSPIPSU_CFG_GEN_FIFO_START_MODE_SHIFT 29
#define XQSPIPSU_CFG_GEN_FIFO_START_MODE_WIDTH 1
#define XQSPIPSU_CFG_GEN_FIFO_START_MODE_MASK 0X20000000
#define XQSPIPSU_CFG_GEN_FIFO_START_MODE_MASK 0X20000000U
#define XQSPIPSU_CFG_START_GEN_FIFO_SHIFT 28
#define XQSPIPSU_CFG_START_GEN_FIFO_WIDTH 1
#define XQSPIPSU_CFG_START_GEN_FIFO_MASK 0X10000000
#define XQSPIPSU_CFG_START_GEN_FIFO_MASK 0X10000000U
#define XQSPIPSU_CFG_ENDIAN_SHIFT 26
#define XQSPIPSU_CFG_ENDIAN_WIDTH 1
#define XQSPIPSU_CFG_ENDIAN_MASK 0X04000000
#define XQSPIPSU_CFG_ENDIAN_MASK 0X04000000U
#define XQSPIPSU_CFG_EN_POLL_TO_SHIFT 20
#define XQSPIPSU_CFG_EN_POLL_TO_WIDTH 1
#define XQSPIPSU_CFG_EN_POLL_TO_MASK 0X00100000
#define XQSPIPSU_CFG_EN_POLL_TO_MASK 0X00100000U
#define XQSPIPSU_CFG_WP_HOLD_SHIFT 19
#define XQSPIPSU_CFG_WP_HOLD_WIDTH 1
#define XQSPIPSU_CFG_WP_HOLD_MASK 0X00080000
#define XQSPIPSU_CFG_WP_HOLD_MASK 0X00080000U
#define XQSPIPSU_CFG_BAUD_RATE_DIV_SHIFT 3
#define XQSPIPSU_CFG_BAUD_RATE_DIV_WIDTH 3
#define XQSPIPSU_CFG_BAUD_RATE_DIV_MASK 0X00000038
#define XQSPIPSU_CFG_BAUD_RATE_DIV_MASK 0X00000038U
#define XQSPIPSU_CFG_CLK_PHA_SHIFT 2
#define XQSPIPSU_CFG_CLK_PHA_WIDTH 1
#define XQSPIPSU_CFG_CLK_PHA_MASK 0X00000004
#define XQSPIPSU_CFG_CLK_PHA_MASK 0X00000004U
#define XQSPIPSU_CFG_CLK_POL_SHIFT 1
#define XQSPIPSU_CFG_CLK_POL_WIDTH 1
#define XQSPIPSU_CFG_CLK_POL_MASK 0X00000002
#define XQSPIPSU_CFG_CLK_POL_MASK 0X00000002U
/**
* Register: XQSPIPSU_ISR
*/
#define XQSPIPSU_ISR_OFFSET 0X00000004
#define XQSPIPSU_ISR_OFFSET 0X00000004U
#define XQSPIPSU_ISR_RXEMPTY_SHIFT 11
#define XQSPIPSU_ISR_RXEMPTY_WIDTH 1
#define XQSPIPSU_ISR_RXEMPTY_MASK 0X00000800
#define XQSPIPSU_ISR_RXEMPTY_MASK 0X00000800U
#define XQSPIPSU_ISR_GENFIFOFULL_SHIFT 10
#define XQSPIPSU_ISR_GENFIFOFULL_WIDTH 1
#define XQSPIPSU_ISR_GENFIFOFULL_MASK 0X00000400
#define XQSPIPSU_ISR_GENFIFOFULL_MASK 0X00000400U
#define XQSPIPSU_ISR_GENFIFONOT_FULL_SHIFT 9
#define XQSPIPSU_ISR_GENFIFONOT_FULL_WIDTH 1
#define XQSPIPSU_ISR_GENFIFONOT_FULL_MASK 0X00000200
#define XQSPIPSU_ISR_GENFIFONOT_FULL_MASK 0X00000200U
#define XQSPIPSU_ISR_TXEMPTY_SHIFT 8
#define XQSPIPSU_ISR_TXEMPTY_WIDTH 1
#define XQSPIPSU_ISR_TXEMPTY_MASK 0X00000100
#define XQSPIPSU_ISR_TXEMPTY_MASK 0X00000100U
#define XQSPIPSU_ISR_GENFIFOEMPTY_SHIFT 7
#define XQSPIPSU_ISR_GENFIFOEMPTY_WIDTH 1
#define XQSPIPSU_ISR_GENFIFOEMPTY_MASK 0X00000080
#define XQSPIPSU_ISR_GENFIFOEMPTY_MASK 0X00000080U
#define XQSPIPSU_ISR_RXFULL_SHIFT 5
#define XQSPIPSU_ISR_RXFULL_WIDTH 1
#define XQSPIPSU_ISR_RXFULL_MASK 0X00000020
#define XQSPIPSU_ISR_RXFULL_MASK 0X00000020U
#define XQSPIPSU_ISR_RXNEMPTY_SHIFT 4
#define XQSPIPSU_ISR_RXNEMPTY_WIDTH 1
#define XQSPIPSU_ISR_RXNEMPTY_MASK 0X00000010
#define XQSPIPSU_ISR_RXNEMPTY_MASK 0X00000010U
#define XQSPIPSU_ISR_TXFULL_SHIFT 3
#define XQSPIPSU_ISR_TXFULL_WIDTH 1
#define XQSPIPSU_ISR_TXFULL_MASK 0X00000008
#define XQSPIPSU_ISR_TXFULL_MASK 0X00000008U
#define XQSPIPSU_ISR_TXNOT_FULL_SHIFT 2
#define XQSPIPSU_ISR_TXNOT_FULL_WIDTH 1
#define XQSPIPSU_ISR_TXNOT_FULL_MASK 0X00000004
#define XQSPIPSU_ISR_TXNOT_FULL_MASK 0X00000004U
#define XQSPIPSU_ISR_POLL_TIME_EXPIRE_SHIFT 1
#define XQSPIPSU_ISR_POLL_TIME_EXPIRE_WIDTH 1
#define XQSPIPSU_ISR_POLL_TIME_EXPIRE_MASK 0X00000002
#define XQSPIPSU_ISR_POLL_TIME_EXPIRE_MASK 0X00000002U
#define XQSPIPSU_ISR_WR_TO_CLR_MASK 0X00000002
#define XQSPIPSU_ISR_WR_TO_CLR_MASK 0X00000002U
/**
* Register: XQSPIPSU_IER
*/
#define XQSPIPSU_IER_OFFSET 0X00000008
#define XQSPIPSU_IER_OFFSET 0X00000008U
#define XQSPIPSU_IER_RXEMPTY_SHIFT 11
#define XQSPIPSU_IER_RXEMPTY_WIDTH 1
#define XQSPIPSU_IER_RXEMPTY_MASK 0X00000800
#define XQSPIPSU_IER_RXEMPTY_MASK 0X00000800U
#define XQSPIPSU_IER_GENFIFOFULL_SHIFT 10
#define XQSPIPSU_IER_GENFIFOFULL_WIDTH 1
#define XQSPIPSU_IER_GENFIFOFULL_MASK 0X00000400
#define XQSPIPSU_IER_GENFIFOFULL_MASK 0X00000400U
#define XQSPIPSU_IER_GENFIFONOT_FULL_SHIFT 9
#define XQSPIPSU_IER_GENFIFONOT_FULL_WIDTH 1
#define XQSPIPSU_IER_GENFIFONOT_FULL_MASK 0X00000200
#define XQSPIPSU_IER_GENFIFONOT_FULL_MASK 0X00000200U
#define XQSPIPSU_IER_TXEMPTY_SHIFT 8
#define XQSPIPSU_IER_TXEMPTY_WIDTH 1
#define XQSPIPSU_IER_TXEMPTY_MASK 0X00000100
#define XQSPIPSU_IER_TXEMPTY_MASK 0X00000100U
#define XQSPIPSU_IER_GENFIFOEMPTY_SHIFT 7
#define XQSPIPSU_IER_GENFIFOEMPTY_WIDTH 1
#define XQSPIPSU_IER_GENFIFOEMPTY_MASK 0X00000080
#define XQSPIPSU_IER_GENFIFOEMPTY_MASK 0X00000080U
#define XQSPIPSU_IER_RXFULL_SHIFT 5
#define XQSPIPSU_IER_RXFULL_WIDTH 1
#define XQSPIPSU_IER_RXFULL_MASK 0X00000020
#define XQSPIPSU_IER_RXFULL_MASK 0X00000020U
#define XQSPIPSU_IER_RXNEMPTY_SHIFT 4
#define XQSPIPSU_IER_RXNEMPTY_WIDTH 1
#define XQSPIPSU_IER_RXNEMPTY_MASK 0X00000010
#define XQSPIPSU_IER_RXNEMPTY_MASK 0X00000010U
#define XQSPIPSU_IER_TXFULL_SHIFT 3
#define XQSPIPSU_IER_TXFULL_WIDTH 1
#define XQSPIPSU_IER_TXFULL_MASK 0X00000008
#define XQSPIPSU_IER_TXFULL_MASK 0X00000008U
#define XQSPIPSU_IER_TXNOT_FULL_SHIFT 2
#define XQSPIPSU_IER_TXNOT_FULL_WIDTH 1
#define XQSPIPSU_IER_TXNOT_FULL_MASK 0X00000004
#define XQSPIPSU_IER_TXNOT_FULL_MASK 0X00000004U
#define XQSPIPSU_IER_POLL_TIME_EXPIRE_SHIFT 1
#define XQSPIPSU_IER_POLL_TIME_EXPIRE_WIDTH 1
#define XQSPIPSU_IER_POLL_TIME_EXPIRE_MASK 0X00000002
#define XQSPIPSU_IER_POLL_TIME_EXPIRE_MASK 0X00000002U
/**
* Register: XQSPIPSU_IDR
*/
#define XQSPIPSU_IDR_OFFSET 0X0000000C
#define XQSPIPSU_IDR_OFFSET 0X0000000CU
#define XQSPIPSU_IDR_RXEMPTY_SHIFT 11
#define XQSPIPSU_IDR_RXEMPTY_WIDTH 1
#define XQSPIPSU_IDR_RXEMPTY_MASK 0X00000800
#define XQSPIPSU_IDR_RXEMPTY_MASK 0X00000800U
#define XQSPIPSU_IDR_GENFIFOFULL_SHIFT 10
#define XQSPIPSU_IDR_GENFIFOFULL_WIDTH 1
#define XQSPIPSU_IDR_GENFIFOFULL_MASK 0X00000400
#define XQSPIPSU_IDR_GENFIFOFULL_MASK 0X00000400U
#define XQSPIPSU_IDR_GENFIFONOT_FULL_SHIFT 9
#define XQSPIPSU_IDR_GENFIFONOT_FULL_WIDTH 1
#define XQSPIPSU_IDR_GENFIFONOT_FULL_MASK 0X00000200
#define XQSPIPSU_IDR_GENFIFONOT_FULL_MASK 0X00000200U
#define XQSPIPSU_IDR_TXEMPTY_SHIFT 8
#define XQSPIPSU_IDR_TXEMPTY_WIDTH 1
#define XQSPIPSU_IDR_TXEMPTY_MASK 0X00000100
#define XQSPIPSU_IDR_TXEMPTY_MASK 0X00000100U
#define XQSPIPSU_IDR_GENFIFOEMPTY_SHIFT 7
#define XQSPIPSU_IDR_GENFIFOEMPTY_WIDTH 1
#define XQSPIPSU_IDR_GENFIFOEMPTY_MASK 0X00000080
#define XQSPIPSU_IDR_GENFIFOEMPTY_MASK 0X00000080U
#define XQSPIPSU_IDR_RXFULL_SHIFT 5
#define XQSPIPSU_IDR_RXFULL_WIDTH 1
#define XQSPIPSU_IDR_RXFULL_MASK 0X00000020
#define XQSPIPSU_IDR_RXFULL_MASK 0X00000020U
#define XQSPIPSU_IDR_RXNEMPTY_SHIFT 4
#define XQSPIPSU_IDR_RXNEMPTY_WIDTH 1
#define XQSPIPSU_IDR_RXNEMPTY_MASK 0X00000010
#define XQSPIPSU_IDR_RXNEMPTY_MASK 0X00000010U
#define XQSPIPSU_IDR_TXFULL_SHIFT 3
#define XQSPIPSU_IDR_TXFULL_WIDTH 1
#define XQSPIPSU_IDR_TXFULL_MASK 0X00000008
#define XQSPIPSU_IDR_TXFULL_MASK 0X00000008U
#define XQSPIPSU_IDR_TXNOT_FULL_SHIFT 2
#define XQSPIPSU_IDR_TXNOT_FULL_WIDTH 1
#define XQSPIPSU_IDR_TXNOT_FULL_MASK 0X00000004
#define XQSPIPSU_IDR_TXNOT_FULL_MASK 0X00000004U
#define XQSPIPSU_IDR_POLL_TIME_EXPIRE_SHIFT 1
#define XQSPIPSU_IDR_POLL_TIME_EXPIRE_WIDTH 1
#define XQSPIPSU_IDR_POLL_TIME_EXPIRE_MASK 0X00000002
#define XQSPIPSU_IDR_POLL_TIME_EXPIRE_MASK 0X00000002U
#define XQSPIPSU_IDR_ALL_MASK 0X0FBE
#define XQSPIPSU_IDR_ALL_MASK 0X0FBEU
/**
* Register: XQSPIPSU_IMR
*/
#define XQSPIPSU_IMR_OFFSET 0X00000010
#define XQSPIPSU_IMR_OFFSET 0X00000010U
#define XQSPIPSU_IMR_RXEMPTY_SHIFT 11
#define XQSPIPSU_IMR_RXEMPTY_WIDTH 1
#define XQSPIPSU_IMR_RXEMPTY_MASK 0X00000800
#define XQSPIPSU_IMR_RXEMPTY_MASK 0X00000800U
#define XQSPIPSU_IMR_GENFIFOFULL_SHIFT 10
#define XQSPIPSU_IMR_GENFIFOFULL_WIDTH 1
#define XQSPIPSU_IMR_GENFIFOFULL_MASK 0X00000400
#define XQSPIPSU_IMR_GENFIFOFULL_MASK 0X00000400U
#define XQSPIPSU_IMR_GENFIFONOT_FULL_SHIFT 9
#define XQSPIPSU_IMR_GENFIFONOT_FULL_WIDTH 1
#define XQSPIPSU_IMR_GENFIFONOT_FULL_MASK 0X00000200
#define XQSPIPSU_IMR_GENFIFONOT_FULL_MASK 0X00000200U
#define XQSPIPSU_IMR_TXEMPTY_SHIFT 8
#define XQSPIPSU_IMR_TXEMPTY_WIDTH 1
#define XQSPIPSU_IMR_TXEMPTY_MASK 0X00000100
#define XQSPIPSU_IMR_TXEMPTY_MASK 0X00000100U
#define XQSPIPSU_IMR_GENFIFOEMPTY_SHIFT 7
#define XQSPIPSU_IMR_GENFIFOEMPTY_WIDTH 1
#define XQSPIPSU_IMR_GENFIFOEMPTY_MASK 0X00000080
#define XQSPIPSU_IMR_GENFIFOEMPTY_MASK 0X00000080U
#define XQSPIPSU_IMR_RXFULL_SHIFT 5
#define XQSPIPSU_IMR_RXFULL_WIDTH 1
#define XQSPIPSU_IMR_RXFULL_MASK 0X00000020
#define XQSPIPSU_IMR_RXFULL_MASK 0X00000020U
#define XQSPIPSU_IMR_RXNEMPTY_SHIFT 4
#define XQSPIPSU_IMR_RXNEMPTY_WIDTH 1
#define XQSPIPSU_IMR_RXNEMPTY_MASK 0X00000010
#define XQSPIPSU_IMR_RXNEMPTY_MASK 0X00000010U
#define XQSPIPSU_IMR_TXFULL_SHIFT 3
#define XQSPIPSU_IMR_TXFULL_WIDTH 1
#define XQSPIPSU_IMR_TXFULL_MASK 0X00000008
#define XQSPIPSU_IMR_TXFULL_MASK 0X00000008U
#define XQSPIPSU_IMR_TXNOT_FULL_SHIFT 2
#define XQSPIPSU_IMR_TXNOT_FULL_WIDTH 1
#define XQSPIPSU_IMR_TXNOT_FULL_MASK 0X00000004
#define XQSPIPSU_IMR_TXNOT_FULL_MASK 0X00000004U
#define XQSPIPSU_IMR_POLL_TIME_EXPIRE_SHIFT 1
#define XQSPIPSU_IMR_POLL_TIME_EXPIRE_WIDTH 1
#define XQSPIPSU_IMR_POLL_TIME_EXPIRE_MASK 0X00000002
#define XQSPIPSU_IMR_POLL_TIME_EXPIRE_MASK 0X00000002U
/**
* Register: XQSPIPSU_EN_REG
*/
#define XQSPIPSU_EN_OFFSET 0X00000014
#define XQSPIPSU_EN_OFFSET 0X00000014U
#define XQSPIPSU_EN_SHIFT 0
#define XQSPIPSU_EN_WIDTH 1
#define XQSPIPSU_EN_MASK 0X00000001
#define XQSPIPSU_EN_MASK 0X00000001U
/**
* Register: XQSPIPSU_TXD
*/
#define XQSPIPSU_TXD_OFFSET 0X0000001C
#define XQSPIPSU_TXD_OFFSET 0X0000001CU
#define XQSPIPSU_TXD_SHIFT 0
#define XQSPIPSU_TXD_WIDTH 32
#define XQSPIPSU_TXD_MASK 0XFFFFFFFF
#define XQSPIPSU_TXD_MASK 0XFFFFFFFFU
#define XQSPIPSU_TXD_DEPTH 64
/**
* Register: XQSPIPSU_RXD
*/
#define XQSPIPSU_RXD_OFFSET 0X00000020
#define XQSPIPSU_RXD_OFFSET 0X00000020U
#define XQSPIPSU_RXD_SHIFT 0
#define XQSPIPSU_RXD_WIDTH 32
#define XQSPIPSU_RXD_MASK 0XFFFFFFFF
#define XQSPIPSU_RXD_MASK 0XFFFFFFFFU
/**
* Register: XQSPIPSU_TX_THRESHOLD
*/
#define XQSPIPSU_TX_THRESHOLD_OFFSET 0X00000028
#define XQSPIPSU_TX_THRESHOLD_OFFSET 0X00000028U
#define XQSPIPSU_TX_FIFO_THRESHOLD_SHIFT 0
#define XQSPIPSU_TX_FIFO_THRESHOLD_WIDTH 6
#define XQSPIPSU_TX_FIFO_THRESHOLD_MASK 0X0000003F
#define XQSPIPSU_TX_FIFO_THRESHOLD_RESET_VAL 0X01
#define XQSPIPSU_TX_FIFO_THRESHOLD_MASK 0X0000003FU
#define XQSPIPSU_TX_FIFO_THRESHOLD_RESET_VAL 0X01U
/**
* Register: XQSPIPSU_RX_THRESHOLD
*/
#define XQSPIPSU_RX_THRESHOLD_OFFSET 0X0000002C
#define XQSPIPSU_RX_THRESHOLD_OFFSET 0X0000002CU
#define XQSPIPSU_RX_FIFO_THRESHOLD_SHIFT 0
#define XQSPIPSU_RX_FIFO_THRESHOLD_WIDTH 6
#define XQSPIPSU_RX_FIFO_THRESHOLD_MASK 0X0000003F
#define XQSPIPSU_RX_FIFO_THRESHOLD_RESET_VAL 0X01
#define XQSPIPSU_RX_FIFO_THRESHOLD_MASK 0X0000003FU
#define XQSPIPSU_RX_FIFO_THRESHOLD_RESET_VAL 0X01U
#define XQSPIPSU_RXFIFO_THRESHOLD_OPT 32
#define XQSPIPSU_RXFIFO_THRESHOLD_OPT 32U
/**
* Register: XQSPIPSU_GPIO
*/
#define XQSPIPSU_GPIO_OFFSET 0X00000030
#define XQSPIPSU_GPIO_OFFSET 0X00000030U
#define XQSPIPSU_GPIO_WP_N_SHIFT 0
#define XQSPIPSU_GPIO_WP_N_WIDTH 1
#define XQSPIPSU_GPIO_WP_N_MASK 0X00000001
#define XQSPIPSU_GPIO_WP_N_MASK 0X00000001U
/**
* Register: XQSPIPSU_LPBK_DLY_ADJ
*/
#define XQSPIPSU_LPBK_DLY_ADJ_OFFSET 0X00000038
#define XQSPIPSU_LPBK_DLY_ADJ_OFFSET 0X00000038U
#define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_SHIFT 5
#define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_WIDTH 1
#define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_MASK 0X00000020
#define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_MASK 0X00000020U
#define XQSPIPSU_LPBK_DLY_ADJ_DLY1_SHIFT 3
#define XQSPIPSU_LPBK_DLY_ADJ_DLY1_WIDTH 2
#define XQSPIPSU_LPBK_DLY_ADJ_DLY1_MASK 0X00000018
#define XQSPIPSU_LPBK_DLY_ADJ_DLY1_MASK 0X00000018U
#define XQSPIPSU_LPBK_DLY_ADJ_DLY0_SHIFT 0
#define XQSPIPSU_LPBK_DLY_ADJ_DLY0_WIDTH 3
#define XQSPIPSU_LPBK_DLY_ADJ_DLY0_MASK 0X00000007
#define XQSPIPSU_LPBK_DLY_ADJ_DLY0_MASK 0X00000007U
/**
* Register: XQSPIPSU_GEN_FIFO
*/
#define XQSPIPSU_GEN_FIFO_OFFSET 0X00000040
#define XQSPIPSU_GEN_FIFO_OFFSET 0X00000040U
#define XQSPIPSU_GEN_FIFO_DATA_SHIFT 0
#define XQSPIPSU_GEN_FIFO_DATA_WIDTH 20
#define XQSPIPSU_GEN_FIFO_DATA_MASK 0X000FFFFF
#define XQSPIPSU_GEN_FIFO_DATA_MASK 0X000FFFFFU
/**
* Register: XQSPIPSU_SEL
*/
#define XQSPIPSU_SEL_OFFSET 0X00000044
#define XQSPIPSU_SEL_OFFSET 0X00000044U
#define XQSPIPSU_SEL_SHIFT 0
#define XQSPIPSU_SEL_WIDTH 1
#define XQSPIPSU_SEL_MASK 0X00000001
#define XQSPIPSU_SEL_MASK 0X00000001U
/**
* Register: XQSPIPSU_FIFO_CTRL
*/
#define XQSPIPSU_FIFO_CTRL_OFFSET 0X0000004C
#define XQSPIPSU_FIFO_CTRL_OFFSET 0X0000004CU
#define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_SHIFT 2
#define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_WIDTH 1
#define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_MASK 0X00000004
#define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_MASK 0X00000004U
#define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_SHIFT 1
#define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_WIDTH 1
#define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_MASK 0X00000002
#define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_MASK 0X00000002U
#define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_SHIFT 0
#define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_WIDTH 1
#define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_MASK 0X00000001
#define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_MASK 0X00000001U
/**
* Register: XQSPIPSU_GF_THRESHOLD
*/
#define XQSPIPSU_GF_THRESHOLD_OFFSET 0X00000050
#define XQSPIPSU_GF_THRESHOLD_OFFSET 0X00000050U
#define XQSPIPSU_GEN_FIFO_THRESHOLD_SHIFT 0
#define XQSPIPSU_GEN_FIFO_THRESHOLD_WIDTH 5
#define XQSPIPSU_GEN_FIFO_THRESHOLD_MASK 0X0000001F
#define XQSPIPSU_GEN_FIFO_THRESHOLD_RESET_VAL 0X10
#define XQSPIPSU_GEN_FIFO_THRESHOLD_RESET_VAL 0X10U
/**
* Register: XQSPIPSU_POLL_CFG
*/
#define XQSPIPSU_POLL_CFG_OFFSET 0X00000054
#define XQSPIPSU_POLL_CFG_OFFSET 0X00000054U
#define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_SHIFT 31
#define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_WIDTH 1
#define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_MASK 0X80000000
#define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_MASK 0X80000000U
#define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_SHIFT 30
#define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_WIDTH 1
#define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_MASK 0X40000000
#define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_MASK 0X40000000U
#define XQSPIPSU_POLL_CFG_MASK_EN_SHIFT 8
#define XQSPIPSU_POLL_CFG_MASK_EN_WIDTH 8
#define XQSPIPSU_POLL_CFG_MASK_EN_MASK 0X0000FF00
#define XQSPIPSU_POLL_CFG_MASK_EN_MASK 0X0000FF00U
#define XQSPIPSU_POLL_CFG_DATA_VALUE_SHIFT 0
#define XQSPIPSU_POLL_CFG_DATA_VALUE_WIDTH 8
#define XQSPIPSU_POLL_CFG_DATA_VALUE_MASK 0X000000FF
#define XQSPIPSU_POLL_CFG_DATA_VALUE_MASK 0X000000FFU
/**
* Register: XQSPIPSU_P_TIMEOUT
*/
#define XQSPIPSU_P_TO_OFFSET 0X00000058
#define XQSPIPSU_P_TO_OFFSET 0X00000058U
#define XQSPIPSU_P_TO_VALUE_SHIFT 0
#define XQSPIPSU_P_TO_VALUE_WIDTH 32
#define XQSPIPSU_P_TO_VALUE_MASK 0XFFFFFFFF
#define XQSPIPSU_P_TO_VALUE_MASK 0XFFFFFFFFU
/**
* Register: XQSPIPSU_XFER_STS
*/
#define XQSPIPSU_XFER_STS_OFFSET 0X0000005C
#define XQSPIPSU_XFER_STS_OFFSET 0X0000005CU
#define XQSPIPSU_XFER_STS_PEND_BYTES_SHIFT 0
#define XQSPIPSU_XFER_STS_PEND_BYTES_WIDTH 32
#define XQSPIPSU_XFER_STS_PEND_BYTES_MASK 0XFFFFFFFF
#define XQSPIPSU_XFER_STS_PEND_BYTES_MASK 0XFFFFFFFFU
/**
* Register: XQSPIPSU_GF_SNAPSHOT
*/
#define XQSPIPSU_GF_SNAPSHOT_OFFSET 0X00000060
#define XQSPIPSU_GF_SNAPSHOT_OFFSET 0X00000060U
#define XQSPIPSU_GF_SNAPSHOT_SHIFT 0
#define XQSPIPSU_GF_SNAPSHOT_WIDTH 20
#define XQSPIPSU_GF_SNAPSHOT_MASK 0X000FFFFF
#define XQSPIPSU_GF_SNAPSHOT_MASK 0X000FFFFFU
/**
* Register: XQSPIPSU_RX_COPY
*/
#define XQSPIPSU_RX_COPY_OFFSET 0X00000064
#define XQSPIPSU_RX_COPY_OFFSET 0X00000064U
#define XQSPIPSU_RX_COPY_UPPER_SHIFT 8
#define XQSPIPSU_RX_COPY_UPPER_WIDTH 8
#define XQSPIPSU_RX_COPY_UPPER_MASK 0X0000FF00
#define XQSPIPSU_RX_COPY_UPPER_MASK 0X0000FF00U
#define XQSPIPSU_RX_COPY_LOWER_SHIFT 0
#define XQSPIPSU_RX_COPY_LOWER_WIDTH 8
#define XQSPIPSU_RX_COPY_LOWER_MASK 0X000000FF
#define XQSPIPSU_RX_COPY_LOWER_MASK 0X000000FFU
/**
* Register: XQSPIPSU_MOD_ID
*/
#define XQSPIPSU_MOD_ID_OFFSET 0X000000FC
#define XQSPIPSU_MOD_ID_OFFSET 0X000000FCU
#define XQSPIPSU_MOD_ID_SHIFT 0
#define XQSPIPSU_MOD_ID_WIDTH 32
#define XQSPIPSU_MOD_ID_MASK 0XFFFFFFFF
#define XQSPIPSU_MOD_ID_MASK 0XFFFFFFFFU
/**
* Register: XQSPIPSU_QSPIDMA_DST_ADDR
*/
#define XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET 0X00000700
#define XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET 0X00000700U
#define XQSPIPSU_QSPIDMA_DST_ADDR_SHIFT 2
#define XQSPIPSU_QSPIDMA_DST_ADDR_WIDTH 30
#define XQSPIPSU_QSPIDMA_DST_ADDR_MASK 0XFFFFFFFC
#define XQSPIPSU_QSPIDMA_DST_ADDR_MASK 0XFFFFFFFCU
/**
* Register: XQSPIPSU_QSPIDMA_DST_SIZE
*/
#define XQSPIPSU_QSPIDMA_DST_SIZE_OFFSET 0X00000704
#define XQSPIPSU_QSPIDMA_DST_SIZE_OFFSET 0X00000704U
#define XQSPIPSU_QSPIDMA_DST_SIZE_SHIFT 2
#define XQSPIPSU_QSPIDMA_DST_SIZE_WIDTH 27
#define XQSPIPSU_QSPIDMA_DST_SIZE_MASK 0X1FFFFFFC
#define XQSPIPSU_QSPIDMA_DST_SIZE_MASK 0X1FFFFFFCU
/**
* Register: XQSPIPSU_QSPIDMA_DST_STS
*/
#define XQSPIPSU_QSPIDMA_DST_STS_OFFSET 0X00000708
#define XQSPIPSU_QSPIDMA_DST_STS_OFFSET 0X00000708U
#define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_SHIFT 13
#define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_WIDTH 3
#define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_MASK 0X0000E000
#define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_MASK 0X0000E000U
#define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_SHIFT 5
#define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_WIDTH 8
#define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_MASK 0X00001FE0
#define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_MASK 0X00001FE0U
#define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_SHIFT 1
#define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_WIDTH 4
#define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_MASK 0X0000001E
#define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_MASK 0X0000001EU
#define XQSPIPSU_QSPIDMA_DST_STS_BUSY_SHIFT 0
#define XQSPIPSU_QSPIDMA_DST_STS_BUSY_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_STS_BUSY_MASK 0X00000001
#define XQSPIPSU_QSPIDMA_DST_STS_BUSY_MASK 0X00000001U
#define XQSPIPSU_QSPIDMA_DST_STS_WTC 0xE000
#define XQSPIPSU_QSPIDMA_DST_STS_WTC 0xE000U
/**
* Register: XQSPIPSU_QSPIDMA_DST_CTRL
*/
#define XQSPIPSU_QSPIDMA_DST_CTRL_OFFSET 0X0000070C
#define XQSPIPSU_QSPIDMA_DST_CTRL_OFFSET 0X0000070CU
#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_SHIFT 25
#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_WIDTH 7
#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_MASK 0XFE000000
#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_MASK 0XFE000000U
#define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_SHIFT 24
#define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_MASK 0X01000000
#define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_MASK 0X01000000U
#define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_SHIFT 23
#define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_MASK 0X00800000
#define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_MASK 0X00800000U
#define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_SHIFT 22
#define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_MASK 0X00400000
#define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_MASK 0X00400000U
#define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_SHIFT 10
#define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_WIDTH 12
#define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_MASK 0X003FFC00
#define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_MASK 0X003FFC00U
#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_SHIFT 2
#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_WIDTH 8
#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_MASK 0X000003FC
#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_MASK 0X000003FCU
#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_SHIFT 1
#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_MASK 0X00000002
#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_MASK 0X00000002U
#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_SHIFT 0
#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_MASK 0X00000001
#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_MASK 0X00000001U
#define XQSPIPSU_QSPIDMA_DST_CTRL_RESET_VAL 0x803FFA00
#define XQSPIPSU_QSPIDMA_DST_CTRL_RESET_VAL 0x403FFA00U
/**
* Register: XQSPIPSU_QSPIDMA_DST_I_STS
*/
#define XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET 0X00000714
#define XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET 0X00000714U
#define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_SHIFT 7
#define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_MASK 0X00000080
#define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_MASK 0X00000080U
#define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_SHIFT 6
#define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_MASK 0X00000040
#define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_MASK 0X00000040U
#define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_SHIFT 5
#define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_MASK 0X00000020
#define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_MASK 0X00000020U
#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_SHIFT 4
#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_MASK 0X00000010
#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_MASK 0X00000010U
#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_SHIFT 3
#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_MASK 0X00000008
#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_MASK 0X00000008U
#define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_SHIFT 2
#define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_MASK 0X00000004
#define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_MASK 0X00000004U
#define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_SHIFT 1
#define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_MASK 0X00000002
#define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_MASK 0X00000002U
#define XQSPIPSU_QSPIDMA_DST_INTR_ERR_MASK 0X000000FC
#define XQSPIPSU_QSPIDMA_DST_INTR_ALL_MASK 0X000000FE
#define XQSPIPSU_QSPIDMA_DST_INTR_ERR_MASK 0X000000FCU
#define XQSPIPSU_QSPIDMA_DST_INTR_ALL_MASK 0X000000FEU
/**
* Register: XQSPIPSU_QSPIDMA_DST_I_EN
*/
#define XQSPIPSU_QSPIDMA_DST_I_EN_OFFSET 0X00000718
#define XQSPIPSU_QSPIDMA_DST_I_EN_OFFSET 0X00000718U
#define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_SHIFT 7
#define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_MASK 0X00000080
#define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_MASK 0X00000080U
#define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_SHIFT 6
#define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_MASK 0X00000040
#define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_MASK 0X00000040U
#define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_SHIFT 5
#define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_MASK 0X00000020
#define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_MASK 0X00000020U
#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_SHIFT 4
#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_MASK 0X00000010
#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_MASK 0X00000010U
#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_SHIFT 3
#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_MASK 0X00000008
#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_MASK 0X00000008U
#define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_SHIFT 2
#define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_MASK 0X00000004
#define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_MASK 0X00000004U
#define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_SHIFT 1
#define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_MASK 0X00000002
#define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_MASK 0X00000002U
/**
* Register: XQSPIPSU_QSPIDMA_DST_I_DIS
*/
#define XQSPIPSU_QSPIDMA_DST_I_DIS_OFFSET 0X0000071C
#define XQSPIPSU_QSPIDMA_DST_I_DIS_OFFSET 0X0000071CU
#define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_SHIFT 7
#define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_MASK 0X00000080
#define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_MASK 0X00000080U
#define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_SHIFT 6
#define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_MASK 0X00000040
#define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_MASK 0X00000040U
#define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_SHIFT 5
#define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_MASK 0X00000020
#define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_MASK 0X00000020U
#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_SHIFT 4
#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_MASK 0X00000010
#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_MASK 0X00000010U
#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_SHIFT 3
#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_MASK 0X00000008
#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_MASK 0X00000008U
#define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_SHIFT 2
#define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_MASK 0X00000004
#define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_MASK 0X00000004U
#define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_SHIFT 1
#define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_MASK 0X00000002
#define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_MASK 0X00000002U
/**
* Register: XQSPIPSU_QSPIDMA_DST_IMR
*/
#define XQSPIPSU_QSPIDMA_DST_IMR_OFFSET 0X00000720
#define XQSPIPSU_QSPIDMA_DST_IMR_OFFSET 0X00000720U
#define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_SHIFT 7
#define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_MASK 0X00000080
#define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_MASK 0X00000080U
#define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_SHIFT 6
#define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_MASK 0X00000040
#define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_MASK 0X00000040U
#define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_SHIFT 5
#define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_MASK 0X00000020
#define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_MASK 0X00000020U
#define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_SHIFT 4
#define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_MASK 0X00000010
#define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_MASK 0X00000010U
#define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_SHIFT 3
#define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_MASK 0X00000008
#define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_MASK 0X00000008U
#define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_SHIFT 2
#define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_MASK 0X00000004
#define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_MASK 0X00000004U
#define XQSPIPSU_QSPIDMA_DST_IMR_DONE_SHIFT 1
#define XQSPIPSU_QSPIDMA_DST_IMR_DONE_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_IMR_DONE_MASK 0X00000002
#define XQSPIPSU_QSPIDMA_DST_IMR_DONE_MASK 0X00000002U
/**
* Register: XQSPIPSU_QSPIDMA_DST_CTRL2
*/
#define XQSPIPSU_QSPIDMA_DST_CTRL2_OFFSET 0X00000724
#define XQSPIPSU_QSPIDMA_DST_CTRL2_OFFSET 0X00000724U
#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_SHIFT 27
#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_MASK 0X08000000
#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_MASK 0X08000000U
#define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_SHIFT 24
#define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_WIDTH 3
#define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_MASK 0X07000000
#define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_MASK 0X07000000U
#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_SHIFT 22
#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_MASK 0X00400000
#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_MASK 0X00400000U
#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_SHIFT 19
#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_WIDTH 3
#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_MASK 0X00380000
#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_MASK 0X00380000U
#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_SHIFT 16
#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_WIDTH 3
#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_MASK 0X00070000
#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_MASK 0X00070000U
#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_SHIFT 4
#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_WIDTH 12
#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_MASK 0X0000FFF0
#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_MASK 0X0000FFF0U
#define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_SHIFT 0
#define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_WIDTH 4
#define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_MASK 0X0000000F
#define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_MASK 0X0000000FU
/**
* Register: XQSPIPSU_QSPIDMA_DST_ADDR_MSB
*/
#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_OFFSET 0X00000728
#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_OFFSET 0X00000728U
#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_SHIFT 0
#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_WIDTH 12
#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_MASK 0X00000FFF
#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_MASK 0X00000FFFU
/**
* Register: XQSPIPSU_QSPIDMA_FUTURE_ECO
*/
#define XQSPIPSU_QSPIDMA_FUTURE_ECO_OFFSET 0X00000EFC
#define XQSPIPSU_QSPIDMA_FUTURE_ECO_OFFSET 0X00000EFCU
#define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_SHIFT 0
#define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_WIDTH 32
#define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_MASK 0XFFFFFFFF
#define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_MASK 0XFFFFFFFFU
/*
* Generic FIFO masks
*/
#define XQSPIPSU_GENFIFO_IMM_DATA_MASK 0xFF
#define XQSPIPSU_GENFIFO_DATA_XFER 0x100
#define XQSPIPSU_GENFIFO_EXP 0x200
#define XQSPIPSU_GENFIFO_MODE_SPI 0x400
#define XQSPIPSU_GENFIFO_MODE_DUALSPI 0x800
#define XQSPIPSU_GENFIFO_MODE_QUADSPI 0xC00
#define XQSPIPSU_GENFIFO_MODE_MASK 0xC00 /* And with ~MASK first */
#define XQSPIPSU_GENFIFO_CS_LOWER 0x1000
#define XQSPIPSU_GENFIFO_CS_UPPER 0x2000
#define XQSPIPSU_GENFIFO_BUS_LOWER 0x4000
#define XQSPIPSU_GENFIFO_BUS_UPPER 0x8000
#define XQSPIPSU_GENFIFO_BUS_BOTH 0xC000 /* inverse is no bus */
#define XQSPIPSU_GENFIFO_BUS_MASK 0xC000 /* And with ~MASK first */
#define XQSPIPSU_GENFIFO_TX 0x10000 /* inverse is zero pump */
#define XQSPIPSU_GENFIFO_RX 0x20000 /* inverse is RX discard */
#define XQSPIPSU_GENFIFO_STRIPE 0x40000
#define XQSPIPSU_GENFIFO_POLL 0x80000
#define XQSPIPSU_GENFIFO_IMM_DATA_MASK 0xFFU
#define XQSPIPSU_GENFIFO_DATA_XFER 0x100U
#define XQSPIPSU_GENFIFO_EXP 0x200U
#define XQSPIPSU_GENFIFO_MODE_SPI 0x400U
#define XQSPIPSU_GENFIFO_MODE_DUALSPI 0x800U
#define XQSPIPSU_GENFIFO_MODE_QUADSPI 0xC00U
#define XQSPIPSU_GENFIFO_MODE_MASK 0xC00U /* And with ~MASK first */
#define XQSPIPSU_GENFIFO_CS_LOWER 0x1000U
#define XQSPIPSU_GENFIFO_CS_UPPER 0x2000U
#define XQSPIPSU_GENFIFO_BUS_LOWER 0x4000U
#define XQSPIPSU_GENFIFO_BUS_UPPER 0x8000U
#define XQSPIPSU_GENFIFO_BUS_BOTH 0xC000U /* inverse is no bus */
#define XQSPIPSU_GENFIFO_BUS_MASK 0xC000U /* And with ~MASK first */
#define XQSPIPSU_GENFIFO_TX 0x10000U /* inverse is zero pump */
#define XQSPIPSU_GENFIFO_RX 0x20000U /* inverse is RX discard */
#define XQSPIPSU_GENFIFO_STRIPE 0x40000U
#define XQSPIPSU_GENFIFO_POLL 0x80000U
/***************** Macros (Inline Functions) Definitions *********************/
@ -805,7 +806,7 @@ extern "C" {
* @return The value read from the register.
*
* @note C-Style signature:
* u32 XQspiPsu_ReadReg(u32 BaseAddress. int RegOffset)
* u32 XQspiPsu_ReadReg(u32 BaseAddress. s32 RegOffset)
*
******************************************************************************/
#define XQspiPsu_ReadReg(BaseAddress, RegOffset) XQspiPsu_In32((BaseAddress) + (RegOffset))
@ -822,7 +823,7 @@ extern "C" {
* @return None.
*
* @note C-Style signature:
* void XQspiPsu_WriteReg(u32 BaseAddress, int RegOffset,
* void XQspiPsu_WriteReg(u32 BaseAddress, s32 RegOffset,
* u32 RegisterValue)
*
******************************************************************************/

204
XilinxProcessorIPLib/drivers/qspipsu_v1_1/src/xqspipsu_options.c
View file

@ -44,6 +44,7 @@
* ----- --- -------- -----------------------------------------------
* 1.0 hk 08/21/14 First release
* sk 03/13/15 Added IO mode support.
* 1.1 sk 04/24/15 Modified the code according to MISRAC-2012.
*
* </pre>
*
@ -104,11 +105,12 @@ static OptionsMap OptionsTable[] = {
* This function is not thread-safe.
*
******************************************************************************/
int XQspiPsu_SetOptions(XQspiPsu *InstancePtr, u32 Options)
s32 XQspiPsu_SetOptions(XQspiPsu *InstancePtr, u32 Options)
{
u32 ConfigReg;
unsigned int Index;
u32 Index;
u32 QspiPsuOptions;
s32 Status;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
@ -117,32 +119,35 @@ int XQspiPsu_SetOptions(XQspiPsu *InstancePtr, u32 Options)
* Do not allow to modify the Control Register while a transfer is in
* progress. Not thread-safe.
*/
if (InstancePtr->IsBusy) {
return XST_DEVICE_BUSY;
}
if (InstancePtr->IsBusy == TRUE) {
Status = (s32)XST_DEVICE_BUSY;
} else {
ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_CFG_OFFSET);
ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_CFG_OFFSET);
/*
* Loop through the options table, turning the option on
* depending on whether the bit is set in the incoming options flag.
*/
for (Index = 0; Index < XQSPIPSU_NUM_OPTIONS; Index++) {
if (Options & OptionsTable[Index].Option) {
/* Turn it on */
ConfigReg |= OptionsTable[Index].Mask;
/*
* Loop through the options table, turning the option on
* depending on whether the bit is set in the incoming options flag.
*/
for (Index = 0U; Index < XQSPIPSU_NUM_OPTIONS; Index++) {
if ((Options & OptionsTable[Index].Option) != FALSE) {
/* Turn it on */
ConfigReg |= OptionsTable[Index].Mask;
}
}
/*
* Now write the control register. Leave it to the upper layers
* to restart the device.
*/
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET,
ConfigReg);
Status = XST_SUCCESS;
}
/*
* Now write the control register. Leave it to the upper layers
* to restart the device.
*/
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET,
ConfigReg);
return XST_SUCCESS;
return Status;
}
/*****************************************************************************/
@ -168,11 +173,12 @@ int XQspiPsu_SetOptions(XQspiPsu *InstancePtr, u32 Options)
* This function is not thread-safe.
*
******************************************************************************/
int XQspiPsu_ClearOptions(XQspiPsu *InstancePtr, u32 Options)
s32 XQspiPsu_ClearOptions(XQspiPsu *InstancePtr, u32 Options)
{
u32 ConfigReg;
unsigned int Index;
u32 Index;
u32 QspiPsuOptions;
s32 Status;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
@ -181,32 +187,35 @@ int XQspiPsu_ClearOptions(XQspiPsu *InstancePtr, u32 Options)
* Do not allow to modify the Control Register while a transfer is in
* progress. Not thread-safe.
*/
if (InstancePtr->IsBusy) {
return XST_DEVICE_BUSY;
}
if (InstancePtr->IsBusy == TRUE) {
Status = (s32)XST_DEVICE_BUSY;
} else {
ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_CFG_OFFSET);
ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_CFG_OFFSET);
/*
* Loop through the options table, turning the option on
* depending on whether the bit is set in the incoming options flag.
*/
for (Index = 0; Index < XQSPIPSU_NUM_OPTIONS; Index++) {
if (Options & OptionsTable[Index].Option) {
/* Turn it off */
ConfigReg &= ~OptionsTable[Index].Mask;
/*
* Loop through the options table, turning the option on
* depending on whether the bit is set in the incoming options flag.
*/
for (Index = 0U; Index < XQSPIPSU_NUM_OPTIONS; Index++) {
if ((Options & OptionsTable[Index].Option) != FALSE) {
/* Turn it off */
ConfigReg &= ~OptionsTable[Index].Mask;
}
}
/*
* Now write the control register. Leave it to the upper layers
* to restart the device.
*/
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET,
ConfigReg);
Status = XST_SUCCESS;
}
/*
* Now write the control register. Leave it to the upper layers
* to restart the device.
*/
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET,
ConfigReg);
return XST_SUCCESS;
return Status;
}
/*****************************************************************************/
@ -230,7 +239,7 @@ u32 XQspiPsu_GetOptions(XQspiPsu *InstancePtr)
{
u32 OptionsFlag = 0;
u32 ConfigReg;
unsigned int Index;
u32 Index;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
@ -242,8 +251,8 @@ u32 XQspiPsu_GetOptions(XQspiPsu *InstancePtr)
XQSPIPSU_CFG_OFFSET);
/* Loop through the options table to grab options */
for (Index = 0; Index < XQSPIPSU_NUM_OPTIONS; Index++) {
if (ConfigReg & OptionsTable[Index].Mask) {
for (Index = 0U; Index < XQSPIPSU_NUM_OPTIONS; Index++) {
if ((ConfigReg & OptionsTable[Index].Mask) != FALSE) {
OptionsFlag |= OptionsTable[Index].Option;
}
}
@ -268,9 +277,10 @@ u32 XQspiPsu_GetOptions(XQspiPsu *InstancePtr)
* @note None.
*
******************************************************************************/
int XQspiPsu_SetClkPrescaler(XQspiPsu *InstancePtr, u8 Prescaler)
s32 XQspiPsu_SetClkPrescaler(XQspiPsu *InstancePtr, u8 Prescaler)
{
u32 ConfigReg;
s32 Status;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
@ -280,26 +290,29 @@ int XQspiPsu_SetClkPrescaler(XQspiPsu *InstancePtr, u8 Prescaler)
* Do not allow the slave select to change while a transfer is in
* progress. Not thread-safe.
*/
if (InstancePtr->IsBusy) {
return XST_DEVICE_BUSY;
if (InstancePtr->IsBusy == TRUE) {
Status = (s32)XST_DEVICE_BUSY;
} else {
/*
* Read the configuration register, mask out the relevant bits, and set
* them with the shifted value passed into the function. Write the
* results back to the configuration register.
*/
ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_CFG_OFFSET);
ConfigReg &= (u32)(~XQSPIPSU_CFG_BAUD_RATE_DIV_MASK);
ConfigReg |= (u32) ((u32)Prescaler & (u32)XQSPIPSU_CR_PRESC_MAXIMUM) <<
XQSPIPSU_CFG_BAUD_RATE_DIV_SHIFT;
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_CFG_OFFSET, ConfigReg);
Status = XST_SUCCESS;
}
/*
* Read the configuration register, mask out the relevant bits, and set
* them with the shifted value passed into the function. Write the
* results back to the configuration register.
*/
ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_CFG_OFFSET);
ConfigReg &= ~XQSPIPSU_CFG_BAUD_RATE_DIV_MASK;
ConfigReg |= (u32) (Prescaler & XQSPIPSU_CR_PRESC_MAXIMUM) <<
XQSPIPSU_CFG_BAUD_RATE_DIV_SHIFT;
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_CFG_OFFSET, ConfigReg);
return XST_SUCCESS;
return Status;
}
/*****************************************************************************/
@ -336,29 +349,35 @@ void XQspiPsu_SelectFlash(XQspiPsu *InstancePtr, u8 FlashCS, u8 FlashBus)
/* Choose slave select line */
switch (FlashCS) {
case XQSPIPSU_SELECT_FLASH_CS_BOTH:
InstancePtr->GenFifoCS = XQSPIPSU_GENFIFO_CS_LOWER |
XQSPIPSU_GENFIFO_CS_UPPER;
InstancePtr->GenFifoCS = (u32)XQSPIPSU_GENFIFO_CS_LOWER |
(u32)XQSPIPSU_GENFIFO_CS_UPPER;
break;
case XQSPIPSU_SELECT_FLASH_CS_UPPER:
InstancePtr->GenFifoCS = XQSPIPSU_GENFIFO_CS_UPPER;
break;
case XQSPIPSU_SELECT_FLASH_CS_LOWER:
InstancePtr->GenFifoCS = XQSPIPSU_GENFIFO_CS_LOWER;
break;
default:
InstancePtr->GenFifoCS = XQSPIPSU_GENFIFO_CS_LOWER;
break;
}
/* Choose bus */
switch (FlashBus) {
case XQSPIPSU_SELECT_FLASH_BUS_BOTH:
InstancePtr->GenFifoBus = XQSPIPSU_GENFIFO_BUS_LOWER |
XQSPIPSU_GENFIFO_BUS_UPPER;
InstancePtr->GenFifoBus = (u32)XQSPIPSU_GENFIFO_BUS_LOWER |
(u32)XQSPIPSU_GENFIFO_BUS_UPPER;
break;
case XQSPIPSU_SELECT_FLASH_BUS_UPPER:
InstancePtr->GenFifoBus = XQSPIPSU_GENFIFO_BUS_UPPER;
break;
case XQSPIPSU_SELECT_FLASH_BUS_LOWER:
InstancePtr->GenFifoBus = XQSPIPSU_GENFIFO_BUS_LOWER;
break;
default:
InstancePtr->GenFifoBus = XQSPIPSU_GENFIFO_BUS_LOWER;
break;
}
}
@ -382,9 +401,10 @@ void XQspiPsu_SelectFlash(XQspiPsu *InstancePtr, u8 FlashCS, u8 FlashBus)
* This function is not thread-safe.
*
******************************************************************************/
int XQspiPsu_SetReadMode(XQspiPsu *InstancePtr, u32 Mode)
s32 XQspiPsu_SetReadMode(XQspiPsu *InstancePtr, u32 Mode)
{
u32 ConfigReg;
s32 Status;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
@ -393,24 +413,26 @@ int XQspiPsu_SetReadMode(XQspiPsu *InstancePtr, u32 Mode)
* Do not allow to modify the Control Register while a transfer is in
* progress. Not thread-safe.
*/
if (InstancePtr->IsBusy) {
return XST_DEVICE_BUSY;
}
InstancePtr->ReadMode = Mode;
ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_CFG_OFFSET);
if (Mode == XQSPIPSU_READMODE_DMA) {
ConfigReg &= ~XQSPIPSU_CFG_MODE_EN_MASK;
ConfigReg |= XQSPIPSU_CFG_MODE_EN_DMA_MASK;
if (InstancePtr->IsBusy == TRUE) {
Status = (s32)XST_DEVICE_BUSY;
} else {
ConfigReg &= ~XQSPIPSU_CFG_MODE_EN_MASK;
InstancePtr->ReadMode = Mode;
ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_CFG_OFFSET);
if (Mode == XQSPIPSU_READMODE_DMA) {
ConfigReg &= ~XQSPIPSU_CFG_MODE_EN_MASK;
ConfigReg |= XQSPIPSU_CFG_MODE_EN_DMA_MASK;
} else {
ConfigReg &= ~XQSPIPSU_CFG_MODE_EN_MASK;
}
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET,
ConfigReg);
Status = XST_SUCCESS;
}
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET,
ConfigReg);
return XST_SUCCESS;
return Status;
}

6
XilinxProcessorIPLib/drivers/qspipsu_v1_1/src/xqspipsu_sinit.c
View file

@ -63,7 +63,7 @@
/************************** Variable Definitions *****************************/
extern XQspiPsu_Config XQspiPsu_ConfigTable[];
extern XQspiPsu_Config XQspiPsu_ConfigTable[XPAR_XQSPIPSU_NUM_INSTANCES];
/*****************************************************************************/
/**
@ -85,7 +85,7 @@ extern XQspiPsu_Config XQspiPsu_ConfigTable[];
XQspiPsu_Config *XQspiPsu_LookupConfig(u16 DeviceId)
{
XQspiPsu_Config *CfgPtr = NULL;
int Index;
s32 Index;
for (Index = 0; Index < XPAR_XQSPIPSU_NUM_INSTANCES; Index++) {
if (XQspiPsu_ConfigTable[Index].DeviceId == DeviceId) {
@ -93,5 +93,5 @@ XQspiPsu_Config *XQspiPsu_LookupConfig(u16 DeviceId)
break;
}
}
return CfgPtr;
return (XQspiPsu_Config *)CfgPtr;
}