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sw_apps:zynqmp_pmufw: Syncup PMUFW App with PMUFW Git Repo

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swbeta2 commit ae6d9a98edb99ce4c51c85bce4872a9f11c7eb74

PMU Firmware is being updated to the latest code base available
in the pmufw git repo. Major changes are:
	-Error Management is enabled by default
	-PM Module bug fixes
	-Code formatting changes
	-PMU ROM handlers use ROM Table instead of
	 individual handler addresses
	-Bug fixes in scheduler
	-FW_IS_PRESENT bit is set if PM is enabled

Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
This commit is contained in:
Jyotheeswar Reddy 2015-04-12 20:24:20 -07:00 • committed by Nava kishore Manne
parent 22b06a8e40
commit 6fcdc41593
40 changed files with 2122 additions and 2027 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

114
lib/sw_apps/zynqmp_pmufw/src/lscript.ld
View file

@ -170,116 +170,4 @@ _SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
_end = .;
}
XpbrACPU0SleepHandler = 0xffd00f98;
XpbrACPU0WakeHandler = 0xffd00d4c;
XpbrACPU1SleepHandler = 0xffd00fbc;
XpbrACPU1WakeHandler = 0xffd00d70;
XpbrACPU2SleepHandler = 0xffd00fe0;
XpbrACPU2WakeHandler = 0xffd00d94;
XpbrACPU3SleepHandler = 0xffd01004;
XpbrACPU3WakeHandler = 0xffd00db8;
XpbrCsuSecureLockdownHandler = 0xffd01e60;
XpbrDapFpdWakeHandler = 0xffd01c70;
XpbrDapRpuWakeHandler = 0xffd01cd8;
XpbrDefaultWakeHandler = 0xffd036d0;
XpbrFpdGicProxyWakeHandler = 0xffd00f04;
XpbrFPIsolationReqHandler = 0xffd01518;
XpbrFPLockIsoHandler = 0xffd0156c;
XpbrGpi1Router = 0xffd038ac;
XpbrGpi2Router = 0xffd03960;
XpbrGpi3Handler = 0xffd00d30;
XpbrHwExceptionHandler = 0xffd03d6c;
XpbrHwRstReqHandler = 0xffd01be0;
XpbrIpi0Handler = 0xffd00cf4;
XpbrIsoReqRouter = 0xffd03b94;
XpbrMio0WakeHandler = 0xffd00e5c;
XpbrMio1WakeHandler = 0xffd00e78;
XpbrMio2WakeHandler = 0xffd00e94;
XpbrMio3WakeHandler = 0xffd00eb0;
XpbrMio4WakeHandler = 0xffd00ecc;
XpbrMio5WakeHandler = 0xffd00ee8;
XpbrNullInterruptHandler = 0xffd03d8c;
XpbrNullServiceHandler = 0xffd020e0;
XpbrPLIsolationReqHandler = 0xffd01534;
XpbrPLNonPCAPIsoReqHandler = 0xffd01550;
XpbrPwrDnACPU0Handler = 0xffd0158c;
XpbrPwrDnACPU1Handler = 0xffd015b0;
XpbrPwrDnACPU2Handler = 0xffd015d4;
XpbrPwrDnACPU3Handler = 0xffd015f8;
XpbrPwrDnFpdHandler = 0xffd01814;
XpbrPwrDnGpuHandler = 0xffd0184c;
XpbrPwrDnL2Bank0Handler = 0xffd01664;
XpbrPwrDnOcmBank0Handler = 0xffd0173c;
XpbrPwrDnOcmBank1Handler = 0xffd01760;
XpbrPwrDnOcmBank2Handler = 0xffd01784;
XpbrPwrDnOcmBank3Handler = 0xffd017a8;
XpbrPwrDnPldHandler = 0xffd01830;
XpbrPwrDnPp0Handler = 0xffd0161c;
XpbrPwrDnPp1Handler = 0xffd01640;
XpbrPwrDnR50Handler = 0xffd01878;
XpbrPwrDnR51Handler = 0xffd01894;
XpbrPwrDnReqRouter = 0xffd03ad4;
XpbrPwrDnRpuHandler = 0xffd01688;
XpbrPwrDnTcm0AHandler = 0xffd016ac;
XpbrPwrDnTcm0BHandler = 0xffd016d0;
XpbrPwrDnTcm1AHandler = 0xffd016f4;
XpbrPwrDnTcm1BHandler = 0xffd01718;
XpbrPwrDnUsb0Handler = 0xffd017cc;
XpbrPwrDnUsb1Handler = 0xffd017f0;
XpbrPwrUpACPU0Handler = 0xffd018b0;
XpbrPwrUpACPU1Handler = 0xffd018d4;
XpbrPwrUpACPU2Handler = 0xffd018f8;
XpbrPwrUpACPU3Handler = 0xffd0191c;
XpbrPwrUpFpdHandler = 0xffd01b38;
XpbrPwrUpL2Bank0Handler = 0xffd01988;
XpbrPwrUpOcmBank0Handler = 0xffd01a60;
XpbrPwrUpOcmBank1Handler = 0xffd01a84;
XpbrPwrUpOcmBank2Handler = 0xffd01aa8;
XpbrPwrUpOcmBank3Handler = 0xffd01acc;
XpbrPwrUpPldHandler = 0xffd01b54;
XpbrPwrUpPp0Handler = 0xffd01940;
XpbrPwrUpPp1Handler = 0xffd01964;
XpbrPwrUpReqRouter = 0xffd03a14;
XpbrPwrUpRpuHandler = 0xffd019ac;
XpbrPwrUpTcm0AHandler = 0xffd019d0;
XpbrPwrUpTcm0BHandler = 0xffd019f4;
XpbrPwrUpTcm1AHandler = 0xffd01a18;
XpbrPwrUpTcm1BHandler = 0xffd01a3c;
XpbrPwrUpUsb0Handler = 0xffd01af0;
XpbrPwrUpUsb1Handler = 0xffd01b14;
XpbrR50SleepHandler = 0xffd01028;
XpbrR50WakeHandler = 0xffd00ddc;
XpbrR51SleepHandler = 0xffd0104c;
XpbrR51WakeHandler = 0xffd00e00;
XpbrROMExceptionHandler = 0xffd03d14;
XpbrRstACPU0Handler = 0xffd01124;
XpbrRstACPU1Handler = 0xffd01158;
XpbrRstACPU2Handler = 0xffd0118c;
XpbrRstACPU3Handler = 0xffd011c0;
XpbrRstACPUxHandler = 0xffd01070;
XpbrRstApuHandler = 0xffd01d48;
XpbrRstDisplayPortHandler = 0xffd0131c;
XpbrRstFpdHandler = 0xffd014e8;
XpbrRstGem0Handler = 0xffd013b8;
XpbrRstGem1Handler = 0xffd013e4;
XpbrRstGem2Handler = 0xffd01410;
XpbrRstGem3Handler = 0xffd0143c;
XpbrRstGpuHandler = 0xffd011f4;
XpbrRstLsRpuHandler = 0xffd01dac;
XpbrRstPCIeHandler = 0xffd012b4;
XpbrRstPp0Handler = 0xffd0123c;
XpbrRstPp1Handler = 0xffd01278;
XpbrRstPsOnlyHandler = 0xffd014c0;
XpbrRstR50Handler = 0xffd01350;
XpbrRstR51Handler = 0xffd01384;
XpbrRstSataHandler = 0xffd012e8;
XpbrRstUsb0Handler = 0xffd01468;
XpbrRstUsb1Handler = 0xffd01494;
XpbrRtcAlarmHandler = 0xffd00d14;
XpbrServiceHandler = 0xffd03dfc;
XpbrServiceMode = 0xffd01b70;
XpbrSwExceptionHandler = 0xffd03d7c;
XpbrSwRstReqRouter = 0xffd03c54;
XpbrTMRFaultDetectionHandler = 0xffd00cec;
XpbrUsb0WakeHandler = 0xffd00e24;
XpbrUsb1WakeHandler = 0xffd00e40;
XpbrServHndlrTbl = 0xffd07bc8;

70
lib/sw_apps/zynqmp_pmufw/src/pm_api.c
View file

@ -1,34 +1,32 @@
/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*
* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*/
/*********************************************************************
* PM API calls definitions: api ids, arguments and functions used for
@ -91,15 +89,6 @@ static const PmApiEntry pmApiTable[] = {
}, {
.apiId = PM_REGISTER_NOTIFIER,
.argTypes = { ARG_NODE, ARG_EVENT_ID, ARG_WAKE, ARG_ENABLE }
}, {
.apiId = PM_CLOCK_REQUEST,
.argTypes = { ARG_UINT32, ARG_UINT32, ARG_UNDEF, ARG_UNDEF }
}, {
.apiId = PM_CLOCK_RELEASE,
.argTypes = { ARG_UINT32, ARG_UNDEF, ARG_UNDEF, ARG_UNDEF }
}, {
.apiId = PM_CLOCK_GET_RATE,
.argTypes = { ARG_UINT32, ARG_UNDEF, ARG_UNDEF, ARG_UNDEF }
}, {
.apiId = PM_RESET_ASSERT,
.argTypes = { ARG_UINT32, ARG_UINT32, ARG_UNDEF, ARG_UNDEF }
@ -178,7 +167,6 @@ static PmPayloadStatus PmCheckArgument(const u8 argType,
case ARG_OP_CH_TYPE:
case ARG_STATE:
case ARG_EVENT_ID:
case ARG_CLOCK:
case ARG_RESET:
case ARG_LATENCY:
case ARG_UINT32:

62
lib/sw_apps/zynqmp_pmufw/src/pm_api.h
View file

@ -1,34 +1,32 @@
/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*
* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*/
/*********************************************************************
* Definitions needed to check correctness of PM API call
@ -67,7 +65,6 @@
#define ARG_STATE 7U
#define ARG_QOS 8U
#define ARG_EVENT_ID 9U
#define ARG_CLOCK 10U
#define ARG_RESET 11U
#define ARG_LATENCY 12U
#define ARG_UINT32 13U
@ -90,7 +87,6 @@ typedef enum {
PM_PAYLOAD_ERR_STATE,
PM_PAYLOAD_ERR_QOS,
PM_PAYLOAD_ERR_EVENT_ID,
PM_PAYLOAD_ERR_CLOCK,
PM_PAYLOAD_ERR_RESET,
PM_PAYLOAD_ERR_LATENCY,
PM_PAYLOAD_ERR_WAKE,

60
lib/sw_apps/zynqmp_pmufw/src/pm_binding.c
View file

@ -1,34 +1,32 @@
/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*
* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*/
/*********************************************************************
* Implementations of the functions to be used for integrating power

60
lib/sw_apps/zynqmp_pmufw/src/pm_binding.h
View file

@ -1,34 +1,32 @@
/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*
* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*/
/*********************************************************************
* Function declarations to be used for integrating
* power management within PMU firmware.

60
lib/sw_apps/zynqmp_pmufw/src/pm_callbacks.c
View file

@ -1,34 +1,32 @@
/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*
* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*/
/*********************************************************************
* PM callbacks interface.

60
lib/sw_apps/zynqmp_pmufw/src/pm_callbacks.h
View file

@ -1,34 +1,32 @@
/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*
* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*/
/*********************************************************************
* PM callbacks interface.

60
lib/sw_apps/zynqmp_pmufw/src/pm_common.c
View file

@ -1,34 +1,32 @@
/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*
* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*/
/*********************************************************************
* Definitions of commonly used functions for debugging PMU Power

60
lib/sw_apps/zynqmp_pmufw/src/pm_common.h
View file

@ -1,34 +1,32 @@
/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*
* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*/
/*********************************************************************
* Definitions of commonly used macros and enums in PMU Power

101
lib/sw_apps/zynqmp_pmufw/src/pm_core.c
View file

@ -1,34 +1,32 @@
/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*
* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*/
/*********************************************************************
* This file contains implementation of the PM API functions, which
@ -550,38 +548,6 @@ static void PmRegisterNotifier(const PmMaster *const master, const u32 node,
event, wake, enable);
}
/**
* PmClockRequest() - Request the clock at some frequency
* @master Initiator of the request
* @clock The clock in question
* @rate Frequency to be set
*/
static void PmClockRequest(const PmMaster *const master, const u32 clock,
const u32 rate)
{
PmDbg("%s(%d, %d) not implemented\n", __func__, clock, rate);
}
/**
* PmClockRelease() - Release the clock
* @master Initiator of the request
* @clock The clock in question
*/
static void PmClockRelease(const PmMaster *const master, const u32 clock)
{
PmDbg("%s(%d) not implemented\n", __func__, clock);
}
/**
* PmGetClockRate() - Get current frequency of the clock
* @master Initiator of the request
* @clock Clock whose frequency should be returned
*/
static void PmGetClockRate(const PmMaster *const master, const u32 clock)
{
PmDbg("%s(%d) not implemented\n", __func__, clock);
}
/**
* PmResetAssert() - Request setting of reset (1 - assert, 0 - release)
* @master Initiator of the request
@ -664,15 +630,6 @@ void PmProcessApiCall(const PmMaster *const master,
case PM_REGISTER_NOTIFIER:
PmRegisterNotifier(master, pload[1], pload[2], pload[3], pload[4]);
break;
case PM_CLOCK_REQUEST:
PmClockRequest(master, pload[1], pload[2]);
break;
case PM_CLOCK_RELEASE:
PmClockRelease(master, pload[1]);
break;
case PM_CLOCK_GET_RATE:
PmGetClockRate(master, pload[1]);
break;
case PM_RESET_ASSERT:
PmResetAssert(master, pload[1], pload[2]);
break;

60
lib/sw_apps/zynqmp_pmufw/src/pm_core.h
View file

@ -1,34 +1,32 @@
/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*
* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*/
/*********************************************************************
* Contains the function to call for processing a PM API call.

65
lib/sw_apps/zynqmp_pmufw/src/pm_defs.h
View file

@ -1,34 +1,32 @@
/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*
* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*/
/*********************************************************************
* Definitions of commonly used enums that have to match definitions
@ -79,11 +77,6 @@
#define PM_SET_REQUIREMENT 15U
#define PM_SET_MAX_LATENCY 16U
#define PM_CLOCK_REQUEST 17U
#define PM_CLOCK_RELEASE 18U
#define PM_CLOCK_SET_RATE 19U
#define PM_CLOCK_GET_RATE 20U
#define PM_CLOCK_GET_RATE_INFO 21U
#define PM_RESET_ASSERT 22U
#define PM_RESET_GET_STATUS 23U
#define PM_MMIO_WRITE 24U

854
lib/sw_apps/zynqmp_pmufw/src/pm_master.c
View file

File diff suppressed because it is too large Load diff

100
lib/sw_apps/zynqmp_pmufw/src/pm_master.h
View file

@ -1,34 +1,32 @@
/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*
* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*/
/*********************************************************************
* This file contains PM master related data structures and
@ -107,9 +105,8 @@ typedef struct PmMaster PmMaster;
#define PM_MASTER_RPU_0_SLAVE_MAX 12U
/* Pm Master request info masks */
#define PM_MASTER_WAKEUP_REQ_MASK 0x40U
#define PM_MASTER_USING_SLAVE_MASK 0x80U
#define PM_MASTER_INDEX_MASK 0x3FU
#define PM_MASTER_WAKEUP_REQ_MASK 0x1U
#define PM_MASTER_USING_SLAVE_MASK 0x2U
/*********************************************************************
* Structure definitions
@ -131,11 +128,11 @@ typedef struct PmMaster PmMaster;
* state (after it goes to sleep or before it gets awake)
*/
typedef struct PmRequirement {
PmSlave* const slave;
PmMaster* const requestor;
u8 info;
u32 currReq;
u32 nextReq;
PmSlave* const slave;
PmMaster* const requestor;
u8 info;
u32 currReq;
u32 nextReq;
} PmRequirement;
/**
@ -153,14 +150,14 @@ typedef struct PmRequirement {
* used slaves)
*/
typedef struct PmMaster {
PmProc* const procs;
const u8 procsCnt;
const u32 ipiMask;
const u32 ipiTrigMask;
const u32 pmuBuffer;
const u32 buffer;
PmRequirement* const reqs;
const PmRequirementId reqsCnt;
PmProc* const procs;
const u8 procsCnt;
const u32 ipiMask;
const u32 ipiTrigMask;
const u32 pmuBuffer;
const u32 buffer;
PmRequirement* const reqs;
const PmRequirementId reqsCnt;
} PmMaster;
/*********************************************************************
@ -182,17 +179,18 @@ PmProc* PmGetProcByWfiStatus(const u32 mask);
PmProc* PmGetProcByWakeStatus(const u32 mask);
PmProc* PmGetProcByNodeId(const PmNodeId nodeId);
PmProc* PmGetProcOfThisMaster(const PmMaster* const master,
const PmNodeId nodeId);
const PmNodeId nodeId);
PmProc* PmGetProcOfOtherMaster(const PmMaster* const master,
const PmNodeId nodeId);
const PmNodeId nodeId);
PmRequirement* PmGetRequirementForSlave(const PmMaster* const master,
const PmNodeId nodeId);
const PmNodeId nodeId);
u32 PmMasterGetAwakeProcCnt(const PmMaster* const master);
/* Requirements related functions */
u32 PmRequirementSchedule(PmRequirement* const masterReq, const u32 caps);
u32 PmRequirementUpdate(PmRequirement* const masterReq, const u32 caps);
void PmRequirementUpdateScheduled(const PmMaster* const master, const bool swap);
void PmRequirementUpdateScheduled(const PmMaster* const master,
const bool swap);
void PmRequirementCancelScheduled(const PmMaster* const master);
void PmEnableAllMasterIpis(void);

60
lib/sw_apps/zynqmp_pmufw/src/pm_node.c
View file

@ -1,34 +1,32 @@
/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*
* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*/
/*********************************************************************
* Global array of all nodes, and GetbyId function

60
lib/sw_apps/zynqmp_pmufw/src/pm_node.h
View file

@ -1,34 +1,32 @@
/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*
* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*/
/*********************************************************************
* Pm Node related structures and definitions

60
lib/sw_apps/zynqmp_pmufw/src/pm_periph.c
View file

@ -1,34 +1,32 @@
/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*
* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*/
#include "pm_periph.h"
#include "pm_common.h"

60
lib/sw_apps/zynqmp_pmufw/src/pm_periph.h
View file

@ -1,34 +1,32 @@
/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*
* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*/
#ifndef PM_PERIPH_H_
#define PM_PERIPH_H_

60
lib/sw_apps/zynqmp_pmufw/src/pm_power.c
View file

@ -1,34 +1,32 @@
/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*
* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*/
/*********************************************************************
* Power nodes (power islands and power domains) related structures,

60
lib/sw_apps/zynqmp_pmufw/src/pm_power.h
View file

@ -1,34 +1,32 @@
/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*
* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*/
/*********************************************************************
* Power nodes (power islands and power domains) related structures

60
lib/sw_apps/zynqmp_pmufw/src/pm_proc.c
View file

@ -1,34 +1,32 @@
/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*
* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*/
/*********************************************************************
* Definitions of processors and finite state machine

60
lib/sw_apps/zynqmp_pmufw/src/pm_proc.h
View file

@ -1,34 +1,32 @@
/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*
* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*/
/*********************************************************************
* Contains all functions, datas and definitions needed for

60
lib/sw_apps/zynqmp_pmufw/src/pm_slave.c
View file

@ -1,34 +1,32 @@
/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*
* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*/
/*************************************************************************
* PM slave structures definitions and code for handling states of slaves.

68
lib/sw_apps/zynqmp_pmufw/src/pm_slave.h
View file

@ -1,34 +1,32 @@
/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*
* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*/
/*********************************************************************
* All functions, data and definitions needed for
@ -84,10 +82,10 @@ typedef struct PmRequirement PmRequirement;
#define FPD_GICP_PMU_IRQ_GROUP4 0x10U
/* FPD GIC Proxy irq masks */
#define FPD_GICP_USB0_WAKE_IRQ_MASK 0x400U
#define FPD_GICP_USB1_WAKE_IRQ_MASK 0x800U
#define FPD_GICP_TTC0_WAKE_IRQ_MASK 0x10U
#define FPD_GICP_SATA_WAKE_IRQ_MASK 0x20U
#define FPD_GICP_USB0_WAKE_IRQ_MASK (1 << 11)
#define FPD_GICP_USB1_WAKE_IRQ_MASK (1 << 12)
#define FPD_GICP_TTC0_WAKE_IRQ_MASK (1 << 4)
#define FPD_GICP_SATA_WAKE_IRQ_MASK (1 << 5)
/*********************************************************************
* Structure definitions

60
lib/sw_apps/zynqmp_pmufw/src/pm_sram.c
View file

@ -1,34 +1,32 @@
/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*
* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*/
/*********************************************************************
* Definitions of PM slave SRAM structures and state transitions.

60
lib/sw_apps/zynqmp_pmufw/src/pm_sram.h
View file

@ -1,34 +1,32 @@
/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*
* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*/
/*********************************************************************
* SRAM memories slaves definitions and data structures

60
lib/sw_apps/zynqmp_pmufw/src/pm_usb.c
View file

@ -1,34 +1,32 @@
/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*
* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*/
/*********************************************************************
* Definitions of PM slave USB structures and state transitions.

60
lib/sw_apps/zynqmp_pmufw/src/pm_usb.h
View file

@ -1,34 +1,32 @@
/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*
* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*/
/*********************************************************************
* USB slaves data structures

9
lib/sw_apps/zynqmp_pmufw/src/xpfw_config.h
View file

@ -40,22 +40,17 @@
/* Let the MB sleep when it is Idle in Main Loop */
#define SLEEP_WHEN_IDLE
#ifndef ZYNQMP_XPFW_VERSION
#define ZYNQMP_XPFW_VERSION "--LOCAL COPY--"
#endif
/* Directs the PMU FW to configure UART */
#define CONFIG_UART
/* Enable Power Management Module */
/* Enable Power Management and Error Management Modules */
#define ENABLE_PM
#define ENABLE_EM
/*
* Disable all other mods
* User can enable Each of the Optional Modules if required
*/
#undef ENABLE_RTC_TEST
#undef ENABLE_EM
#undef ENABLE_SCHEDULER
#endif /* XPFW_CONFIG_H_ */

5
lib/sw_apps/zynqmp_pmufw/src/xpfw_core.c
View file

@ -93,6 +93,11 @@ XStatus XPfw_CoreConfigure(void)
/* FIXME: Enable IPI0 for PM-> Do it elsewhere */
XPfw_InterruptEnable(PMU_IOMODULE_IRQ_ENABLE_IPI0_MASK);
XPfw_InterruptStart();
#ifdef ENABLE_PM /* ENABLE_PM */
/* Set the FW_IS_PRESENT bit to enable PMUFW discovery by ATF*/
XPfw_RMW32(PMU_GLOBAL_GLOBAL_CNTRL, PMU_GLOBAL_GLOBAL_CNTRL_FW_IS_PRESENT_MASK,
PMU_GLOBAL_GLOBAL_CNTRL_FW_IS_PRESENT_MASK);
#endif /* ENABLE_PM */
Status = XST_SUCCESS;
} else {
Status = XST_FAILURE;

14
lib/sw_apps/zynqmp_pmufw/src/xpfw_error_handler.c
View file

@ -81,9 +81,6 @@ void XPfw_ErrorHandlerOne(void)
/* Latch the Error Flags */
l_ErrorOneReg = XPfw_Read32(PMU_GLOBAL_ERROR_STATUS_1);
/* Clear Error Register so that new errors can trigger an Interrupt */
XPfw_Write32(PMU_GLOBAL_ERROR_STATUS_1,l_ErrorOneReg);
if( (l_ErrorOneReg & PMU_GLOBAL_ERROR_STATUS_1_DDR_ECC_MASK) != 0x00000000U) {
XPfw_ErrorEccDdr();
}
@ -121,8 +118,7 @@ void XPfw_ErrorHandlerOne(void)
XPfw_ErrorXmpu();
}
/* Clear Error Register so that new errors can trigger an Interrupt */
/* Clear Error Register */
XPfw_Write32(PMU_GLOBAL_ERROR_STATUS_1,l_ErrorOneReg);
}
@ -135,9 +131,6 @@ void XPfw_ErrorHandlerTwo(void)
/* Latch the Error Flags */
l_ErrorTwoReg = XPfw_Read32(PMU_GLOBAL_ERROR_STATUS_2);
/* Clear Error Register so that new errors can trigger an Interrupt */
XPfw_Write32(PMU_GLOBAL_ERROR_STATUS_2,l_ErrorTwoReg);
if( (l_ErrorTwoReg & PMU_GLOBAL_ERROR_STATUS_2_TO_MASK) != 0x00000000U) {
XPfw_ErrorTimeOut();
}
@ -166,9 +159,8 @@ void XPfw_ErrorHandlerTwo(void)
XPfw_ErrorCsuRom();
}
/* Clear Error Register */
XPfw_Write32(PMU_GLOBAL_ERROR_STATUS_2,l_ErrorTwoReg);
}

224
lib/sw_apps/zynqmp_pmufw/src/xpfw_events.c
View file

@ -1,5 +1,4 @@
/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
@ -27,105 +26,101 @@
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#include "xpfw_events.h"
#include "xpfw_interrupts.h"
static struct XPfw_Event_t EventTable[]={
[0U] = {.Type = (u8)0U, .RegMask = MASK32_ALL_LOW, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_MB_FAULT] = { .Type = XPFW_EV_TYPE_GPI0, .RegMask = MASK32_ALL_HIGH, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_APB_AIB_ERROR] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_APB_AIB_ERROR_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_AXI_AIB_ERROR] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_AXI_AIB_ERROR_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_ERROR_2] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_ERROR_2_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_ERROR_1] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_ERROR_1_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_ACPU_3_DBG_PWRUP] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_ACPU_3_DBG_PWRUP_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_ACPU_2_DBG_PWRUP] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_ACPU_2_DBG_PWRUP_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_ACPU_1_DBG_PWRUP] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_ACPU_1_DBG_PWRUP_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_ACPU_0_DBG_PWRUP] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_ACPU_0_DBG_PWRUP_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_FPD_WAKE_GIC_PROXY] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_FPD_WAKE_GIC_PROXY_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_MIO_WAKE_5] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_MIO_WAKE_5_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_MIO_WAKE_4] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_MIO_WAKE_4_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_MIO_WAKE_3] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_MIO_WAKE_3_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_MIO_WAKE_2] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_MIO_WAKE_2_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_MIO_WAKE_1] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_MIO_WAKE_1_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_MIO_WAKE_0] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_MIO_WAKE_0_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_DAP_RPU_WAKE] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_DAP_RPU_WAKE_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_DAP_FPD_WAKE] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_DAP_FPD_WAKE_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_USB_1_WAKE] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_USB_1_WAKE_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_USB_0_WAKE] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_USB_0_WAKE_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_R5_1_WAKE] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_R5_1_WAKE_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_R5_0_WAKE] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_R5_0_WAKE_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_ACPU_3_WAKE] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_ACPU_3_WAKE_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_ACPU_2_WAKE] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_ACPU_2_WAKE_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_ACPU_1_WAKE] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_ACPU_1_WAKE_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_ACPU_0_WAKE] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_ACPU_0_WAKE_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_VCC_INT_FP_DISCONNECT] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_VCC_INT_FP_DISCONNECT_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_VCC_INT_DISCONNECT] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_VCC_INT_DISCONNECT_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_VCC_AUX_DISCONNECT] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_VCC_AUX_DISCONNECT_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_DBG_ACPU3_RST_REQ] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_DBG_ACPU3_RST_REQ_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_DBG_ACPU2_RST_REQ] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_DBG_ACPU2_RST_REQ_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_DBG_ACPU1_RST_REQ] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_DBG_ACPU1_RST_REQ_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_DBG_ACPU0_RST_REQ] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_DBG_ACPU0_RST_REQ_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_CP_ACPU3_RST_REQ] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_CP_ACPU3_RST_REQ_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_CP_ACPU2_RST_REQ] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_CP_ACPU2_RST_REQ_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_CP_ACPU1_RST_REQ] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_CP_ACPU1_RST_REQ_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_CP_ACPU0_RST_REQ] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_CP_ACPU0_RST_REQ_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_DBG_RCPU1_RST_REQ] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_DBG_RCPU1_RST_REQ_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_DBG_RCPU0_RST_REQ] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_DBG_RCPU0_RST_REQ_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_R5_1_SLEEP] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_R5_1_SLEEP_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_R5_0_SLEEP] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_R5_0_SLEEP_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_ACPU_3_SLEEP] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_ACPU_3_SLEEP_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_ACPU_2_SLEEP] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_ACPU_2_SLEEP_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_ACPU_1_SLEEP] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_ACPU_1_SLEEP_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_ACPU_0_SLEEP] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_ACPU_0_SLEEP_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_31] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_31_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_30] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_30_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_29] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_29_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_28] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_28_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_27] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_27_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_26] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_26_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_25] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_25_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_24] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_24_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_23] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_23_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_22] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_22_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_21] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_21_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_20] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_20_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_19] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_19_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_18] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_18_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_17] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_17_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_16] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_16_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_15] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_15_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_14] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_14_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_13] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_13_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_12] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_12_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_11] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_11_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_10] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_10_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_9] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_9_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_8] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_8_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_7] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_7_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_6] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_6_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_5] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_5_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_4] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_4_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_3] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_3_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_2] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_2_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_1] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_1_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_0] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_0_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_RTC_SECONDS] = { .Type = XPFW_EV_TYPE_RTC, .RegMask = PMU_IOMODULE_IRQ_PENDING_RTC_EVERY_SECOND_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_RTC_ALARM] = { .Type = XPFW_EV_TYPE_RTC, .RegMask = PMU_IOMODULE_IRQ_PENDING_RTC_ALARM_MASK, .ModMask = MASK32_ALL_LOW }
static struct XPfw_Event_t EventTable[] = {
[0U] = {.Type = (u8)0U, .RegMask = MASK32_ALL_LOW, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_MB_FAULT] = { .Type = XPFW_EV_TYPE_GPI0, .RegMask = MASK32_ALL_HIGH, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_APB_AIB_ERROR] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_APB_AIB_ERROR_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_AXI_AIB_ERROR] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_AXI_AIB_ERROR_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_ERROR_2] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_ERROR_2_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_ERROR_1] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_ERROR_1_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_ACPU_3_DBG_PWRUP] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_ACPU_3_DBG_PWRUP_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_ACPU_2_DBG_PWRUP] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_ACPU_2_DBG_PWRUP_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_ACPU_1_DBG_PWRUP] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_ACPU_1_DBG_PWRUP_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_ACPU_0_DBG_PWRUP] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_ACPU_0_DBG_PWRUP_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_FPD_WAKE_GIC_PROXY] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_FPD_WAKE_GIC_PROXY_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_MIO_WAKE_5] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_MIO_WAKE_5_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_MIO_WAKE_4] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_MIO_WAKE_4_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_MIO_WAKE_3] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_MIO_WAKE_3_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_MIO_WAKE_2] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_MIO_WAKE_2_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_MIO_WAKE_1] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_MIO_WAKE_1_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_MIO_WAKE_0] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_MIO_WAKE_0_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_DAP_RPU_WAKE] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_DAP_RPU_WAKE_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_DAP_FPD_WAKE] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_DAP_FPD_WAKE_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_USB_1_WAKE] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_USB_1_WAKE_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_USB_0_WAKE] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_USB_0_WAKE_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_R5_1_WAKE] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_R5_1_WAKE_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_R5_0_WAKE] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_R5_0_WAKE_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_ACPU_3_WAKE] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_ACPU_3_WAKE_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_ACPU_2_WAKE] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_ACPU_2_WAKE_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_ACPU_1_WAKE] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_ACPU_1_WAKE_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_ACPU_0_WAKE] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_ACPU_0_WAKE_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_VCC_INT_FP_DISCONNECT] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_VCC_INT_FP_DISCONNECT_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_VCC_INT_DISCONNECT] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_VCC_INT_DISCONNECT_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_VCC_AUX_DISCONNECT] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_VCC_AUX_DISCONNECT_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_DBG_ACPU3_RST_REQ] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_DBG_ACPU3_RST_REQ_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_DBG_ACPU2_RST_REQ] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_DBG_ACPU2_RST_REQ_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_DBG_ACPU1_RST_REQ] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_DBG_ACPU1_RST_REQ_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_DBG_ACPU0_RST_REQ] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_DBG_ACPU0_RST_REQ_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_CP_ACPU3_RST_REQ] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_CP_ACPU3_RST_REQ_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_CP_ACPU2_RST_REQ] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_CP_ACPU2_RST_REQ_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_CP_ACPU1_RST_REQ] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_CP_ACPU1_RST_REQ_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_CP_ACPU0_RST_REQ] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_CP_ACPU0_RST_REQ_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_DBG_RCPU1_RST_REQ] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_DBG_RCPU1_RST_REQ_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_DBG_RCPU0_RST_REQ] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_DBG_RCPU0_RST_REQ_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_R5_1_SLEEP] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_R5_1_SLEEP_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_R5_0_SLEEP] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_R5_0_SLEEP_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_ACPU_3_SLEEP] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_ACPU_3_SLEEP_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_ACPU_2_SLEEP] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_ACPU_2_SLEEP_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_ACPU_1_SLEEP] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_ACPU_1_SLEEP_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_ACPU_0_SLEEP] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_ACPU_0_SLEEP_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_31] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_31_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_30] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_30_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_29] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_29_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_28] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_28_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_27] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_27_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_26] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_26_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_25] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_25_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_24] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_24_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_23] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_23_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_22] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_22_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_21] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_21_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_20] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_20_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_19] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_19_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_18] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_18_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_17] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_17_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_16] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_16_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_15] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_15_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_14] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_14_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_13] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_13_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_12] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_12_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_11] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_11_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_10] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_10_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_9] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_9_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_8] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_8_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_7] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_7_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_6] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_6_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_5] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_5_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_4] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_4_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_3] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_3_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_2] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_2_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_1] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_1_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_PL_GPI_0] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_0_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_RTC_SECONDS] = { .Type = XPFW_EV_TYPE_RTC, .RegMask = PMU_IOMODULE_IRQ_PENDING_RTC_EVERY_SECOND_MASK, .ModMask = MASK32_ALL_LOW },
[XPFW_EV_RTC_ALARM] = { .Type = XPFW_EV_TYPE_RTC, .RegMask = PMU_IOMODULE_IRQ_PENDING_RTC_ALARM_MASK, .ModMask = MASK32_ALL_LOW }
};
u32 XPfw_EventGetModMask(u32 EventId)
{
u32 Mask;
if(EventId < XPFW_EV_MAX){
if (EventId < XPFW_EV_MAX) {
Mask = EventTable[EventId].ModMask;
}
else{
} else {
Mask = 0U;
}
@ -135,10 +130,10 @@ u32 XPfw_EventGetModMask(u32 EventId)
u32 XPfw_EventGetRegMask(u32 EventId)
{
u32 Mask;
if(EventId < XPFW_EV_MAX){
if (EventId < XPFW_EV_MAX) {
Mask = EventTable[EventId].RegMask;
}
else{
} else {
Mask = MASK32_ALL_HIGH;
}
@ -149,8 +144,7 @@ static XStatus XPfw_EventEnable(u32 EventId)
{
XStatus Status;
switch(EventTable[EventId].Type){
switch (EventTable[EventId].Type) {
case XPFW_EV_TYPE_GPI0:
/* Nothing to do for GPI0. These are enabled by default */
/* Enable GPI0 bit in IRQ_ENABLE */
@ -190,12 +184,8 @@ static XStatus XPfw_EventEnable(u32 EventId)
default:
Status = XST_FAILURE;
break;
}
return Status;
}
@ -203,8 +193,7 @@ static XStatus XPfw_EventDisable(u32 EventId)
{
XStatus Status;
switch(EventTable[EventId].Type){
switch (EventTable[EventId].Type) {
case XPFW_EV_TYPE_GPI0:
/* Nothing to do for GPI0. These are enabled by default */
/* Disable GPI0 bit in IRQ_ENABLE */
@ -216,7 +205,7 @@ static XStatus XPfw_EventDisable(u32 EventId)
/* Disable the event in GPI1 ENABLE register */
XPfw_RMW32(PMU_LOCAL_GPI1_ENABLE, EventTable[EventId].RegMask, 0U);
/* Disable the GPI1 bit in IRQ ENABLE */
if(0U == XPfw_Read32(PMU_LOCAL_GPI1_ENABLE)) {
if (0U == XPfw_Read32(PMU_LOCAL_GPI1_ENABLE)) {
XPfw_InterruptDisable(PMU_IOMODULE_IRQ_ENABLE_GPI1_MASK);
}
Status = XST_SUCCESS;
@ -236,7 +225,7 @@ static XStatus XPfw_EventDisable(u32 EventId)
/* Disable the event in GPI3 ENABLE register */
XPfw_RMW32(PMU_LOCAL_GPI3_ENABLE, EventTable[EventId].RegMask, 0U);
/* Enable the GPI3 bit in IRQ ENABLE */
if(0U == XPfw_Read32(PMU_LOCAL_GPI3_ENABLE)) {
if (0U == XPfw_Read32(PMU_LOCAL_GPI3_ENABLE)) {
XPfw_InterruptDisable(PMU_IOMODULE_IRQ_ENABLE_GPI3_MASK);
}
Status = XST_SUCCESS;
@ -250,25 +239,19 @@ static XStatus XPfw_EventDisable(u32 EventId)
default:
Status = XST_FAILURE;
break;
}
return Status;
}
XStatus XPfw_EventAddOwner(u8 ModId, u32 EventId)
{
XStatus Status;
if((EventId < XPFW_EV_MAX) && (ModId < 32U)){
if ((EventId < XPFW_EV_MAX) && (ModId < 32U)) {
EventTable[EventId].ModMask = EventTable[EventId].ModMask | ((u32)1U<<ModId);
Status = XPfw_EventEnable(EventId);
}
else{
} else {
Status = XST_FAILURE;
}
@ -278,21 +261,19 @@ XStatus XPfw_EventAddOwner(u8 ModId, u32 EventId)
XStatus XPfw_EventRemoveOwner(u32 ModId, u32 EventId)
{
XStatus Status;
if((EventId < XPFW_EV_MAX) && (ModId < 32U)){
if ((EventId < XPFW_EV_MAX) && (ModId < 32U)) {
/* Update the ModMask for Event */
EventTable[EventId].ModMask = EventTable[EventId].ModMask & (~((u32)1U<<ModId));
/* Check if the Event has been de-registered by All Modules */
if(0U == EventTable[EventId].ModMask) {
if (0U == EventTable[EventId].ModMask) {
/* Disable the corresponding Event from occurring */
Status = XPfw_EventDisable(EventId);
} else {
/* We successfully completed de-registration */
Status = XST_SUCCESS;
}
}
else{
} else {
/* Failed due to Invalid EventId or Mod Id */
Status = XST_FAILURE;
}
@ -303,8 +284,10 @@ XStatus XPfw_EventRemoveOwner(u32 ModId, u32 EventId)
u32 XPfw_EventGetId(u32 EventType, u32 Mask)
{
u32 Index;
for(Index=0; Index<XPFW_EV_MAX;Index++){
if((EventTable[Index].RegMask == Mask) && (EventTable[Index].Type == EventType)){
for (Index=0; Index<XPFW_EV_MAX;Index++) {
if ((EventTable[Index].RegMask == Mask) &&
(EventTable[Index].Type == EventType)) {
break;
}
}
@ -312,14 +295,13 @@ u32 XPfw_EventGetId(u32 EventType, u32 Mask)
return Index;
}
u32 XPfw_EventGetType(u32 EventId)
{
u32 EventType;
if(EventId < XPFW_EV_MAX) {
if (EventId < XPFW_EV_MAX) {
EventType = EventTable[EventId].Type;
}
else {
} else {
EventType = XPFW_EV_TYPE_INVALID;
}

289
lib/sw_apps/zynqmp_pmufw/src/xpfw_interrupts.c
View file

@ -1,5 +1,4 @@
/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
@ -27,7 +26,6 @@
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#include "xpfw_interrupts.h"
@ -42,95 +40,93 @@
*/
static u32 InterruptRegsiter;
/**
* This list of IDs enables re-ordering of Events for GPI1 as per user's priority
*/
static u32 Gpi1EventIdList[]={
XPFW_EV_APB_AIB_ERROR,
XPFW_EV_AXI_AIB_ERROR,
XPFW_EV_ERROR_2,
XPFW_EV_ERROR_1,
XPFW_EV_ACPU_3_DBG_PWRUP,
XPFW_EV_ACPU_2_DBG_PWRUP,
XPFW_EV_ACPU_1_DBG_PWRUP,
XPFW_EV_ACPU_0_DBG_PWRUP,
XPFW_EV_FPD_WAKE_GIC_PROXY,
XPFW_EV_MIO_WAKE_5,
XPFW_EV_MIO_WAKE_4,
XPFW_EV_MIO_WAKE_3,
XPFW_EV_MIO_WAKE_2,
XPFW_EV_MIO_WAKE_1,
XPFW_EV_MIO_WAKE_0,
XPFW_EV_DAP_RPU_WAKE,
XPFW_EV_DAP_FPD_WAKE,
XPFW_EV_USB_1_WAKE,
XPFW_EV_USB_0_WAKE,
XPFW_EV_R5_1_WAKE,
XPFW_EV_R5_0_WAKE,
XPFW_EV_ACPU_3_WAKE,
XPFW_EV_ACPU_2_WAKE,
XPFW_EV_ACPU_1_WAKE,
XPFW_EV_ACPU_0_WAKE
static u32 Gpi1EventIdList[] = {
XPFW_EV_APB_AIB_ERROR,
XPFW_EV_AXI_AIB_ERROR,
XPFW_EV_ERROR_2,
XPFW_EV_ERROR_1,
XPFW_EV_ACPU_3_DBG_PWRUP,
XPFW_EV_ACPU_2_DBG_PWRUP,
XPFW_EV_ACPU_1_DBG_PWRUP,
XPFW_EV_ACPU_0_DBG_PWRUP,
XPFW_EV_FPD_WAKE_GIC_PROXY,
XPFW_EV_MIO_WAKE_5,
XPFW_EV_MIO_WAKE_4,
XPFW_EV_MIO_WAKE_3,
XPFW_EV_MIO_WAKE_2,
XPFW_EV_MIO_WAKE_1,
XPFW_EV_MIO_WAKE_0,
XPFW_EV_DAP_RPU_WAKE,
XPFW_EV_DAP_FPD_WAKE,
XPFW_EV_USB_1_WAKE,
XPFW_EV_USB_0_WAKE,
XPFW_EV_R5_1_WAKE,
XPFW_EV_R5_0_WAKE,
XPFW_EV_ACPU_3_WAKE,
XPFW_EV_ACPU_2_WAKE,
XPFW_EV_ACPU_1_WAKE,
XPFW_EV_ACPU_0_WAKE
};
static u32 Gpi2EventIdList[]={XPFW_EV_VCC_INT_FP_DISCONNECT,
XPFW_EV_VCC_INT_DISCONNECT,
XPFW_EV_VCC_AUX_DISCONNECT,
XPFW_EV_DBG_ACPU3_RST_REQ,
XPFW_EV_DBG_ACPU2_RST_REQ,
XPFW_EV_DBG_ACPU1_RST_REQ,
XPFW_EV_DBG_ACPU0_RST_REQ,
XPFW_EV_CP_ACPU3_RST_REQ,
XPFW_EV_CP_ACPU2_RST_REQ,
XPFW_EV_CP_ACPU1_RST_REQ,
XPFW_EV_CP_ACPU0_RST_REQ,
XPFW_EV_DBG_RCPU1_RST_REQ,
XPFW_EV_DBG_RCPU0_RST_REQ,
XPFW_EV_R5_1_SLEEP,
XPFW_EV_R5_0_SLEEP,
XPFW_EV_ACPU_3_SLEEP,
XPFW_EV_ACPU_2_SLEEP,
XPFW_EV_ACPU_1_SLEEP,
XPFW_EV_ACPU_0_SLEEP
};
static u32 Gpi3EventIdList[]={XPFW_EV_PL_GPI_31,
XPFW_EV_PL_GPI_30,
XPFW_EV_PL_GPI_29,
XPFW_EV_PL_GPI_28,
XPFW_EV_PL_GPI_27,
XPFW_EV_PL_GPI_26,
XPFW_EV_PL_GPI_25,
XPFW_EV_PL_GPI_24,
XPFW_EV_PL_GPI_23,
XPFW_EV_PL_GPI_22,
XPFW_EV_PL_GPI_21,
XPFW_EV_PL_GPI_20,
XPFW_EV_PL_GPI_19,
XPFW_EV_PL_GPI_18,
XPFW_EV_PL_GPI_17,
XPFW_EV_PL_GPI_16,
XPFW_EV_PL_GPI_15,
XPFW_EV_PL_GPI_14,
XPFW_EV_PL_GPI_13,
XPFW_EV_PL_GPI_12,
XPFW_EV_PL_GPI_11,
XPFW_EV_PL_GPI_10,
XPFW_EV_PL_GPI_9,
XPFW_EV_PL_GPI_8,
XPFW_EV_PL_GPI_7,
XPFW_EV_PL_GPI_6,
XPFW_EV_PL_GPI_5,
XPFW_EV_PL_GPI_4,
XPFW_EV_PL_GPI_3,
XPFW_EV_PL_GPI_2,
XPFW_EV_PL_GPI_1,
XPFW_EV_PL_GPI_0,
static u32 Gpi2EventIdList[] = {
XPFW_EV_VCC_INT_FP_DISCONNECT,
XPFW_EV_VCC_INT_DISCONNECT,
XPFW_EV_VCC_AUX_DISCONNECT,
XPFW_EV_DBG_ACPU3_RST_REQ,
XPFW_EV_DBG_ACPU2_RST_REQ,
XPFW_EV_DBG_ACPU1_RST_REQ,
XPFW_EV_DBG_ACPU0_RST_REQ,
XPFW_EV_CP_ACPU3_RST_REQ,
XPFW_EV_CP_ACPU2_RST_REQ,
XPFW_EV_CP_ACPU1_RST_REQ,
XPFW_EV_CP_ACPU0_RST_REQ,
XPFW_EV_DBG_RCPU1_RST_REQ,
XPFW_EV_DBG_RCPU0_RST_REQ,
XPFW_EV_R5_1_SLEEP,
XPFW_EV_R5_0_SLEEP,
XPFW_EV_ACPU_3_SLEEP,
XPFW_EV_ACPU_2_SLEEP,
XPFW_EV_ACPU_1_SLEEP,
XPFW_EV_ACPU_0_SLEEP
};
static u32 Gpi3EventIdList[] = {
XPFW_EV_PL_GPI_31,
XPFW_EV_PL_GPI_30,
XPFW_EV_PL_GPI_29,
XPFW_EV_PL_GPI_28,
XPFW_EV_PL_GPI_27,
XPFW_EV_PL_GPI_26,
XPFW_EV_PL_GPI_25,
XPFW_EV_PL_GPI_24,
XPFW_EV_PL_GPI_23,
XPFW_EV_PL_GPI_22,
XPFW_EV_PL_GPI_21,
XPFW_EV_PL_GPI_20,
XPFW_EV_PL_GPI_19,
XPFW_EV_PL_GPI_18,
XPFW_EV_PL_GPI_17,
XPFW_EV_PL_GPI_16,
XPFW_EV_PL_GPI_15,
XPFW_EV_PL_GPI_14,
XPFW_EV_PL_GPI_13,
XPFW_EV_PL_GPI_12,
XPFW_EV_PL_GPI_11,
XPFW_EV_PL_GPI_10,
XPFW_EV_PL_GPI_9,
XPFW_EV_PL_GPI_8,
XPFW_EV_PL_GPI_7,
XPFW_EV_PL_GPI_6,
XPFW_EV_PL_GPI_5,
XPFW_EV_PL_GPI_4,
XPFW_EV_PL_GPI_3,
XPFW_EV_PL_GPI_2,
XPFW_EV_PL_GPI_1,
XPFW_EV_PL_GPI_0,
};
static void XPfw_NullHandler(void)
{
@ -143,28 +139,26 @@ static void XPfw_NullHandler(void)
static void XPfw_InterruptGpi0Handler(void)
{
XStatus Status;
Status = XPfw_CoreDispatchEvent(XPFW_EV_MB_FAULT);
XStatus Status = XPfw_CoreDispatchEvent(XPFW_EV_MB_FAULT);
if (XST_SUCCESS != Status) {
fw_printf("Warning: Failed to dispatch Event ID: %d\r\n",
XPFW_EV_MB_FAULT);
}
}
static void XPfw_InterruptGpi1Handler(void)
{
u32 Index, GpiRegVal, RegMask;
XStatus Status;
GpiRegVal = XPfw_Read32(PMU_IOMODULE_GPI1);
u32 Index;
for (Index = 0U; Index < ARRAYSIZE(Gpi1EventIdList); Index++) {
u32 RegMask = XPfw_EventGetRegMask(Gpi1EventIdList[Index]);
u32 GpiRegVal = XPfw_Read32(PMU_IOMODULE_GPI1);
RegMask = XPfw_EventGetRegMask(Gpi1EventIdList[Index]);
if ((GpiRegVal & RegMask) == RegMask) {
/* Dispatch the event to Registered Modules */
Status = XPfw_CoreDispatchEvent(Gpi1EventIdList[Index]);
XStatus Status = XPfw_CoreDispatchEvent(Gpi1EventIdList[Index]);
if (XST_SUCCESS != Status) {
fw_printf("Warning: Failed to dispatch Event ID: %d\r\n",
Gpi1EventIdList[Index]);
@ -172,19 +166,19 @@ static void XPfw_InterruptGpi1Handler(void)
}
}
}
static void XPfw_InterruptGpi2Handler(void)
{
u32 Index, GpiRegVal, RegMask;
XStatus Status;
GpiRegVal = XPfw_Read32(PMU_IOMODULE_GPI2);
u32 Index;
for (Index = 0U; Index < ARRAYSIZE(Gpi2EventIdList); Index++) {
u32 RegMask = XPfw_EventGetRegMask(Gpi2EventIdList[Index]);
u32 GpiRegVal = XPfw_Read32(PMU_IOMODULE_GPI2);
RegMask = XPfw_EventGetRegMask(Gpi2EventIdList[Index]);
if ((GpiRegVal & RegMask) == RegMask) {
/* Dispatch the event to Registered Modules */
Status = XPfw_CoreDispatchEvent(Gpi2EventIdList[Index]);
XStatus Status = XPfw_CoreDispatchEvent(Gpi2EventIdList[Index]);
if (XST_SUCCESS != Status) {
fw_printf("Warning: Failed to dispatch Event ID: %d\r\n",
Gpi2EventIdList[Index]);
@ -195,16 +189,16 @@ static void XPfw_InterruptGpi2Handler(void)
static void XPfw_InterruptGpi3Handler(void)
{
u32 Index, GpiRegVal, RegMask;
XStatus Status;
GpiRegVal = XPfw_Read32(PMU_IOMODULE_GPI3);
u32 Index;
for (Index = 0U; Index < ARRAYSIZE(Gpi3EventIdList); Index++) {
u32 RegMask = XPfw_EventGetRegMask(Gpi3EventIdList[Index]);
u32 GpiRegVal = XPfw_Read32(PMU_IOMODULE_GPI3);
RegMask = XPfw_EventGetRegMask(Gpi3EventIdList[Index]);
if ((GpiRegVal & RegMask) == RegMask) {
/* Dispatch the event to Registered Modules */
Status = XPfw_CoreDispatchEvent(Gpi3EventIdList[Index]);
XStatus Status = XPfw_CoreDispatchEvent(Gpi3EventIdList[Index]);
if (XST_SUCCESS != Status) {
fw_printf("Warning: Failed to dispatch Event ID: %d\r\n",
Gpi3EventIdList[Index]);
@ -220,7 +214,6 @@ static void XPfw_InterruptRtcAlaramHandler(void)
(void)XPfw_CoreDispatchEvent(XPFW_EV_RTC_ALARM);
}
static void XPfw_InterruptRtcSecondsmHandler(void)
{
(void)XPfw_CoreDispatchEvent(XPFW_EV_RTC_SECONDS);
@ -233,12 +226,11 @@ static void XPfw_Pit1Handler(void)
static void XPfw_Ipi0Handler(void)
{
XStatus Status;
u32 Mask;
Mask = XPfw_Read32(IPI_PMU_0_ISR);
Status = XPfw_CoreDispatchIpi(0U);
XStatus Status = XPfw_CoreDispatchIpi(0U);
/* If no Mod has registered for IPI, Ack it to prevent re-triggering */
if(XST_SUCCESS != Status){
if (XST_SUCCESS != Status) {
u32 Mask = XPfw_Read32(IPI_PMU_0_ISR);
fw_printf("Error: Unhandled IPI received\r\n");
XPfw_Write32(IPI_PMU_0_ISR, Mask);
}
@ -246,12 +238,11 @@ static void XPfw_Ipi0Handler(void)
static void XPfw_Ipi1Handler(void)
{
XStatus Status;
u32 Mask;
Mask = XPfw_Read32(IPI_PMU_1_ISR);
Status = XPfw_CoreDispatchIpi(1U);
XStatus Status = XPfw_CoreDispatchIpi(1U);
/* If no Mod has registered for IPI, Ack it to prevent re-triggering */
if(XST_SUCCESS != Status){
if (XST_SUCCESS != Status) {
u32 Mask = XPfw_Read32(IPI_PMU_1_ISR);
fw_printf("Error: Unhandled IPI received\r\n");
XPfw_Write32(IPI_PMU_1_ISR, Mask);
}
@ -259,12 +250,11 @@ static void XPfw_Ipi1Handler(void)
static void XPfw_Ipi2Handler(void)
{
XStatus Status;
u32 Mask;
Mask = XPfw_Read32(IPI_PMU_2_ISR);
Status = XPfw_CoreDispatchIpi(2U);
XStatus Status = XPfw_CoreDispatchIpi(2U);
/* If no Mod has registered for IPI, Ack it to prevent re-triggering */
if(XST_SUCCESS != Status){
u32 Mask = XPfw_Read32(IPI_PMU_2_ISR);
fw_printf("Error: Unhandled IPI received\r\n");
XPfw_Write32(IPI_PMU_2_ISR, Mask);
}
@ -272,51 +262,46 @@ static void XPfw_Ipi2Handler(void)
static void XPfw_Ipi3Handler(void)
{
XStatus Status;
u32 Mask;
Mask = XPfw_Read32(IPI_PMU_3_ISR);
Status = XPfw_CoreDispatchIpi(3U);
XStatus Status = XPfw_CoreDispatchIpi(3U);
/* If no Mod has registered for IPI, Ack it to prevent re-triggering */
if(XST_SUCCESS != Status){
u32 Mask = XPfw_Read32(IPI_PMU_3_ISR);
fw_printf("Error: Unhandled IPI received\r\n");
XPfw_Write32(IPI_PMU_3_ISR, Mask);
}
}
static struct HandlerTable g_TopLevelInterruptTable[] ={
{PMU_IOMODULE_IRQ_PENDING_RTC_ALARM_MASK, XPfw_InterruptRtcAlaramHandler},
{PMU_IOMODULE_IRQ_PENDING_RTC_EVERY_SECOND_MASK, XPfw_InterruptRtcSecondsmHandler},
{PMU_IOMODULE_IRQ_PENDING_CORRECTABLE_ECC_MASK, XPfw_NullHandler},
{PMU_IOMODULE_IRQ_PENDING_INV_ADDR_MASK, XPfw_NullHandler},
{PMU_IOMODULE_IRQ_PENDING_IPI3_MASK, XPfw_Ipi3Handler},
{PMU_IOMODULE_IRQ_PENDING_IPI2_MASK, XPfw_Ipi2Handler},
{PMU_IOMODULE_IRQ_PENDING_IPI1_MASK, XPfw_Ipi1Handler},
{PMU_IOMODULE_IRQ_PENDING_IPI0_MASK, XPfw_Ipi0Handler},
{PMU_IOMODULE_IRQ_PENDING_PWR_UP_REQ_MASK, XPfw_NullHandler},
{PMU_IOMODULE_IRQ_PENDING_PWR_DN_REQ_MASK, XPfw_NullHandler},
{PMU_IOMODULE_IRQ_PENDING_ISO_REQ_MASK, XPfw_NullHandler},
{PMU_IOMODULE_IRQ_PENDING_SW_RST_REQ_MASK, XPfw_NullHandler},
{PMU_IOMODULE_IRQ_PENDING_HW_RST_REQ_MASK, XPfw_NullHandler},
{PMU_IOMODULE_IRQ_PENDING_GPI3_MASK, XPfw_InterruptGpi3Handler},
{PMU_IOMODULE_IRQ_PENDING_GPI2_MASK, XPfw_InterruptGpi2Handler},
{PMU_IOMODULE_IRQ_PENDING_GPI1_MASK, XPfw_InterruptGpi1Handler},
{PMU_IOMODULE_IRQ_PENDING_GPI0_MASK, XPfw_InterruptGpi0Handler},
{PMU_IOMODULE_IRQ_PENDING_PIT3_MASK, XPfw_NullHandler},
{PMU_IOMODULE_IRQ_PENDING_PIT2_MASK, XPfw_NullHandler},
{PMU_IOMODULE_IRQ_PENDING_PIT1_MASK, XPfw_Pit1Handler},
{PMU_IOMODULE_IRQ_PENDING_PIT0_MASK, XPfw_NullHandler},
{PMU_IOMODULE_IRQ_PENDING_CSU_PMU_SEC_LOCK_MASK, XPfw_NullHandler}
static struct HandlerTable g_TopLevelInterruptTable[] = {
{PMU_IOMODULE_IRQ_PENDING_RTC_ALARM_MASK, XPfw_InterruptRtcAlaramHandler},
{PMU_IOMODULE_IRQ_PENDING_RTC_EVERY_SECOND_MASK, XPfw_InterruptRtcSecondsmHandler},
{PMU_IOMODULE_IRQ_PENDING_CORRECTABLE_ECC_MASK, XPfw_NullHandler},
{PMU_IOMODULE_IRQ_PENDING_INV_ADDR_MASK, XPfw_NullHandler},
{PMU_IOMODULE_IRQ_PENDING_IPI3_MASK, XPfw_Ipi3Handler},
{PMU_IOMODULE_IRQ_PENDING_IPI2_MASK, XPfw_Ipi2Handler},
{PMU_IOMODULE_IRQ_PENDING_IPI1_MASK, XPfw_Ipi1Handler},
{PMU_IOMODULE_IRQ_PENDING_IPI0_MASK, XPfw_Ipi0Handler},
{PMU_IOMODULE_IRQ_PENDING_PWR_UP_REQ_MASK, XPfw_NullHandler},
{PMU_IOMODULE_IRQ_PENDING_PWR_DN_REQ_MASK, XPfw_NullHandler},
{PMU_IOMODULE_IRQ_PENDING_ISO_REQ_MASK, XPfw_NullHandler},
{PMU_IOMODULE_IRQ_PENDING_SW_RST_REQ_MASK, XPfw_NullHandler},
{PMU_IOMODULE_IRQ_PENDING_HW_RST_REQ_MASK, XPfw_NullHandler},
{PMU_IOMODULE_IRQ_PENDING_GPI3_MASK, XPfw_InterruptGpi3Handler},
{PMU_IOMODULE_IRQ_PENDING_GPI2_MASK, XPfw_InterruptGpi2Handler},
{PMU_IOMODULE_IRQ_PENDING_GPI1_MASK, XPfw_InterruptGpi1Handler},
{PMU_IOMODULE_IRQ_PENDING_GPI0_MASK, XPfw_InterruptGpi0Handler},
{PMU_IOMODULE_IRQ_PENDING_PIT3_MASK, XPfw_NullHandler},
{PMU_IOMODULE_IRQ_PENDING_PIT2_MASK, XPfw_NullHandler},
{PMU_IOMODULE_IRQ_PENDING_PIT1_MASK, XPfw_Pit1Handler},
{PMU_IOMODULE_IRQ_PENDING_PIT0_MASK, XPfw_NullHandler},
{PMU_IOMODULE_IRQ_PENDING_CSU_PMU_SEC_LOCK_MASK, XPfw_NullHandler}
};
void XPfw_InterruptInit(void)
{
XPfw_Write32(PMU_IOMODULE_IRQ_ENABLE, 0U);
Xil_ExceptionDisable();
XPfw_Write32(PMU_IOMODULE_IRQ_ACK, 0xffffffffU);
InterruptRegsiter = 0U;
}
void XPfw_InterruptStart(void)
@ -330,8 +315,7 @@ void XPfw_InterruptHandler(void)
u32 l_IrqReg;
u32 l_index;
if ( XST_SUCCESS == XPfw_CoreIsReady()) {
if (XST_SUCCESS == XPfw_CoreIsReady()) {
/* Latch the IRQ_PENDING register into a local variable */
l_IrqReg = XPfw_Read32(PMU_IOMODULE_IRQ_PENDING);
@ -353,11 +337,8 @@ void XPfw_InterruptHandler(void)
XPfw_Write32(PMU_IOMODULE_IRQ_ENABLE, 0U);
XPfw_Write32(PMU_IOMODULE_IRQ_ACK, 0xffffffffU);
}
}
void XPfw_InterruptDisable(u32 Mask)
{
InterruptRegsiter = InterruptRegsiter & (~Mask);

5
lib/sw_apps/zynqmp_pmufw/src/xpfw_interrupts.h
View file

@ -35,15 +35,10 @@
#include "xpfw_default.h"
void XPfw_InterruptHandler(void) __attribute__ ((interrupt_handler));
void XPfw_InterruptDisable(u32 Mask);
void XPfw_InterruptEnable(u32 Mask);
void XPfw_InterruptStart(void);
void XPfw_InterruptInit(void);
#endif /* XPFW_INTERRUPTS_H_ */

613
lib/sw_apps/zynqmp_pmufw/src/xpfw_rom_interface.h
View file

@ -1,113 +1,500 @@
u32 XpbrACPU0SleepHandler(void);
u32 XpbrACPU0WakeHandler(void);
u32 XpbrACPU1SleepHandler(void);
u32 XpbrACPU1WakeHandler(void);
u32 XpbrACPU2SleepHandler(void);
u32 XpbrACPU2WakeHandler(void);
u32 XpbrACPU3SleepHandler(void);
u32 XpbrACPU3WakeHandler(void);
u32 XpbrCsuSecureLockdownHandler(void);
u32 XpbrDapFpdWakeHandler(void);
u32 XpbrDapRpuWakeHandler(void);
u32 XpbrDefaultWakeHandler(void);
u32 XpbrFpdGicProxyWakeHandler(void);
u32 XpbrFPIsolationReqHandler(void);
u32 XpbrFPLockIsoHandler(void);
u32 XpbrGpi1Router(void);
u32 XpbrGpi2Router(void);
u32 XpbrGpi3Handler(void);
u32 XpbrHwExceptionHandler(void);
u32 XpbrHwRstReqHandler(void);
u32 XpbrIpi0Handler(void);
u32 XpbrIsoReqRouter(void);
u32 XpbrMio0WakeHandler(void);
u32 XpbrMio1WakeHandler(void);
u32 XpbrMio2WakeHandler(void);
u32 XpbrMio3WakeHandler(void);
u32 XpbrMio4WakeHandler(void);
u32 XpbrMio5WakeHandler(void);
u32 XpbrNullInterruptHandler(void);
u32 XpbrNullServiceHandler(void);
u32 XpbrPLIsolationReqHandler(void);
u32 XpbrPLNonPCAPIsoReqHandler(void);
u32 XpbrPwrDnACPU0Handler(void);
u32 XpbrPwrDnACPU1Handler(void);
u32 XpbrPwrDnACPU2Handler(void);
u32 XpbrPwrDnACPU3Handler(void);
u32 XpbrPwrDnFpdHandler(void);
u32 XpbrPwrDnGpuHandler(void);
u32 XpbrPwrDnL2Bank0Handler(void);
u32 XpbrPwrDnOcmBank0Handler(void);
u32 XpbrPwrDnOcmBank1Handler(void);
u32 XpbrPwrDnOcmBank2Handler(void);
u32 XpbrPwrDnOcmBank3Handler(void);
u32 XpbrPwrDnPldHandler(void);
u32 XpbrPwrDnPp0Handler(void);
u32 XpbrPwrDnPp1Handler(void);
u32 XpbrPwrDnR50Handler(void);
u32 XpbrPwrDnR51Handler(void);
u32 XpbrPwrDnReqRouter(void);
u32 XpbrPwrDnRpuHandler(void);
u32 XpbrPwrDnTcm0AHandler(void);
u32 XpbrPwrDnTcm0BHandler(void);
u32 XpbrPwrDnTcm1AHandler(void);
u32 XpbrPwrDnTcm1BHandler(void);
u32 XpbrPwrDnUsb0Handler(void);
u32 XpbrPwrDnUsb1Handler(void);
u32 XpbrPwrUpACPU0Handler(void);
u32 XpbrPwrUpACPU1Handler(void);
u32 XpbrPwrUpACPU2Handler(void);
u32 XpbrPwrUpACPU3Handler(void);
u32 XpbrPwrUpFpdHandler(void);
u32 XpbrPwrUpL2Bank0Handler(void);
u32 XpbrPwrUpOcmBank0Handler(void);
u32 XpbrPwrUpOcmBank1Handler(void);
u32 XpbrPwrUpOcmBank2Handler(void);
u32 XpbrPwrUpOcmBank3Handler(void);
u32 XpbrPwrUpPldHandler(void);
u32 XpbrPwrUpPp0Handler(void);
u32 XpbrPwrUpPp1Handler(void);
u32 XpbrPwrUpReqRouter(void);
u32 XpbrPwrUpRpuHandler(void);
u32 XpbrPwrUpTcm0AHandler(void);
u32 XpbrPwrUpTcm0BHandler(void);
u32 XpbrPwrUpTcm1AHandler(void);
u32 XpbrPwrUpTcm1BHandler(void);
u32 XpbrPwrUpUsb0Handler(void);
u32 XpbrPwrUpUsb1Handler(void);
u32 XpbrR50SleepHandler(void);
u32 XpbrR50WakeHandler(void);
u32 XpbrR51SleepHandler(void);
u32 XpbrR51WakeHandler(void);
u32 XpbrROMExceptionHandler(void);
u32 XpbrRstACPU0Handler(void);
u32 XpbrRstACPU1Handler(void);
u32 XpbrRstACPU2Handler(void);
u32 XpbrRstACPU3Handler(void);
u32 XpbrRstACPUxHandler(void);
u32 XpbrRstApuHandler(void);
u32 XpbrRstDisplayPortHandler(void);
u32 XpbrRstFpdHandler(void);
u32 XpbrRstGem0Handler(void);
u32 XpbrRstGem1Handler(void);
u32 XpbrRstGem2Handler(void);
u32 XpbrRstGem3Handler(void);
u32 XpbrRstGpuHandler(void);
u32 XpbrRstLsRpuHandler(void);
u32 XpbrRstPCIeHandler(void);
u32 XpbrRstPp0Handler(void);
u32 XpbrRstPp1Handler(void);
u32 XpbrRstPsOnlyHandler(void);
u32 XpbrRstR50Handler(void);
u32 XpbrRstR51Handler(void);
u32 XpbrRstSataHandler(void);
u32 XpbrRstUsb0Handler(void);
u32 XpbrRstUsb1Handler(void);
u32 XpbrRtcAlarmHandler(void);
u32 XpbrServiceHandler(void);
u32 XpbrServiceMode(void);
u32 XpbrSwExceptionHandler(void);
u32 XpbrSwRstReqRouter(void);
u32 XpbrTMRFaultDetectionHandler(void);
u32 XpbrUsb0WakeHandler(void);
u32 XpbrUsb1WakeHandler(void);
/*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*/
/**
*
* PMU_ROM SERVICE EXTENSION IDCODES
*
* All Services implemented in the ROM can be extended or overriden by
* firmware loaded into the PMU_RAM. Including the IRQ routing infrastructure.
* Aside from the PMU_ROM Service Functions, other extendable/overridable
* `hooks` are provided to the firmware. These PMU_ROM Service Hooks are
* included in the Extension Table but also have their IDCODES highlighted
* below.
*
* Before calling the default implementation of these services, ROM checks the
* index indicated below in the Service Extension Table for a function address.
* If a function pointer is found, ROM will call that function /instead/ of the
* default ROM function. However, as an argument to the FW function, is a
* callback to the default ROM function, thus allowing the overriding FW to
* implmentent wrapping logic around existing ROM behavior.
*
* @note: These Identifiers are also used to identify the service mode
* error.
*/
enum xpbr_serv_ext_id {
XPBR_SERV_EXT_TBL_BASE = 0U,
/* RESERVED 1U */
/* RESERVED 2U */
XPBR_SERV_EXT_PIT0 = 3U,
XPBR_SERV_EXT_PIT1 = 4U,
XPBR_SERV_EXT_PIT2 = 5U,
XPBR_SERV_EXT_PIT3 = 6U,
/* RESERVED 7U */
/* RESERVED 8U */
/* RESERVED 9U */
/* RESERVED 10U */
XPBR_SERV_EXT_TMRFAULT = 11U,
XPBR_SERV_EXT_GPI1 = 12U,
XPBR_SERV_EXT_GPI2 = 13U,
XPBR_SERV_EXT_GPI3 = 14U,
/* RESERVED 15U */
XPBR_SERV_EXT_COR_ECC_HANDLER = 16U,
XPBR_SERV_EXT_RTCEVERYSECOND = 17U,
XPBR_SERV_EXT_RTCALARM = 18U,
XPBR_SERV_EXT_IPI0 = 19U,
XPBR_SERV_EXT_IPI1 = 20U,
XPBR_SERV_EXT_IPI2 = 21U,
XPBR_SERV_EXT_IPI3 = 22U,
XPBR_SERV_EXT_FW_REQS = 23U,
XPBR_SERV_EXT_ISO_REQS = 24U,
XPBR_SERV_EXT_HWRST = 25U,
XPBR_SERV_EXT_SWRST_REQS = 26U,
XPBR_SERV_EXT_PWRUP_REQS = 27U,
XPBR_SERV_EXT_PWRDN_REQS = 28U,
XPBR_SERV_EXT_INVADDR = 29U,
/* RESERVED 30U */
XPBR_SERV_EXT_CSU_SECLOCK = 31U,
XPBR_SERV_EXT_ACPU0WAKE = 32U,
XPBR_SERV_EXT_ACPU1WAKE = 33U,
XPBR_SERV_EXT_ACPU2WAKE = 34U,
XPBR_SERV_EXT_ACPU3WAKE = 35U,
XPBR_SERV_EXT_R50WAKE = 36U,
XPBR_SERV_EXT_R51WAKE = 37U,
XPBR_SERV_EXT_USB0WAKE = 38U,
XPBR_SERV_EXT_USB1WAKE = 39U,
XPBR_SERV_EXT_DAPFPDWAKE = 40U,
XPBR_SERV_EXT_DAPRPUWAKE = 41U,
XPBR_SERV_EXT_MIO0WAKE = 42U,
XPBR_SERV_EXT_MIO1WAKE = 43U,
XPBR_SERV_EXT_MIO2WAKE = 44U,
XPBR_SERV_EXT_MIO3WAKE = 45U,
XPBR_SERV_EXT_MIO4WAKE = 46U,
XPBR_SERV_EXT_MIO5WAKE = 47U,
XPBR_SERV_EXT_FPDGICPROXYWAKE = 48U,
/* RESERVED 49U */
/* RESERVED 50U */
/* RESERVED 51U */
XPBR_SERV_EXT_ACPU0DBGPWRUP = 52U,
XPBR_SERV_EXT_ACPU1DBGPWRUP = 53U,
XPBR_SERV_EXT_ACPU2DBGPWRUP = 54U,
XPBR_SERV_EXT_ACPU3DBGPWRUP = 55U,
/* RESERVED 56U */
/* RESERVED 57U */
/* RESERVED 58U */
/* RESERVED 59U */
XPBR_SERV_EXT_ERROR1 = 60U,
XPBR_SERV_EXT_ERROR2 = 61U,
XPBR_SERV_EXT_AXIAIBERR = 62U,
XPBR_SERV_EXT_APBAIBERR = 63U,
XPBR_SERV_EXT_ACPU0SLEEP = 64U,
XPBR_SERV_EXT_ACPU1SLEEP = 65U,
XPBR_SERV_EXT_ACPU2SLEEP = 66U,
XPBR_SERV_EXT_ACPU3SLEEP = 67U,
XPBR_SERV_EXT_R50SLEEP = 68U,
XPBR_SERV_EXT_R51SLEEP = 69U,
/* RESERVED 70U */
/* RESERVED 71U */
XPBR_SERV_EXT_RCPU0_DBG_RST = 72U,
XPBR_SERV_EXT_RCPU1_DBG_RST = 73U,
/* RESERVED 74U */
/* RESERVED 75U */
/* RESERVED 76U */
/* RESERVED 77U */
/* RESERVED 78U */
/* RESERVED 79U */
XPBR_SERV_EXT_ACPU0_CP_RST = 80U,
XPBR_SERV_EXT_ACPU1_CP_RST = 81U,
XPBR_SERV_EXT_ACPU2_CP_RST = 82U,
XPBR_SERV_EXT_ACPU3_CP_RST = 83U,
XPBR_SERV_EXT_ACPU0_DBG_RST = 84U,
XPBR_SERV_EXT_ACPU1_DBG_RST = 85U,
XPBR_SERV_EXT_ACPU2_DBG_RST = 86U,
XPBR_SERV_EXT_ACPU3_DBG_RST = 87U,
/* RESERVED 88U */
/* RESERVED 89U */
/* RESERVED 90U */
/* RESERVED 91U */
/* RESERVED 92U */
XPBR_SERV_EXT_VCCAUX_DISCONNECT = 93U,
XPBR_SERV_EXT_VCCINT_DISCONNECT = 94U,
XPBR_SERV_EXT_VCCINTFP_DISCONNECT = 95U,
XPBR_SERV_EXT_PWRUPACPU0 = 96U,
XPBR_SERV_EXT_PWRUPACPU1 = 97U,
XPBR_SERV_EXT_PWRUPACPU2 = 98U,
XPBR_SERV_EXT_PWRUPACPU3 = 99U,
XPBR_SERV_EXT_PWRUPPP0 = 100U,
XPBR_SERV_EXT_PWRUPPP1 = 101U,
/* RESERVED 102U */
XPBR_SERV_EXT_PWRUPL2BANK0 = 103U,
/* RESERVED 104U */
/* RESERVED 105U */
XPBR_SERV_EXT_PWRUPRPU = 106U,
/* RESERVED 107U */
XPBR_SERV_EXT_PWRUPTCM0A = 108U,
XPBR_SERV_EXT_PWRUPTCM0B = 109U,
XPBR_SERV_EXT_PWRUPTCM1A = 110U,
XPBR_SERV_EXT_PWRUPTCM1B = 111U,
XPBR_SERV_EXT_PWRUPOCMBANK0 = 112U,
XPBR_SERV_EXT_PWRUPOCMBANK1 = 113U,
XPBR_SERV_EXT_PWRUPOCMBANK2 = 114U,
XPBR_SERV_EXT_PWRUPOCMBANK3 = 115U,
XPBR_SERV_EXT_PWRUPUSB0 = 116U,
XPBR_SERV_EXT_PWRUPUSB1 = 117U,
XPBR_SERV_EXT_PWRUPFPD = 118U,
XPBR_SERV_EXT_PWRUPPLD = 119U,
/* RESERVED 120U */
/* RESERVED 121U */
/* RESERVED 122U */
/* RESERVED 123U */
/* RESERVED 124U */
/* RESERVED 125U */
/* RESERVED 126U */
/* RESERVED 127U */
XPBR_SERV_EXT_PWRDNACPU0 = 128U,
XPBR_SERV_EXT_PWRDNACPU1 = 129U,
XPBR_SERV_EXT_PWRDNACPU2 = 130U,
XPBR_SERV_EXT_PWRDNACPU3 = 131U,
XPBR_SERV_EXT_PWRDNPP0 = 132U,
XPBR_SERV_EXT_PWRDNPP1 = 133U,
/* RESERVED 134U */
XPBR_SERV_EXT_PWRDNL2BANK0 = 135U,
/* RESERVED 136U */
/* RESERVED 137U */
XPBR_SERV_EXT_PWRDNRPU = 138U,
/* RESERVED 139U */
XPBR_SERV_EXT_PWRDNTCM0A = 140U,
XPBR_SERV_EXT_PWRDNTCM0B = 141U,
XPBR_SERV_EXT_PWRDNTCM1A = 142U,
XPBR_SERV_EXT_PWRDNTCM1B = 143U,
XPBR_SERV_EXT_PWRDNOCMBANK0 = 144U,
XPBR_SERV_EXT_PWRDNOCMBANK1 = 145U,
XPBR_SERV_EXT_PWRDNOCMBANK2 = 146U,
XPBR_SERV_EXT_PWRDNOCMBANK3 = 147U,
XPBR_SERV_EXT_PWRDNUSB0 = 148U,
XPBR_SERV_EXT_PWRDNUSB1 = 149U,
XPBR_SERV_EXT_PWRDNFPD = 150U,
XPBR_SERV_EXT_PWRDNPLD = 151U,
/* RESERVED 152U */
/* RESERVED 153U */
/* RESERVED 154U */
/* RESERVED 155U */
/* RESERVED 156U */
/* RESERVED 157U */
/* RESERVED 158U */
/* RESERVED 159U */
XPBR_SERV_EXT_FPISOLATION = 160U,
XPBR_SERV_EXT_PLISOLATION = 161U,
XPBR_SERV_EXT_PLNONPCAPISO = 162U,
/* RESERVED 163U */
XPBR_SERV_EXT_FPLOCKISO = 164U,
/* RESERVED 165U */
/* RESERVED 166U */
/* RESERVED 167U */
/* RESERVED 168U */
/* RESERVED 169U */
/* RESERVED 170U */
/* RESERVED 171U */
/* RESERVED 172U */
/* RESERVED 173U */
/* RESERVED 174U */
/* RESERVED 175U */
/* RESERVED 176U */
/* RESERVED 177U */
/* RESERVED 178U */
/* RESERVED 179U */
/* RESERVED 180U */
/* RESERVED 181U */
/* RESERVED 182U */
/* RESERVED 183U */
/* RESERVED 184U */
/* RESERVED 185U */
/* RESERVED 186U */
/* RESERVED 187U */
/* RESERVED 188U */
/* RESERVED 189U */
/* RESERVED 190U */
/* RESERVED 191U */
XPBR_SERV_EXT_RSTACPU0 = 192U,
XPBR_SERV_EXT_RSTACPU1 = 193U,
XPBR_SERV_EXT_RSTACPU2 = 194U,
XPBR_SERV_EXT_RSTACPU3 = 195U,
XPBR_SERV_EXT_RSTAPU = 196U,
/* RESERVED 197U */
XPBR_SERV_EXT_RSTPP0 = 198U,
XPBR_SERV_EXT_RSTPP1 = 199U,
XPBR_SERV_EXT_RSTGPU = 200U,
XPBR_SERV_EXT_RSTPCIE = 201U,
XPBR_SERV_EXT_RSTSATA = 202U,
/* RESERVED 203U */
XPBR_SERV_EXT_RSTDISPLAYPORT = 204U,
/* RESERVED 205U */
/* RESERVED 206U */
/* RESERVED 207U */
XPBR_SERV_EXT_RSTR50 = 208U,
XPBR_SERV_EXT_RSTR51 = 209U,
XPBR_SERV_EXT_RSTLSRPU = 210U,
/* RESERVED 211U */
XPBR_SERV_EXT_RSTGEM0 = 212U,
XPBR_SERV_EXT_RSTGEM1 = 213U,
XPBR_SERV_EXT_RSTGEM2 = 214U,
XPBR_SERV_EXT_RSTGEM3 = 215U,
XPBR_SERV_EXT_RSTUSB0 = 216U,
XPBR_SERV_EXT_RSTUSB1 = 217U,
/* RESERVED 218U */
XPBR_SERV_EXT_RSTIOU = 219U,
XPBR_SERV_EXT_RSTPSONLY = 220U,
XPBR_SERV_EXT_RSTLPD = 221U,
XPBR_SERV_EXT_RSTFPD = 222U,
XPBR_SERV_EXT_RSTPLD = 223U,
XPBR_SERV_EXT_FW_REQ_0 = 224U,
XPBR_SERV_EXT_FW_REQ_1 = 225U,
XPBR_SERV_EXT_FW_REQ_2 = 226U,
XPBR_SERV_EXT_FW_REQ_3 = 227U,
/* RESERVED 228U */
/* RESERVED 229U */
XPBR_SERV_EXT_FW_REQ_4 = 230U,
XPBR_SERV_EXT_FW_REQ_5 = 231U,
/* RESERVED 232U */
/* RESERVED 233U */
XPBR_SERV_EXT_FW_REQ_6 = 234U,
/* RESERVED 235U */
XPBR_SERV_EXT_FW_REQ_7 = 236U,
XPBR_SERV_EXT_FW_REQ_8 = 237U,
/* RESERVED 238U */
/* RESERVED 239U */
XPBR_SERV_EXT_FW_REQ_9 = 240U,
XPBR_SERV_EXT_FW_REQ_10 = 241U,
/* RESERVED 242U */
/* RESERVED 243U */
/* RESERVED 244U */
/* RESERVED 245U */
/* RESERVED 246U */
/* RESERVED 247U */
/* RESERVED 248U */
/* RESERVED 249U */
XPBR_SERV_EXT_FPD_SUPPYENABLE = 250U,
XPBR_SERV_EXT_FPD_SUPPYDISABLE = 251U,
XPBR_SERV_EXT_FPD_SUPPYCHECK = 252U,
XPBR_SERV_EXT_PLD_SUPPYENABLE = 253U,
XPBR_SERV_EXT_PLD_SUPPYDISABLE = 254U,
XPBR_SERV_EXT_PLD_SUPPYCHECK = 255U,
XPBR_SERV_EXT_TBL_MAX = 256U
};
typedef u32 (*XpbrServHndlr_t) (void);
extern const XpbrServHndlr_t XpbrServHndlrTbl[XPBR_SERV_EXT_TBL_MAX];
static inline u32 XpbrACPU0SleepHandler(void)
{
return XpbrServHndlrTbl[XPBR_SERV_EXT_ACPU0SLEEP]();
}
static inline u32 XpbrACPU0WakeHandler(void)
{
return XpbrServHndlrTbl[XPBR_SERV_EXT_ACPU0WAKE]();
}
static inline u32 XpbrACPU1SleepHandler(void)
{
return XpbrServHndlrTbl[XPBR_SERV_EXT_ACPU1SLEEP]();
}
static inline u32 XpbrACPU1WakeHandler(void)
{
return XpbrServHndlrTbl[XPBR_SERV_EXT_ACPU1WAKE]();
}
static inline u32 XpbrACPU2SleepHandler(void)
{
return XpbrServHndlrTbl[XPBR_SERV_EXT_ACPU2SLEEP]();
}
static inline u32 XpbrACPU2WakeHandler(void)
{
return XpbrServHndlrTbl[XPBR_SERV_EXT_ACPU2WAKE]();
}
static inline u32 XpbrACPU3SleepHandler(void)
{
return XpbrServHndlrTbl[XPBR_SERV_EXT_ACPU3SLEEP]();
}
static inline u32 XpbrACPU3WakeHandler(void)
{
return XpbrServHndlrTbl[XPBR_SERV_EXT_ACPU3WAKE]();
}
static inline u32 XpbrRstFpdHandler(void)
{
return XpbrServHndlrTbl[XPBR_SERV_EXT_RSTFPD]();
}
static inline u32 XpbrPwrDnFpdHandler(void)
{
return XpbrServHndlrTbl[XPBR_SERV_EXT_PWRDNFPD]();
}
static inline u32 XpbrPwrUpFpdHandler(void)
{
return XpbrServHndlrTbl[XPBR_SERV_EXT_PWRUPFPD]();
}
static inline u32 XpbrPwrDnRpuHandler(void)
{
return XpbrServHndlrTbl[XPBR_SERV_EXT_PWRDNRPU]();
}
static inline u32 XpbrPwrUpRpuHandler(void)
{
return XpbrServHndlrTbl[XPBR_SERV_EXT_PWRUPRPU]();
}
static inline u32 XpbrRstR50Handler(void)
{
return XpbrServHndlrTbl[XPBR_SERV_EXT_RSTR50]();
}
static inline u32 XpbrRstR51Handler(void)
{
return XpbrServHndlrTbl[XPBR_SERV_EXT_RSTR51]();
}
static inline u32 XpbrPwrDnOcmBank0Handler(void)
{
return XpbrServHndlrTbl[XPBR_SERV_EXT_PWRDNOCMBANK0]();
}
static inline u32 XpbrPwrDnOcmBank1Handler(void)
{
return XpbrServHndlrTbl[XPBR_SERV_EXT_PWRDNOCMBANK1]();
}
static inline u32 XpbrPwrDnOcmBank2Handler(void)
{
return XpbrServHndlrTbl[XPBR_SERV_EXT_PWRDNOCMBANK2]();
}
static inline u32 XpbrPwrDnOcmBank3Handler(void)
{
return XpbrServHndlrTbl[XPBR_SERV_EXT_PWRDNOCMBANK3]();
}
static inline u32 XpbrPwrUpOcmBank0Handler(void)
{
return XpbrServHndlrTbl[XPBR_SERV_EXT_PWRUPOCMBANK0]();
}
static inline u32 XpbrPwrUpOcmBank1Handler(void)
{
return XpbrServHndlrTbl[XPBR_SERV_EXT_PWRUPOCMBANK1]();
}
static inline u32 XpbrPwrUpOcmBank2Handler(void)
{
return XpbrServHndlrTbl[XPBR_SERV_EXT_PWRUPOCMBANK2]();
}
static inline u32 XpbrPwrUpOcmBank3Handler(void)
{
return XpbrServHndlrTbl[XPBR_SERV_EXT_PWRUPOCMBANK3]();
}
static inline u32 XpbrPwrDnTcm0AHandler(void)
{
return XpbrServHndlrTbl[XPBR_SERV_EXT_PWRDNTCM0A]();
}
static inline u32 XpbrPwrDnTcm0BHandler(void)
{
return XpbrServHndlrTbl[XPBR_SERV_EXT_PWRDNTCM0B]();
}
static inline u32 XpbrPwrDnTcm1AHandler(void)
{
return XpbrServHndlrTbl[XPBR_SERV_EXT_PWRDNTCM1A]();
}
static inline u32 XpbrPwrDnTcm1BHandler(void)
{
return XpbrServHndlrTbl[XPBR_SERV_EXT_PWRDNTCM1B]();
}
static inline u32 XpbrPwrUpTcm0AHandler(void)
{
return XpbrServHndlrTbl[XPBR_SERV_EXT_PWRUPTCM0A]();
}
static inline u32 XpbrPwrUpTcm0BHandler(void)
{
return XpbrServHndlrTbl[XPBR_SERV_EXT_PWRUPTCM0B]();
}
static inline u32 XpbrPwrUpTcm1AHandler(void)
{
return XpbrServHndlrTbl[XPBR_SERV_EXT_PWRUPTCM1A]();
}
static inline u32 XpbrPwrUpTcm1BHandler(void)
{
return XpbrServHndlrTbl[XPBR_SERV_EXT_PWRUPTCM1B]();
}
static inline u32 XpbrPwrDnL2Bank0Handler(void)
{
return XpbrServHndlrTbl[XPBR_SERV_EXT_PWRDNL2BANK0]();
}
static inline u32 XpbrPwrUpL2Bank0Handler(void)
{
return XpbrServHndlrTbl[XPBR_SERV_EXT_PWRUPL2BANK0]();
}
static inline u32 XpbrPwrDnUsb0Handler(void)
{
return XpbrServHndlrTbl[XPBR_SERV_EXT_PWRDNUSB0]();
}
static inline u32 XpbrPwrDnUsb1Handler(void)
{
return XpbrServHndlrTbl[XPBR_SERV_EXT_PWRDNUSB1]();
}
static inline u32 XpbrPwrUpUsb0Handler(void)
{
return XpbrServHndlrTbl[XPBR_SERV_EXT_PWRUPUSB0]();
}
static inline u32 XpbrPwrUpUsb1Handler(void)
{
return XpbrServHndlrTbl[XPBR_SERV_EXT_PWRUPUSB1]();
}

143
lib/sw_apps/zynqmp_pmufw/src/xpfw_scheduler.c
View file

@ -1,5 +1,4 @@
/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
@ -27,7 +26,6 @@
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#include "xpfw_scheduler.h"
@ -44,54 +42,59 @@
* Microblaze IOModule PIT Register Offsets
* Used internally in this file
*/
#define PIT_PRELOAD_OFFSET 0U
#define PIT_PRELOAD_OFFSET 0U
#define PIT_COUNTER_OFFSET 4U
#define PIT_CONTROL_OFFSET 8U
#define PIT_CONTROL_OFFSET 8U
XStatus XPfw_SchedulerInit(XPfw_Scheduler_t *SchedPtr, u32 PitBaseAddr)
{
u32 Idx;
XStatus Status;
if (SchedPtr != NULL) {
/* Disable all the tasks */
for (Idx = 0U; Idx < XPFW_SCHED_MAX_TASK; Idx++) {
SchedPtr->TaskList[Idx].Interval = 0U;
SchedPtr->TaskList[Idx].Callback = NULL;
}
SchedPtr->Enabled = FALSE;
SchedPtr->PitBaseAddr = PitBaseAddr;
SchedPtr->Tick = 0U;
XPfw_Write32(SchedPtr->PitBaseAddr + PIT_CONTROL_OFFSET, 0U);
/* Successfully completed init */
Status = XST_SUCCESS;
} else {
/* Failed due to NULL pointer to Scheduler */
if (SchedPtr == NULL) {
Status = XST_FAILURE;
goto done;
}
return Status;
/* Disable all the tasks */
for (Idx = 0U; Idx < XPFW_SCHED_MAX_TASK; Idx++) {
SchedPtr->TaskList[Idx].Interval = 0U;
SchedPtr->TaskList[Idx].Callback = NULL;
SchedPtr->TaskList[Idx].Status = XPFW_TASK_STATUS_DISABLED;
}
SchedPtr->Enabled = FALSE;
SchedPtr->PitBaseAddr = PitBaseAddr;
SchedPtr->Tick = 0U;
XPfw_Write32(SchedPtr->PitBaseAddr + PIT_CONTROL_OFFSET, 0U);
/* Successfully completed init */
Status = XST_SUCCESS;
done:
return Status;
}
XStatus XPfw_SchedulerStart(XPfw_Scheduler_t *SchedPtr)
{
XStatus Status;
if (SchedPtr != NULL) {
SchedPtr->Enabled = TRUE;
XPfw_Write32(SchedPtr->PitBaseAddr + PIT_PRELOAD_OFFSET,
COUNT_PER_TICK);
XPfw_Write32(SchedPtr->PitBaseAddr + PIT_CONTROL_OFFSET, 3U);
Status = XST_SUCCESS;
} else {
if (SchedPtr == NULL) {
Status = XST_FAILURE;
goto done;
}
SchedPtr->Enabled = TRUE;
XPfw_Write32(SchedPtr->PitBaseAddr + PIT_PRELOAD_OFFSET,
COUNT_PER_TICK);
XPfw_Write32(SchedPtr->PitBaseAddr + PIT_CONTROL_OFFSET, 3U);
Status = XST_SUCCESS;
done:
return Status;
}
XStatus XPfw_SchedulerStop(XPfw_Scheduler_t *SchedPtr)
{
SchedPtr->Enabled =FALSE;
@ -104,85 +107,91 @@ XStatus XPfw_SchedulerStop(XPfw_Scheduler_t *SchedPtr)
void XPfw_SchedulerTickHandler(XPfw_Scheduler_t *SchedPtr)
{
u32 Idx;
/* TODO: Add check to detect task misses */
SchedPtr->Tick++;
for (Idx = 0U; Idx < XPFW_SCHED_MAX_TASK; Idx++) {
/* Check if it this task can be triggered */
if ((0U != SchedPtr->TaskList[Idx].Interval) &&
(NULL != SchedPtr->TaskList[Idx].Callback) &&
(0U == (SchedPtr->Tick % SchedPtr->TaskList[Idx].Interval))) {
/* Mark the Task as TRIGGERED */
SchedPtr->TaskList[Idx].Status = XPFW_TASK_STATUS_TRIGGERED;
}
}
}
XStatus XPfw_SchedulerProcess(const XPfw_Scheduler_t *SchedPtr)
XStatus XPfw_SchedulerProcess(XPfw_Scheduler_t *SchedPtr)
{
u32 Idx;
XStatus Status;
u32 CallCount = 0U;
for (Idx = 0U; Idx < XPFW_SCHED_MAX_TASK; Idx++) {
/* Check if it is valid event */
if ((0U != SchedPtr->TaskList[Idx].Interval)
&& (NULL != SchedPtr->TaskList[Idx].Callback)) {
/* Check if it has triggered */
if (0U == (SchedPtr->Tick % SchedPtr->TaskList[Idx].Interval)) {
/* Execute the Task */
SchedPtr->TaskList[Idx].Callback();
CallCount++;
}
/* Check if the task is triggered and has a valid Callback */
if ((XPFW_TASK_STATUS_TRIGGERED == SchedPtr->TaskList[Idx].Status) &&
(NULL != SchedPtr->TaskList[Idx].Callback)) {
/* Execute the Task */
SchedPtr->TaskList[Idx].Callback();
/* Disable the executed Task */
SchedPtr->TaskList[Idx].Status = XPFW_TASK_STATUS_DISABLED;
CallCount++;
}
}
//fw_printf("%s: %d Tasks were triggered\r\n", __func__, CallCount);
if (CallCount > 0U) {
Status = XST_SUCCESS;
} else {
/* Failed because non of the tasks were triggered */
/* Failed because none of the tasks were triggered */
Status = XST_FAILURE;
}
return Status;
}
XStatus XPfw_SchedulerAddTask(XPfw_Scheduler_t *SchedPtr, u32 OwnerId,u32 MilliSeconds, XPfw_Callback_t Callback)
{
u32 Idx;
XStatus Status;
/* Get the Next Free Task Index */
for(Idx=0U;Idx < XPFW_SCHED_MAX_TASK;Idx++){
if( 0U == SchedPtr->TaskList[Idx].Interval){
for (Idx=0U;Idx < XPFW_SCHED_MAX_TASK;Idx++) {
if (0U == SchedPtr->TaskList[Idx].Interval) {
break;
}
}
/* Check if we have reached Max Task limit */
if(XPFW_SCHED_MAX_TASK == Idx){
if (XPFW_SCHED_MAX_TASK == Idx) {
Status = XST_FAILURE;
}
else{
/* Add Interval as a factor of TICK_MILLISECONDS */
SchedPtr->TaskList[Idx].Interval = MilliSeconds/TICK_MILLISECONDS;
SchedPtr->TaskList[Idx].OwnerId = OwnerId;
SchedPtr->TaskList[Idx].Callback = Callback;
Status = XST_SUCCESS;
goto done;
}
/* Add Interval as a factor of TICK_MILLISECONDS */
SchedPtr->TaskList[Idx].Interval = MilliSeconds/TICK_MILLISECONDS;
SchedPtr->TaskList[Idx].OwnerId = OwnerId;
SchedPtr->TaskList[Idx].Callback = Callback;
Status = XST_SUCCESS;
done:
return Status;
}
XStatus XPfw_SchedulerRemoveTask(XPfw_Scheduler_t *SchedPtr, u32 OwnerId, u32 MilliSeconds, XPfw_Callback_t Callback)
{
u32 Idx;
u32 TaskCount = 0;
/*Find the Task Index */
for (Idx = 0U; Idx < XPFW_SCHED_MAX_TASK; Idx++) {
if ((Callback == SchedPtr->TaskList[Idx].Callback)
&& (SchedPtr->TaskList[Idx].OwnerId == OwnerId)) {
/* Disable task with given Milliseconds param or ALL if Milliseconds=0 */
if ((SchedPtr->TaskList[Idx].Interval == MilliSeconds)
|| (0U == MilliSeconds)) {
SchedPtr->TaskList[Idx].Interval = 0U;
SchedPtr->TaskList[Idx].OwnerId = 0U;
SchedPtr->TaskList[Idx].Callback = NULL;
TaskCount++;
}
if ((Callback == SchedPtr->TaskList[Idx].Callback) &&
(SchedPtr->TaskList[Idx].OwnerId == OwnerId) &&
((SchedPtr->TaskList[Idx].Interval == MilliSeconds) ||
(0U == MilliSeconds))) {
SchedPtr->TaskList[Idx].Interval = 0U;
SchedPtr->TaskList[Idx].OwnerId = 0U;
SchedPtr->TaskList[Idx].Callback = NULL;
TaskCount++;
}
}

10
lib/sw_apps/zynqmp_pmufw/src/xpfw_scheduler.h
View file

@ -1,5 +1,4 @@
/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
@ -27,23 +26,25 @@
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#ifndef XPFW_SCHEDULER_H_
#define XPFW_SCHEDULER_H_
#include "xpfw_default.h"
#define XPFW_SCHED_MAX_TASK 10U
/* Values for TaskPtr->Status */
#define XPFW_TASK_STATUS_TRIGGERED 0x5AFEC0C0U
#define XPFW_TASK_STATUS_DISABLED 0x00000000U
typedef void (*XPfw_Callback_t) (void);
struct XPfw_Task_t{
u32 Interval;
u32 OwnerId;
u32 Status;
XPfw_Callback_t Callback;
};
@ -55,12 +56,11 @@ typedef struct {
u32 Enabled;
} XPfw_Scheduler_t ;
void XPfw_SchedulerTickHandler(XPfw_Scheduler_t *SchedPtr);
XStatus XPfw_SchedulerInit(XPfw_Scheduler_t *SchedPtr, u32 PitBaseAddr);
XStatus XPfw_SchedulerStart(XPfw_Scheduler_t *SchedPtr);
XStatus XPfw_SchedulerStop(XPfw_Scheduler_t *SchedPtr);
XStatus XPfw_SchedulerProcess(const XPfw_Scheduler_t *SchedPtr);
XStatus XPfw_SchedulerProcess(XPfw_Scheduler_t *SchedPtr);
XStatus XPfw_SchedulerAddTask(XPfw_Scheduler_t *SchedPtr, u32 OwnerId,u32 MilliSeconds, XPfw_Callback_t Callback);
XStatus XPfw_SchedulerRemoveTask(XPfw_Scheduler_t *SchedPtr, u32 OwnerId, u32 MilliSeconds, XPfw_Callback_t Callback);

192
lib/sw_apps/zynqmp_pmufw/src/xpfw_user_startup.c
View file

@ -1,6 +1,5 @@
/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -27,10 +26,8 @@
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#include "xpfw_config.h"
#include "xpfw_core.h"
@ -46,29 +43,13 @@
#include "ipi_buffer.h"
#include "pm_defs.h"
#ifdef ENABLE_SCHEDULER
void PrintMsg1(void)
{
fw_printf("Task#1\r\n");
}
void PrintMsg2(void)
{
fw_printf("Task#2\r\n");
}
#endif
#ifdef ENABLE_PM
static void PmIpiHandler(const XPfw_Module_t *ModPtr, u32 IpiNum, u32 SrcMask)
{
u32 isrVal, apiId;
XPfw_PmIpiStatus ipiStatus;
switch(IpiNum) {
switch (IpiNum) {
case 0:
isrVal = XPfw_Read32(IPI_PMU_0_ISR);
fw_printf("Received IPI Mask:0x%08x\r\n", isrVal);
@ -76,11 +57,11 @@ static void PmIpiHandler(const XPfw_Module_t *ModPtr, u32 IpiNum, u32 SrcMask)
if (XPFW_PM_IPI_IS_PM_CALL == ipiStatus) {
/* Power management API processing */
XPfw_PmIpiHandler(isrVal, apiId);
}
else {
} else {
fw_printf("MOD-%d: Non-PM IPI-%d call received\r\n", ModPtr->ModId, IpiNum);
}
XPfw_Write32(IPI_PMU_0_ISR, isrVal);
XPfw_Write32(IPI_PMU_0_ISR, isrVal);
break;
case 1:
@ -100,34 +81,30 @@ static void PmIpiHandler(const XPfw_Module_t *ModPtr, u32 IpiNum, u32 SrcMask)
default:
fw_printf("ERROR: Invalid IPI Number: %d\r\n", IpiNum);
}
}
void PmEventHandler(const XPfw_Module_t *ModPtr, u32 EventId)
static void PmEventHandler(const XPfw_Module_t *ModPtr, u32 EventId)
{
u32 EvType, RegValue;
EvType = XPfw_EventGetType(EventId);
switch (EvType) {
case XPFW_EV_TYPE_GPI1:
RegValue = XPfw_EventGetRegMask(EventId);
XPfw_PmWakeHandler(RegValue);
break;
case XPFW_EV_TYPE_GPI2:
RegValue = XPfw_EventGetRegMask(EventId);
XPfw_PmWfiHandler(RegValue);
break;
default:
fw_printf("Unhandled PM Event: %d\r\n", EventId);
case XPFW_EV_TYPE_GPI1:
RegValue = XPfw_EventGetRegMask(EventId);
XPfw_PmWakeHandler(RegValue);
break;
case XPFW_EV_TYPE_GPI2:
RegValue = XPfw_EventGetRegMask(EventId);
XPfw_PmWfiHandler(RegValue);
break;
default:
fw_printf("Unhandled PM Event: %d\r\n", EventId);
break;
}
}
void PmCfgInit(const XPfw_Module_t *ModPtr, const u32 *CfgData, u32 Len)
static void PmCfgInit(const XPfw_Module_t *ModPtr, const u32 *CfgData, u32 Len)
{
/* Add Event Handlers for PM */
XPfw_CoreRegisterEvent(ModPtr, XPFW_EV_ACPU_0_WAKE);
@ -163,10 +140,20 @@ void PmCfgInit(const XPfw_Module_t *ModPtr, const u32 *CfgData, u32 Len)
*/
XPfw_PmInit();
}
#endif
static void ModPmInit(void)
{
const XPfw_Module_t *PmModPtr = XPfw_CoreCreateMod();
(void)XPfw_CoreSetCfgHandler(PmModPtr, PmCfgInit);
(void)XPfw_CoreSetEventHandler(PmModPtr, PmEventHandler);
(void)XPfw_CoreSetIpiHandler(PmModPtr, PmIpiHandler, 0U);
}
#else /* ENABLE_PM */
static void ModPmInit(void) { }
#endif /* ENABLE_PM */
#ifdef ENABLE_EM
void EmEventHandler(const XPfw_Module_t *ModPtr, u32 EventId)
static void EmEventHandler(const XPfw_Module_t *ModPtr, u32 EventId)
{
switch (EventId) {
case XPFW_EV_ERROR_1:
@ -179,104 +166,91 @@ void EmEventHandler(const XPfw_Module_t *ModPtr, u32 EventId)
fw_printf("EM:Unhandled Event(ID:%d)\r\n", EventId);
break;
}
}
void EmCfgInit(const XPfw_Module_t *ModPtr, const u32 *CfgData, u32 Len)
static void EmCfgInit(const XPfw_Module_t *ModPtr, const u32 *CfgData, u32 Len)
{
(void)XPfw_CoreRegisterEvent(ModPtr,XPFW_EV_ERROR_1);
(void)XPfw_CoreRegisterEvent(ModPtr,XPFW_EV_ERROR_2);
(void)XPfw_CoreRegisterEvent(ModPtr, XPFW_EV_ERROR_1);
(void)XPfw_CoreRegisterEvent(ModPtr, XPFW_EV_ERROR_2);
XPfw_ErrorHandlerInit();
fw_printf("EM (MOD-%d): Initialized.\r\n", ModPtr->ModId);
}
#endif
static void ModEmInit(void)
{
const XPfw_Module_t *EmModPtr = XPfw_CoreCreateMod();
(void)XPfw_CoreSetCfgHandler(EmModPtr, EmCfgInit);
(void)XPfw_CoreSetEventHandler(EmModPtr, EmEventHandler);
}
#else /* ENABLE_EM */
static void ModEmInit(void) { }
#endif /* ENABLE_EM */
#ifdef ENABLE_RTC_TEST
void RtcEventHandler(const XPfw_Module_t *ModPtr, u32 EventId)
static void RtcEventHandler(const XPfw_Module_t *ModPtr, u32 EventId)
{
fw_printf("MOD%d:EVENTID: %d\r\n", ModPtr->ModId, EventId);
//XPfw_CorePrintStats();
if(XPFW_EV_RTC_SECONDS == EventId){
if (XPFW_EV_RTC_SECONDS == EventId) {
/* Ack the Int in RTC Module */
Xil_Out32(RTC_RTC_INT_STATUS,1U);
Xil_Out32(RTC_RTC_INT_STATUS, 1U);
fw_printf("RTC: %d \r\n", Xil_In32(RTC_CURRENT_TIME));
}
}
void RtcCfgInit(const XPfw_Module_t *ModPtr, const u32 *CfgData, u32 Len)
static void RtcCfgInit(const XPfw_Module_t *ModPtr, const u32 *CfgData, u32 Len)
{
XPfw_CoreRegisterEvent(ModPtr,XPFW_EV_RTC_SECONDS);
XPfw_CoreRegisterEvent(ModPtr, XPFW_EV_RTC_SECONDS);
/* Enable Seconds Alarm */
Xil_Out32(RTC_RTC_INT_EN,1U);
Xil_Out32(RTC_RTC_INT_STATUS,1U);
Xil_Out32(RTC_RTC_INT_EN, 1U);
Xil_Out32(RTC_RTC_INT_STATUS, 1U);
fw_printf("RTC (MOD-%d): Initialized.\r\n", ModPtr->ModId);
}
static void ModRtcInit(void)
{
const XPfw_Module_t *RtcModPtr = XPfw_CoreCreateMod();
#endif
(void)XPfw_CoreSetCfgHandler(RtcModPtr, RtcCfgInit);
(void)XPfw_CoreSetEventHandler(RtcModPtr, RtcEventHandler);
}
#else /* ENABLE_RTC_TEST */
static void ModRtcInit(void) { }
#endif /* ENABLE_RTC_TEST */
#ifdef ENABLE_SCHEDULER
void SchCfgInit(const XPfw_Module_t *ModPtr, const u32 *CfgData, u32 Len)
static void PrintMsg1(void)
{
fw_printf("Task#1\r\n");
}
static void PrintMsg2(void)
{
fw_printf("Task#2\r\n");
}
static void SchCfgInit(const XPfw_Module_t *ModPtr, const u32 *CfgData, u32 Len)
{
/* Task every 5 seconds - For our convenience in manual testing */
fw_printf("Adding Task1 - Status: %d\n", XPfw_CoreScheduleTask(ModPtr,5000U, PrintMsg1));
fw_printf("Adding Task1 - Status: %d\n", XPfw_CoreScheduleTask(ModPtr, 5000U, PrintMsg1));
/* Every 10 seconds */
fw_printf("Adding Task2 - Status:%d\n", XPfw_CoreScheduleTask(ModPtr,10000U, PrintMsg2));
fw_printf("Adding Task2 - Status:%d\n", XPfw_CoreScheduleTask(ModPtr, 10000U, PrintMsg2));
}
#endif
static XStatus ModSchInit(void)
{
const XPfw_Module_t *SchModPtr = XPfw_CoreCreateMod();
return XPfw_CoreSetCfgHandler(SchModPtr, SchCfgInit);
}
#else /* ENABLE_SCHEDULER */
static void ModSchInit(void) { }
#endif /* ENABLE_SCHEDULER */
void XPfw_UserStartUp(void)
{
#ifdef ENABLE_PM
const XPfw_Module_t *PmModPtr;
#endif
#ifdef ENABLE_RTC_TEST
const XPfw_Module_t *RtcModPtr;
#endif
#ifdef ENABLE_EM
const XPfw_Module_t *EmModPtr;
#endif
#ifdef ENABLE_SCHEDULER
const XPfw_Module_t *SchModPtr;
#endif
#ifdef ENABLE_RTC_TEST
RtcModPtr = XPfw_CoreCreateMod();
(void)XPfw_CoreSetCfgHandler(RtcModPtr,RtcCfgInit);
(void)XPfw_CoreSetEventHandler(RtcModPtr,RtcEventHandler);
#endif
#ifdef ENABLE_EM
EmModPtr = XPfw_CoreCreateMod();
(void)XPfw_CoreSetCfgHandler(EmModPtr,EmCfgInit);
(void)XPfw_CoreSetEventHandler(EmModPtr,EmEventHandler);
#endif
#ifdef ENABLE_PM
PmModPtr = XPfw_CoreCreateMod();
(void)XPfw_CoreSetCfgHandler(PmModPtr,PmCfgInit);
(void)XPfw_CoreSetEventHandler(PmModPtr,PmEventHandler);
(void)XPfw_CoreSetIpiHandler(PmModPtr,PmIpiHandler,0U);
#endif
#ifdef ENABLE_SCHEDULER
SchModPtr = XPfw_CoreCreateMod();
(void)XPfw_CoreSetCfgHandler(SchModPtr,SchCfgInit);
#endif
ModRtcInit();
ModEmInit();
ModPmInit();
(void)ModSchInit();
}

5
lib/sw_apps/zynqmp_pmufw/src/xpfw_user_startup.h
View file

@ -1,6 +1,5 @@
/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -27,10 +26,8 @@
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#ifndef XPFW_USER_STARTUP_H_
#define XPFW_USER_STARTUP_H_

6
lib/sw_apps/zynqmp_pmufw/src/xpfw_version.h
View file

@ -1,4 +1,4 @@
#ifndef ZYNQMP_XPFW_VERSION__H_
#define ZYNQMP_XPFW_VERSION__H_
#define ZYNQMP_XPFW_VERSION "51ced25"
#endif
#define ZYNQMP_XPFW_VERSION__H_
#define ZYNQMP_XPFW_VERSION "rc1-00006-gdc6ab46"
#endif