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trafficgen: 64-bit support

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Add 64-bit support for traffic generator.

Signed-off-by: Shubhrajyoti Datta <shubhraj@xilinx.com>
Reviewed-by: Kedareswara rao Appana <appanad@xilinx.com>
This commit is contained in:
Shubhrajyoti Datta 2015-08-19 18:51:44 +05:30 • committed by Nava kishore Manne
parent ed4a66f256
commit 6fd0d9fb68
6 changed files with 81 additions and 10 deletions
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2
XilinxProcessorIPLib/drivers/trafgen/data/trafgen.mdd
View file

@ -37,7 +37,7 @@ BEGIN driver trafgen
OPTION supported_peripherals = (axi_traffic_gen_v[2-9]_[0-9][0-9]_[a-z] axi_traffic_gen_v[2-9]_[0-9]);
OPTION driver_state = ACTIVE;
OPTION copyfiles = all;
OPTION VERSION = 3.2;
OPTION VERSION = 4.0;
OPTION NAME = trafgen;
END driver

12
XilinxProcessorIPLib/drivers/trafgen/data/trafgen.tcl
View file

@ -56,6 +56,7 @@ set periph_ninstances_atg 0
set atg_mode_value 0
set atg_mode_value_l2 0
set axi_mode_value 0
set address_width_value 0
set baseaddr_value 0
set highaddr_value 0
@ -113,6 +114,7 @@ proc xdfeine_trafgen_params_constants { periph } {
global atg_mode_value_l2
global axi_mode_value
global baseaddr_value
global address_width_value
global highaddr_value
set atg_mode_name [::hsi::utils::get_param_value $periph C_ATG_MODE]
@ -174,6 +176,10 @@ proc xdfeine_trafgen_params_constants { periph } {
if {[llength $baseaddr_value] == 0} {
set baseaddr_value 0
}
set address_width_value [::hsi::utils::get_param_value $periph C_EXTENDED_ADDRESS_WIDTH]
if {[llength $address_width_value] == 0} {
set address_width_value 0
}
set highaddr_value [::hsi::utils::get_param_value $periph C_HIGHADDR]
if {[llength $highaddr_value] == 0} {
set highaddr_value 0
@ -194,6 +200,7 @@ proc xdefine_trafgen_params_instance {file_handle periph device_id} {
puts $file_handle "\#define [::hsi::utils::get_ip_param_name $periph "C_ATG_MODE"] $atg_mode_value"
puts $file_handle "\#define [::hsi::utils::get_ip_param_name $periph "C_ATG_MODE_L2"] $atg_mode_value_l2"
puts $file_handle "\#define [::hsi::utils::get_ip_param_name $periph "C_AXIS_MODE"] $axi_mode_value"
puts $file_handle "\#define [::hsi::utils::get_ip_param_name $periph "C_EXTENDED_ADDRESS_WIDTH"] [::hsi::utils::get_param_value $periph C_EXTENDED_ADDRESS_WIDTH]"
}
proc xdefine_trafgen_params_canonical {file_handle periph device_id} {
@ -201,6 +208,7 @@ proc xdefine_trafgen_params_canonical {file_handle periph device_id} {
global atg_mode_value
global atg_mode_value_l2
global axi_mode_value
global address_width_value
global baseaddr_value
global highaddr_value
puts $file_handle "\n/* Canonical definitions for peripheral [string toupper [common::get_property NAME $periph]] */"
@ -230,6 +238,10 @@ proc xdefine_trafgen_params_canonical {file_handle periph device_id} {
set canonical_name [format "%s_AXIS_MODE" $canonical_tag]
puts $file_handle "\#define $canonical_name $axi_mode_value"
add_field_to_periph_config_struct_atg $device_id $canonical_name
set canonical_name [format "%s_EXTENDED_ADDRESS_WIDTH" $canonical_tag]
puts $file_handle "\#define $canonical_name $address_width_value"
add_field_to_periph_config_struct_atg $device_id $canonical_name
}
proc xdefine_trafgen_config_file {file_name drv_string} {

24
XilinxProcessorIPLib/drivers/trafgen/src/xtrafgen.c
View file

@ -116,7 +116,7 @@ static int XTrafGen_ProgramParamRam(XTrafGen *InstancePtr, u8 RdWrFlag);
*
*****************************************************************************/
int XTrafGen_CfgInitialize(XTrafGen * InstancePtr,
XTrafGen_Config *Config, u32 EffectiveAddress)
XTrafGen_Config *Config, UINTPTR EffectiveAddress)
{
u32 ConfigStatus;
@ -130,6 +130,7 @@ int XTrafGen_CfgInitialize(XTrafGen * InstancePtr,
memset(InstancePtr, 0, sizeof(XTrafGen));
InstancePtr->Config.BaseAddress = EffectiveAddress;
InstancePtr->Config.DeviceId = Config->DeviceId;
InstancePtr->Config.AddressWidth = Config->AddressWidth;
if((Config->BusType == 1) && (Config->Mode == 1 ||
Config->ModeType == 2)) {
@ -442,7 +443,13 @@ static void XTrafGen_PrepCmdWords(XTrafGen *InstancePtr,
Cmd = &CmdPtr->CRamCmd;
/* Command Word 0 */
CmdWords[0] = Cmd->Address;
if ( InstancePtr->Config.AddressWidth > 32) {
/* Command Word 4 */
CmdWords[0] = LOWER_32_BITS(Cmd->Address);
CmdWords[4] = UPPER_32_BITS(Cmd->Address);
} else {
CmdWords[0] = Cmd->Address;
}
/* Command Word 1 */
CmdWords[1] = 0;
@ -556,6 +563,7 @@ static int XTrafGen_ProgramCmdRam(XTrafGen *InstancePtr, u8 RdWrFlag)
u32 Index;
u32 Offset;
u32 CmdWordIndex;
u32 Offset1;
int ValidIndex;
/* Verify arguments */
@ -567,10 +575,12 @@ static int XTrafGen_ProgramCmdRam(XTrafGen *InstancePtr, u8 RdWrFlag)
EntryIndex = CmdInfo->WrIndex;
ValidIndex = CmdInfo->LastWrValidIndex;
Offset = XTG_CMD_RAM_BLOCK_SIZE;
Offset1 = XTG_EXTCMD_RAM_BLOCK_SIZE;
} else {
EntryIndex = CmdInfo->RdIndex;
ValidIndex = CmdInfo->LastRdValidIndex;
Offset = 0;
Offset1 = 0;
}
for (Index = 0; Index < EntryIndex; Index++) {
@ -582,6 +592,12 @@ static int XTrafGen_ProgramCmdRam(XTrafGen *InstancePtr, u8 RdWrFlag)
Offset, CmdWords[CmdWordIndex]);
Offset += 4;
}
if ( InstancePtr->Config.AddressWidth > 32) {
XTrafGen_WriteCmdRam_Msb(InstancePtr->Config.BaseAddress,
Offset1, CmdWords[4]);
Offset1 += 4;
}
} else {
return XST_FAILURE;
}
@ -671,7 +687,7 @@ void XTrafGen_PrintCmds(XTrafGen *InstancePtr)
xil_printf("Commands configured for Write Block: \n\r");
for (Index1 = 0; Index1 < MAX_NUM_ENTRIES; Index1++) {
xil_printf("Cmd%d:\t", Index1);
for (Index2 = 0; Index2 < 4; Index2++) {
for (Index2 = 0; Index2 < 5; Index2++) {
xil_printf("0x%08x, ",
CmdInfo->CmdEntry[1][Index1].CmdWords[Index2]);
}
@ -681,7 +697,7 @@ void XTrafGen_PrintCmds(XTrafGen *InstancePtr)
xil_printf("Commands configured for Read Block: \n\r");
for (Index1 = 0; Index1 < MAX_NUM_ENTRIES; Index1++) {
xil_printf("Cmd%d:\t", Index1);
for (Index2 = 0; Index2 < 4; Index2++) {
for (Index2 = 0; Index2 < 5; Index2++) {
xil_printf("0x%08x, ",
CmdInfo->CmdEntry[0][Index1].CmdWords[Index2]);
}

12
XilinxProcessorIPLib/drivers/trafgen/src/xtrafgen.h
View file

@ -191,6 +191,8 @@
* 3.2 adk 05/08/14 Fixed CR:798742 The last word of 8KB Master RAM in
* axi traffic generator can't access and CR:799554
* Some incorrect parameter in axi traffic generator driver.
* 4.0 sd 19/08/15 Fixed CR:876564 Added 64-bit Support to axi traffic generator
* driver.
* </pre>
******************************************************************************/
@ -235,6 +237,7 @@ extern "C" {
/* Internal RAM Sizes */
#define XTG_PRM_RAM_BLOCK_SIZE 0x400 /**< PARAM Block Size (1KB) */
#define XTG_CMD_RAM_BLOCK_SIZE 0x1000 /**< Cmd RAM Block Size (4KB) */
#define XTG_EXTCMD_RAM_BLOCK_SIZE 0x400 /**< Extended CMDRAM Block Size (1KB) */
#define XTG_PARAM_RAM_SIZE 0x800 /**< Parameter RAM (2KB) */
#define XTG_COMMAND_RAM_SIZE 0x2000 /**< Command RAM (8KB) */
#define XTG_MASTER_RAM_SIZE 0x2000 /**< Master RAM (8KB) */
@ -247,7 +250,7 @@ extern "C" {
*/
typedef struct XTrafGen_CRamCmd
{
u32 Address; /**< Address Driven to a*_addr line */
UINTPTR Address; /**< Address Driven to a*_addr line */
u32 ValidCmd; /**< Valid Command */
u32 LastAddress; /**< Last address */
u32 Prot; /**< Driven to a*_prot line */
@ -301,7 +304,7 @@ typedef struct XTrafGen_Cmd
*/
typedef struct XTrafGen_CmdEntry
{
u32 CmdWords[4]; /**< Command Ram words */
u32 CmdWords[5]; /**< Command Ram words */
u32 ParamWord; /**< Parameter Ram word */
} XTrafGen_CmdEntry;
@ -312,10 +315,11 @@ typedef struct XTrafGen_CmdEntry
*/
typedef struct XTrafGen_Config {
u16 DeviceId; /**< Device Id */
u32 BaseAddress; /**< Base Address */
UINTPTR BaseAddress; /**< Base Address */
u32 BusType; /**< Atgmode */
u32 Mode; /**< Atgmode_l2 */
u32 ModeType; /**< Axismode */
u32 AddressWidth; /**< AddressWidth */
} XTrafGen_Config;
/**
@ -1188,7 +1192,7 @@ typedef struct XTrafGen {
* Initialization and control functions in xtrafgen.c
*/
int XTrafGen_CfgInitialize(XTrafGen * InstancePtr,
XTrafGen_Config *Config, u32 EffectiveAddress);
XTrafGen_Config *Config, UINTPTR EffectiveAddress);
XTrafGen_Config *XTrafGen_LookupConfig(u32 DeviceId);
int XTrafGen_AddCommand(XTrafGen *InstancePtr, XTrafGen_Cmd *CmdPtr);
int XTrafGen_GetLastValidIndex(XTrafGen *InstancePtr, u32 RdWrFlag);

3
XilinxProcessorIPLib/drivers/trafgen/src/xtrafgen_g.c
View file

@ -67,7 +67,8 @@ XTrafGen_Config XTrafGen_ConfigTable[] =
XPAR_XTRAFGEN_0_BASEADDR,
XPAR_XTRAFGEN_0_ATG_MODE,
XPAR_XTRAFGEN_0_ATG_MODE_L2,
XPAR_XTRAFGEN_0_AXIS_MODE
XPAR_XTRAFGEN_0_AXIS_MODE,
XPAR_XTRAFGEN_0_ADDRESS_WIDTH
}
};
/** @} */

38
XilinxProcessorIPLib/drivers/trafgen/src/xtrafgen_hw.h
View file

@ -107,6 +107,7 @@ extern "C" {
#define XTG_PARAM_RAM_OFFSET 0x1000 /**< Parameter RAM Offset */
#define XTG_COMMAND_RAM_OFFSET 0x8000 /**< Command RAM Offset */
#define XTG_MASTER_RAM_OFFSET 0xC000 /**< Master RAM Offset */
#define XTG_COMMAND_RAM_MSB_OFFSET 0xa000 /**< Command RAM MSB Offset */
/*@}*/
@ -458,6 +459,23 @@ extern "C" {
/****************************************************************************/
/**
*
* XTrafGen_ReadCmdRam_Msb returns the value read from the Command RAM
* specified by <i>Offset</i>.
*
* @param BaseAddress is the MSB of base address of the Axi TrafGen device.
* @param Offset is the offset of the Command RAM to be read.
*
* @return Returns the 32-bit value of the memory location.
*
* @note C-style signature:
* u32 XTrafGen_ReadCmdRam_Msb(u32 BaseAddress, u32 Offset)
*
*****************************************************************************/
#define XTrafGen_ReadCmdRam_Msb(BaseAddress, Offset) \
(Xil_In32(((BaseAddress) + XTG_COMMAND_RAM_MSB_OFFSET + (Offset))))
/****************************************************************************/
/**
*
* XTrafGen_WriteCmdRam, writes <i>Data</i> to the Command RAM specified by
* <i>Offset</i>.
*
@ -475,6 +493,26 @@ extern "C" {
*****************************************************************************/
#define XTrafGen_WriteCmdRam(BaseAddress, Offset, Data) \
Xil_Out32(((BaseAddress) + XTG_COMMAND_RAM_OFFSET + (Offset)), (Data))
/****************************************************************************/
/**
*
* XTrafGen_WriteCmdRam_Msb, writes <i>Data</i> to the Command RAM specified by
* <i>Offset</i>.
*
* @param BaseAddress is the MSB of base address of the Axi TrafGen device.
* @param Offset is the offset of the location in Command RAM
* to be written.
* @param Data is the 32-bit value to write to the Command RAM.
*
* @return None.
*
* @note
* C-style signature:
* void XTrafGen_WriteCmdRam_Msb(u32 BaseAddress, u32 Offset, u32 Data)
*
*****************************************************************************/
#define XTrafGen_WriteCmdRam_Msb(BaseAddress, Offset, Data) \
Xil_Out32(((BaseAddress) + XTG_COMMAND_RAM_MSB_OFFSET + (Offset)), (Data))
/****************************************************************************/
/**