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uartps: Modified driver source code for MISRA-C:2012 compliance

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This patch modifies driver code according to misrac guidelines.

support for Zynq Ultrascale Mp added.

Signed-off-by: Vishnu Motghare <vishnum@xilinx.com>
This commit is contained in:
Vishnu Motghare 2014-12-09 21:16:43 +05:30 • committed by Nava kishore Manne
parent ae31a85612
commit 73a8484b60
9 changed files with 467 additions and 428 deletions
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185
XilinxProcessorIPLib/drivers/uartps/src/xuartps.c
View file

@ -62,7 +62,7 @@
* baud rate that will be generated using the specified clock and the * baud rate that will be generated using the specified clock and the
* desired baud rate. * desired baud rate.
*/ */
#define XUARTPS_MAX_BAUD_ERROR_RATE 3 /* max % error allowed */ #define XUARTPS_MAX_BAUD_ERROR_RATE 3U /* max % error allowed */
/**************************** Type Definitions ******************************/ /**************************** Type Definitions ******************************/
@ -73,11 +73,11 @@
/************************** Function Prototypes *****************************/ /************************** Function Prototypes *****************************/
static void XUartPs_StubHandler(void *CallBackRef, u32 Event, static void XUartPs_StubHandler(void *CallBackRef, u32 Event,
unsigned int ByteCount); u32 ByteCount);
unsigned int XUartPs_SendBuffer(XUartPs *InstancePtr); u32 XUartPs_SendBuffer(XUartPs *InstancePtr);
unsigned int XUartPs_ReceiveBuffer(XUartPs *InstancePtr); u32 XUartPs_ReceiveBuffer(XUartPs *InstancePtr);
/************************** Variable Definitions ****************************/ /************************** Variable Definitions ****************************/
@ -123,10 +123,10 @@ unsigned int XUartPs_ReceiveBuffer(XUartPs *InstancePtr);
* All interrupts are disabled. * All interrupts are disabled.
* *
*****************************************************************************/ *****************************************************************************/
int XUartPs_CfgInitialize(XUartPs *InstancePtr, s32 XUartPs_CfgInitialize(XUartPs *InstancePtr,
XUartPs_Config * Config, u32 EffectiveAddr) XUartPs_Config * Config, u32 EffectiveAddr)
{ {
int Status; s32 Status;
u32 ModeRegister; u32 ModeRegister;
u32 BaudRate; u32 BaudRate;
@ -149,12 +149,12 @@ int XUartPs_CfgInitialize(XUartPs *InstancePtr,
InstancePtr->Handler = XUartPs_StubHandler; InstancePtr->Handler = XUartPs_StubHandler;
InstancePtr->SendBuffer.NextBytePtr = NULL; InstancePtr->SendBuffer.NextBytePtr = NULL;
InstancePtr->SendBuffer.RemainingBytes = 0; InstancePtr->SendBuffer.RemainingBytes = 0U;
InstancePtr->SendBuffer.RequestedBytes = 0; InstancePtr->SendBuffer.RequestedBytes = 0U;
InstancePtr->ReceiveBuffer.NextBytePtr = NULL; InstancePtr->ReceiveBuffer.NextBytePtr = NULL;
InstancePtr->ReceiveBuffer.RemainingBytes = 0; InstancePtr->ReceiveBuffer.RemainingBytes = 0U;
InstancePtr->ReceiveBuffer.RequestedBytes = 0; InstancePtr->ReceiveBuffer.RequestedBytes = 0U;
/* /*
* Flag that the driver instance is ready to use * Flag that the driver instance is ready to use
@ -165,59 +165,60 @@ int XUartPs_CfgInitialize(XUartPs *InstancePtr,
* Set the default baud rate here, can be changed prior to * Set the default baud rate here, can be changed prior to
* starting the device * starting the device
*/ */
BaudRate = XUARTPS_DFT_BAUDRATE; BaudRate = (u32)XUARTPS_DFT_BAUDRATE;
Status = XUartPs_SetBaudRate(InstancePtr, BaudRate); Status = XUartPs_SetBaudRate(InstancePtr, BaudRate);
if (Status != XST_SUCCESS) { if (Status != (s32)XST_SUCCESS) {
InstancePtr->IsReady = 0; InstancePtr->IsReady = 0U;
return Status; } else {
/*
* Set up the default data format: 8 bit data, 1 stop bit, no
* parity
*/
ModeRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
XUARTPS_MR_OFFSET);
/*
* Mask off what's already there
*/
ModeRegister &= (~((u32)XUARTPS_MR_CHARLEN_MASK |
(u32)XUARTPS_MR_STOPMODE_MASK |
(u32)XUARTPS_MR_PARITY_MASK));
/*
* Set the register value to the desired data format
*/
ModeRegister |= ((u32)XUARTPS_MR_CHARLEN_8_BIT |
(u32)XUARTPS_MR_STOPMODE_1_BIT |
(u32)XUARTPS_MR_PARITY_NONE);
/*
* Write the mode register out
*/
XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
ModeRegister);
/*
* Set the RX FIFO trigger at 8 data bytes.
*/
XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
XUARTPS_RXWM_OFFSET, 0x08U);
/*
* Set the RX timeout to 1, which will be 4 character time
*/
XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
XUARTPS_RXTOUT_OFFSET, 0x01U);
/*
* Disable all interrupts, polled mode is the default
*/
XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
XUARTPS_IXR_MASK);
Status = XST_SUCCESS;
} }
return Status;
/*
* Set up the default data format: 8 bit data, 1 stop bit, no
* parity
*/
ModeRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
XUARTPS_MR_OFFSET);
/*
* Mask off what's already there
*/
ModeRegister &= ~(XUARTPS_MR_CHARLEN_MASK |
XUARTPS_MR_STOPMODE_MASK |
XUARTPS_MR_PARITY_MASK);
/*
* Set the register value to the desired data format
*/
ModeRegister |= (XUARTPS_MR_CHARLEN_8_BIT |
XUARTPS_MR_STOPMODE_1_BIT |
XUARTPS_MR_PARITY_NONE);
/*
* Write the mode register out
*/
XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
ModeRegister);
/*
* Set the RX FIFO trigger at 8 data bytes.
*/
XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
XUARTPS_RXWM_OFFSET, 0x08);
/*
* Set the RX timeout to 1, which will be 4 character time
*/
XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
XUARTPS_RXTOUT_OFFSET, 0x01);
/*
* Disable all interrupts, polled mode is the default
*/
XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
XUARTPS_IXR_MASK);
return XST_SUCCESS;
} }
/****************************************************************************/ /****************************************************************************/
@ -254,10 +255,10 @@ int XUartPs_CfgInitialize(XUartPs *InstancePtr,
* <br><br> * <br><br>
* *
*****************************************************************************/ *****************************************************************************/
unsigned int XUartPs_Send(XUartPs *InstancePtr, u8 *BufferPtr, u32 XUartPs_Send(XUartPs *InstancePtr, u8 *BufferPtr,
unsigned int NumBytes) u32 NumBytes)
{ {
unsigned int BytesSent; u32 BytesSent;
/* /*
* Asserts validate the input arguments * Asserts validate the input arguments
@ -320,10 +321,10 @@ unsigned int XUartPs_Send(XUartPs *InstancePtr, u8 *BufferPtr,
* with a value of zero to stop an operation that is already in progress. * with a value of zero to stop an operation that is already in progress.
* *
*****************************************************************************/ *****************************************************************************/
unsigned int XUartPs_Recv(XUartPs *InstancePtr, u32 XUartPs_Recv(XUartPs *InstancePtr,
u8 *BufferPtr, unsigned int NumBytes) u8 *BufferPtr, u32 NumBytes)
{ {
unsigned int ReceivedCount; u32 ReceivedCount;
u32 ImrRegister; u32 ImrRegister;
/* /*
@ -391,9 +392,9 @@ unsigned int XUartPs_Recv(XUartPs *InstancePtr,
* @note None. * @note None.
* *
*****************************************************************************/ *****************************************************************************/
unsigned int XUartPs_SendBuffer(XUartPs *InstancePtr) u32 XUartPs_SendBuffer(XUartPs *InstancePtr)
{ {
unsigned int SentCount = 0; u32 SentCount = 0U;
u32 ImrRegister; u32 ImrRegister;
/* /*
@ -409,11 +410,11 @@ unsigned int XUartPs_SendBuffer(XUartPs *InstancePtr)
*/ */
XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
XUARTPS_FIFO_OFFSET, XUARTPS_FIFO_OFFSET,
InstancePtr->SendBuffer. ((u32)InstancePtr->SendBuffer.
NextBytePtr[SentCount]); NextBytePtr[SentCount]));
/* /*
* Incriment the send count. * Increment the send count.
*/ */
SentCount++; SentCount++;
} }
@ -432,13 +433,13 @@ unsigned int XUartPs_SendBuffer(XUartPs *InstancePtr)
ImrRegister = ImrRegister =
XUartPs_ReadReg(InstancePtr->Config.BaseAddress, XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
XUARTPS_IMR_OFFSET); XUARTPS_IMR_OFFSET);
if ((ImrRegister & XUARTPS_IXR_RXFULL) || if (((ImrRegister & XUARTPS_IXR_RXFULL) != (u32)0) ||
(ImrRegister & XUARTPS_IXR_RXEMPTY) || ((ImrRegister & XUARTPS_IXR_RXEMPTY) != (u32)0)||
(ImrRegister & XUARTPS_IXR_RXOVR)) { ((ImrRegister & XUARTPS_IXR_RXOVR) != (u32)0)) {
XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
XUARTPS_IER_OFFSET, XUARTPS_IER_OFFSET,
ImrRegister | XUARTPS_IXR_TXEMPTY); ImrRegister | (u32)XUARTPS_IXR_TXEMPTY);
} }
return SentCount; return SentCount;
@ -473,10 +474,10 @@ unsigned int XUartPs_SendBuffer(XUartPs *InstancePtr)
* @note None. * @note None.
* *
*****************************************************************************/ *****************************************************************************/
unsigned int XUartPs_ReceiveBuffer(XUartPs *InstancePtr) u32 XUartPs_ReceiveBuffer(XUartPs *InstancePtr)
{ {
u32 CsrRegister; u32 CsrRegister;
unsigned int ReceivedCount = 0; u32 ReceivedCount = 0U;
/* /*
* Read the Channel Status Register to determine if there is any data in * Read the Channel Status Register to determine if there is any data in
@ -490,7 +491,7 @@ unsigned int XUartPs_ReceiveBuffer(XUartPs *InstancePtr)
* number of bytes has been received * number of bytes has been received
*/ */
while((ReceivedCount < InstancePtr->ReceiveBuffer.RemainingBytes)&& while((ReceivedCount < InstancePtr->ReceiveBuffer.RemainingBytes)&&
(0 == (CsrRegister & XUARTPS_SR_RXEMPTY))){ (((CsrRegister & XUARTPS_SR_RXEMPTY) == (u32)0))){
InstancePtr->ReceiveBuffer.NextBytePtr[ReceivedCount] = InstancePtr->ReceiveBuffer.NextBytePtr[ReceivedCount] =
XUartPs_ReadReg(InstancePtr->Config. XUartPs_ReadReg(InstancePtr->Config.
@ -507,7 +508,9 @@ unsigned int XUartPs_ReceiveBuffer(XUartPs *InstancePtr)
* Update the receive buffer to reflect the number of bytes just * Update the receive buffer to reflect the number of bytes just
* received * received
*/ */
InstancePtr->ReceiveBuffer.NextBytePtr += ReceivedCount; if(InstancePtr->ReceiveBuffer.NextBytePtr != NULL){
InstancePtr->ReceiveBuffer.NextBytePtr += ReceivedCount;
}
InstancePtr->ReceiveBuffer.RemainingBytes -= ReceivedCount; InstancePtr->ReceiveBuffer.RemainingBytes -= ReceivedCount;
return ReceivedCount; return ReceivedCount;
@ -532,15 +535,15 @@ unsigned int XUartPs_ReceiveBuffer(XUartPs *InstancePtr)
* @note None. * @note None.
* *
*****************************************************************************/ *****************************************************************************/
int XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate) s32 XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate)
{ {
u8 IterBAUDDIV; /* Iterator for available baud divisor values */ u32 IterBAUDDIV; /* Iterator for available baud divisor values */
u32 BRGR_Value; /* Calculated value for baud rate generator */ u32 BRGR_Value; /* Calculated value for baud rate generator */
u32 CalcBaudRate; /* Calculated baud rate */ u32 CalcBaudRate; /* Calculated baud rate */
u32 BaudError; /* Diff between calculated and requested baud rate */ u32 BaudError; /* Diff between calculated and requested baud rate */
u32 Best_BRGR = 0; /* Best value for baud rate generator */ u32 Best_BRGR = 0U; /* Best value for baud rate generator */
u8 Best_BAUDDIV = 0; /* Best value for baud divisor */ u8 Best_BAUDDIV = 0U; /* Best value for baud divisor */
u32 Best_Error = 0xFFFFFFFF; u32 Best_Error = 0xFFFFFFFFU;
u32 PercentError; u32 PercentError;
u32 ModeReg; u32 ModeReg;
u32 InputClk; u32 InputClk;
@ -550,8 +553,8 @@ int XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate)
*/ */
Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(BaudRate <= XUARTPS_MAX_RATE); Xil_AssertNonvoid(BaudRate <= (u32)XUARTPS_MAX_RATE);
Xil_AssertNonvoid(BaudRate >= XUARTPS_MIN_RATE); Xil_AssertNonvoid(BaudRate >= (u32)XUARTPS_MIN_RATE);
/* /*
* Make sure the baud rate is not impossilby large. * Make sure the baud rate is not impossilby large.
@ -660,9 +663,9 @@ int XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate)
* *
*****************************************************************************/ *****************************************************************************/
static void XUartPs_StubHandler(void *CallBackRef, u32 Event, static void XUartPs_StubHandler(void *CallBackRef, u32 Event,
unsigned int ByteCount) u32 ByteCount)
{ {
(void) CallBackRef; (void *) CallBackRef;
(void) Event; (void) Event;
(void) ByteCount; (void) ByteCount;
/* /*

119
XilinxProcessorIPLib/drivers/uartps/src/xuartps.h
View file

@ -152,6 +152,8 @@
* 2.1 hk 04/16/14 Change XUARTPS_MAX_RATE to 921600. CR# 780625. * 2.1 hk 04/16/14 Change XUARTPS_MAX_RATE to 921600. CR# 780625.
* 2.2 hk 06/23/14 SW reset of RX and TX should be done when changing * 2.2 hk 06/23/14 SW reset of RX and TX should be done when changing
* baud rate. CR# 804281. * baud rate. CR# 804281.
* 3.0 vm 12/09/14 Modified source code according to misrac guideline.
* Support for Zynq Ultrascale Mp added.
* *
* </pre> * </pre>
* *
@ -178,10 +180,10 @@ extern "C" {
* numbers are based only on the testing that has been done. The hardware * numbers are based only on the testing that has been done. The hardware
* is capable of other baud rates. * is capable of other baud rates.
*/ */
#define XUARTPS_MAX_RATE 921600 #define XUARTPS_MAX_RATE 921600U
#define XUARTPS_MIN_RATE 110 #define XUARTPS_MIN_RATE 110U
#define XUARTPS_DFT_BAUDRATE 115200 /* Default baud rate */ #define XUARTPS_DFT_BAUDRATE 115200U /* Default baud rate */
/** @name Configuration options /** @name Configuration options
* @{ * @{
@ -194,14 +196,14 @@ extern "C" {
* *
*/ */
#define XUARTPS_OPTION_SET_BREAK 0x0080 /**< Starts break transmission */ #define XUARTPS_OPTION_SET_BREAK 0x0080U /**< Starts break transmission */
#define XUARTPS_OPTION_STOP_BREAK 0x0040 /**< Stops break transmission */ #define XUARTPS_OPTION_STOP_BREAK 0x0040U /**< Stops break transmission */
#define XUARTPS_OPTION_RESET_TMOUT 0x0020 /**< Reset the receive timeout */ #define XUARTPS_OPTION_RESET_TMOUT 0x0020U /**< Reset the receive timeout */
#define XUARTPS_OPTION_RESET_TX 0x0010 /**< Reset the transmitter */ #define XUARTPS_OPTION_RESET_TX 0x0010U /**< Reset the transmitter */
#define XUARTPS_OPTION_RESET_RX 0x0008 /**< Reset the receiver */ #define XUARTPS_OPTION_RESET_RX 0x0008U /**< Reset the receiver */
#define XUARTPS_OPTION_ASSERT_RTS 0x0004 /**< Assert the RTS bit */ #define XUARTPS_OPTION_ASSERT_RTS 0x0004U /**< Assert the RTS bit */
#define XUARTPS_OPTION_ASSERT_DTR 0x0002 /**< Assert the DTR bit */ #define XUARTPS_OPTION_ASSERT_DTR 0x0002U /**< Assert the DTR bit */
#define XUARTPS_OPTION_SET_FCM 0x0001 /**< Turn on flow control mode */ #define XUARTPS_OPTION_SET_FCM 0x0001U /**< Turn on flow control mode */
/*@}*/ /*@}*/
@ -213,10 +215,10 @@ extern "C" {
* @{ * @{
*/ */
#define XUARTPS_OPER_MODE_NORMAL 0x00 /**< Normal Mode */ #define XUARTPS_OPER_MODE_NORMAL (u8)0x00U /**< Normal Mode */
#define XUARTPS_OPER_MODE_AUTO_ECHO 0x01 /**< Auto Echo Mode */ #define XUARTPS_OPER_MODE_AUTO_ECHO (u8)0x01U /**< Auto Echo Mode */
#define XUARTPS_OPER_MODE_LOCAL_LOOP 0x02 /**< Local Loopback Mode */ #define XUARTPS_OPER_MODE_LOCAL_LOOP (u8)0x02U /**< Local Loopback Mode */
#define XUARTPS_OPER_MODE_REMOTE_LOOP 0x03 /**< Remote Loopback Mode */ #define XUARTPS_OPER_MODE_REMOTE_LOOP (u8)0x03U /**< Remote Loopback Mode */
/* @} */ /* @} */
@ -228,19 +230,19 @@ extern "C" {
* *
* @{ * @{
*/ */
#define XUARTPS_FORMAT_8_BITS 0 /**< 8 data bits */ #define XUARTPS_FORMAT_8_BITS 0U /**< 8 data bits */
#define XUARTPS_FORMAT_7_BITS 2 /**< 7 data bits */ #define XUARTPS_FORMAT_7_BITS 2U /**< 7 data bits */
#define XUARTPS_FORMAT_6_BITS 3 /**< 6 data bits */ #define XUARTPS_FORMAT_6_BITS 3U /**< 6 data bits */
#define XUARTPS_FORMAT_NO_PARITY 4 /**< No parity */ #define XUARTPS_FORMAT_NO_PARITY 4U /**< No parity */
#define XUARTPS_FORMAT_MARK_PARITY 3 /**< Mark parity */ #define XUARTPS_FORMAT_MARK_PARITY 3U /**< Mark parity */
#define XUARTPS_FORMAT_SPACE_PARITY 2 /**< parity */ #define XUARTPS_FORMAT_SPACE_PARITY 2U /**< parity */
#define XUARTPS_FORMAT_ODD_PARITY 1 /**< Odd parity */ #define XUARTPS_FORMAT_ODD_PARITY 1U /**< Odd parity */
#define XUARTPS_FORMAT_EVEN_PARITY 0 /**< Even parity */ #define XUARTPS_FORMAT_EVEN_PARITY 0U /**< Even parity */
#define XUARTPS_FORMAT_2_STOP_BIT 2 /**< 2 stop bits */ #define XUARTPS_FORMAT_2_STOP_BIT 2U /**< 2 stop bits */
#define XUARTPS_FORMAT_1_5_STOP_BIT 1 /**< 1.5 stop bits */ #define XUARTPS_FORMAT_1_5_STOP_BIT 1U /**< 1.5 stop bits */
#define XUARTPS_FORMAT_1_STOP_BIT 0 /**< 1 stop bit */ #define XUARTPS_FORMAT_1_STOP_BIT 0U /**< 1 stop bit */
/*@}*/ /*@}*/
/** @name Callback events /** @name Callback events
@ -251,11 +253,11 @@ extern "C" {
* *
* @{ * @{
*/ */
#define XUARTPS_EVENT_RECV_DATA 1 /**< Data receiving done */ #define XUARTPS_EVENT_RECV_DATA 1U /**< Data receiving done */
#define XUARTPS_EVENT_RECV_TOUT 2 /**< A receive timeout occurred */ #define XUARTPS_EVENT_RECV_TOUT 2U /**< A receive timeout occurred */
#define XUARTPS_EVENT_SENT_DATA 3 /**< Data transmission done */ #define XUARTPS_EVENT_SENT_DATA 3U /**< Data transmission done */
#define XUARTPS_EVENT_RECV_ERROR 4 /**< A receive error detected */ #define XUARTPS_EVENT_RECV_ERROR 4U /**< A receive error detected */
#define XUARTPS_EVENT_MODEM 5 /**< Modem status changed */ #define XUARTPS_EVENT_MODEM 5U /**< Modem status changed */
/*@}*/ /*@}*/
@ -268,7 +270,7 @@ typedef struct {
u16 DeviceId; /**< Unique ID of device */ u16 DeviceId; /**< Unique ID of device */
u32 BaseAddress; /**< Base address of device (IPIF) */ u32 BaseAddress; /**< Base address of device (IPIF) */
u32 InputClockHz;/**< Input clock frequency */ u32 InputClockHz;/**< Input clock frequency */
int ModemPinsConnected; /** Specifies whether modem pins are connected s32 ModemPinsConnected; /** Specifies whether modem pins are connected
* to MIO or FMIO */ * to MIO or FMIO */
} XUartPs_Config; } XUartPs_Config;
@ -277,8 +279,8 @@ typedef struct {
*/ */
typedef struct { typedef struct {
u8 *NextBytePtr; u8 *NextBytePtr;
unsigned int RequestedBytes; u32 RequestedBytes;
unsigned int RemainingBytes; u32 RemainingBytes;
} XUartPsBuffer; } XUartPsBuffer;
/** /**
@ -287,7 +289,7 @@ typedef struct {
typedef struct { typedef struct {
u32 BaudRate; /**< In bps, ie 1200 */ u32 BaudRate; /**< In bps, ie 1200 */
u32 DataBits; /**< Number of data bits */ u32 DataBits; /**< Number of data bits */
u32 Parity; /**< Parity */ u32 Parity; /**< Parity */
u8 StopBits; /**< Number of stop bits */ u8 StopBits; /**< Number of stop bits */
} XUartPsFormat; } XUartPsFormat;
@ -308,7 +310,7 @@ typedef struct {
* *
******************************************************************************/ ******************************************************************************/
typedef void (*XUartPs_Handler) (void *CallBackRef, u32 Event, typedef void (*XUartPs_Handler) (void *CallBackRef, u32 Event,
unsigned int EventData); u32 EventData);
/** /**
* The XUartPs driver instance data structure. A pointer to an instance data * The XUartPs driver instance data structure. A pointer to an instance data
@ -344,7 +346,7 @@ typedef struct {
* *
******************************************************************************/ ******************************************************************************/
#define XUartPs_GetChannelStatus(InstancePtr) \ #define XUartPs_GetChannelStatus(InstancePtr) \
Xil_In32(((InstancePtr)->Config.BaseAddress) + XUARTPS_SR_OFFSET) Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET)
/****************************************************************************/ /****************************************************************************/
/** /**
@ -359,7 +361,7 @@ typedef struct {
* *
******************************************************************************/ ******************************************************************************/
#define XUartPs_GetModeControl(InstancePtr) \ #define XUartPs_GetModeControl(InstancePtr) \
Xil_In32(((InstancePtr)->Config.BaseAddress) + XUARTPS_CR_OFFSET) Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET)
/****************************************************************************/ /****************************************************************************/
/** /**
@ -375,8 +377,8 @@ typedef struct {
* *
******************************************************************************/ ******************************************************************************/
#define XUartPs_SetModeControl(InstancePtr, RegisterValue) \ #define XUartPs_SetModeControl(InstancePtr, RegisterValue) \
Xil_Out32(((InstancePtr)->Config.BaseAddress) + XUARTPS_CR_OFFSET, \ Xil_Out32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET, \
(RegisterValue)) (u32)(RegisterValue))
/****************************************************************************/ /****************************************************************************/
/** /**
@ -391,9 +393,9 @@ typedef struct {
* *
******************************************************************************/ ******************************************************************************/
#define XUartPs_EnableUart(InstancePtr) \ #define XUartPs_EnableUart(InstancePtr) \
Xil_Out32(((InstancePtr)->Config.BaseAddress + XUARTPS_CR_OFFSET), \ Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
((Xil_In32((InstancePtr)->Config.BaseAddress + XUARTPS_CR_OFFSET) & \ ((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET) & \
~XUARTPS_CR_EN_DIS_MASK) | (XUARTPS_CR_RX_EN | XUARTPS_CR_TX_EN))) (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_EN | (u32)XUARTPS_CR_TX_EN)))
/****************************************************************************/ /****************************************************************************/
/** /**
@ -408,9 +410,9 @@ typedef struct {
* *
******************************************************************************/ ******************************************************************************/
#define XUartPs_DisableUart(InstancePtr) \ #define XUartPs_DisableUart(InstancePtr) \
Xil_Out32(((InstancePtr)->Config.BaseAddress + XUARTPS_CR_OFFSET), \ Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
(((Xil_In32((InstancePtr)->Config.BaseAddress + XUARTPS_CR_OFFSET)) & \ (((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET)) & \
~XUARTPS_CR_EN_DIS_MASK) | (XUARTPS_CR_RX_DIS | XUARTPS_CR_TX_DIS))) (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS)))
/****************************************************************************/ /****************************************************************************/
/** /**
@ -427,8 +429,8 @@ typedef struct {
* *
******************************************************************************/ ******************************************************************************/
#define XUartPs_IsTransmitEmpty(InstancePtr) \ #define XUartPs_IsTransmitEmpty(InstancePtr) \
((Xil_In32(((InstancePtr)->Config.BaseAddress) + XUARTPS_SR_OFFSET) & \ ((Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET) & \
XUARTPS_SR_TXEMPTY) == XUARTPS_SR_TXEMPTY) (u32)XUARTPS_SR_TXEMPTY) == (u32)XUARTPS_SR_TXEMPTY)
/************************** Function Prototypes *****************************/ /************************** Function Prototypes *****************************/
@ -441,16 +443,16 @@ XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId);
/* /*
* Interface functions implemented in xuartps.c * Interface functions implemented in xuartps.c
*/ */
int XUartPs_CfgInitialize(XUartPs *InstancePtr, s32 XUartPs_CfgInitialize(XUartPs *InstancePtr,
XUartPs_Config * Config, u32 EffectiveAddr); XUartPs_Config * Config, u32 EffectiveAddr);
unsigned int XUartPs_Send(XUartPs *InstancePtr, u8 *BufferPtr, u32 XUartPs_Send(XUartPs *InstancePtr,u8 *BufferPtr,
unsigned int NumBytes); u32 NumBytes);
unsigned int XUartPs_Recv(XUartPs *InstancePtr, u8 *BufferPtr, u32 XUartPs_Recv(XUartPs *InstancePtr,u8 *BufferPtr,
unsigned int NumBytes); u32 NumBytes);
int XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate); s32 XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate);
/* /*
* Options functions in xuartps_options.c * Options functions in xuartps_options.c
@ -479,8 +481,9 @@ u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr);
void XUartPs_SetRecvTimeout(XUartPs *InstancePtr, u8 RecvTimeout); void XUartPs_SetRecvTimeout(XUartPs *InstancePtr, u8 RecvTimeout);
int XUartPs_SetDataFormat(XUartPs *InstancePtr, XUartPsFormat * Format); s32 XUartPs_SetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr);
void XUartPs_GetDataFormat(XUartPs *InstancePtr, XUartPsFormat * Format);
void XUartPs_GetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr);
/* /*
* interrupt functions in xuartps_intr.c * interrupt functions in xuartps_intr.c
@ -497,7 +500,7 @@ void XUartPs_SetHandler(XUartPs *InstancePtr, XUartPs_Handler FuncPtr,
/* /*
* self-test functions in xuartps_selftest.c * self-test functions in xuartps_selftest.c
*/ */
int XUartPs_SelfTest(XUartPs *InstancePtr); s32 XUartPs_SelfTest(XUartPs *InstancePtr);
#ifdef __cplusplus #ifdef __cplusplus
} }

16
XilinxProcessorIPLib/drivers/uartps/src/xuartps_g.c
View file

@ -70,17 +70,19 @@
/** /**
* Each XUartPs device in the system has an entry in this table. * Each XUartPs device in the system has an entry in this table.
*/ */
XUartPs_Config XUartPs_ConfigTable[] = { XUartPs_Config XUartPs_ConfigTable[XPAR_XUARTPS_NUM_INSTANCES] = {
#ifdef XPAR_XUARTPS_0_DEVICE_ID #ifdef XPAR_XUARTPS_0_DEVICE_ID
{ {
XPAR_XUARTPS_0_DEVICE_ID, (u16)XPAR_XUARTPS_0_DEVICE_ID,
XPAR_XUARTPS_0_BASEADDR, (u32)XPAR_XUARTPS_0_BASEADDR,
XPAR_XUARTPS_0_CLOCK_HZ (u32)XPAR_XUARTPS_0_CLOCK_HZ,
(s32)0
}, },
#endif #endif
{ {
XPAR_PS7_UART_1_DEVICE_ID, (u16)XPAR_PS7_UART_1_DEVICE_ID,
XPAR_PS7_UART_1_BASEADDR, (u32)XPAR_PS7_UART_1_BASEADDR,
XPAR_PS7_UART_1_UART_CLK_FREQ_HZ (u32)XPAR_PS7_UART_1_UART_CLK_FREQ_HZ,
(s32)0
} }
}; };

47
XilinxProcessorIPLib/drivers/uartps/src/xuartps_hw.c
View file

@ -76,15 +76,17 @@
*****************************************************************************/ *****************************************************************************/
void XUartPs_SendByte(u32 BaseAddress, u8 Data) void XUartPs_SendByte(u32 BaseAddress, u8 Data)
{ {
/* /*
* Wait until there is space in TX FIFO * Wait until there is space in TX FIFO
*/ */
while (XUartPs_IsTransmitFull(BaseAddress)); while (XUartPs_IsTransmitFull(BaseAddress)) {
;
}
/* /*
* Write the byte into the TX FIFO * Write the byte into the TX FIFO
*/ */
XUartPs_WriteReg(BaseAddress, XUARTPS_FIFO_OFFSET, Data); XUartPs_WriteReg(BaseAddress, XUARTPS_FIFO_OFFSET, (u32)Data);
} }
/****************************************************************************/ /****************************************************************************/
@ -102,15 +104,18 @@ void XUartPs_SendByte(u32 BaseAddress, u8 Data)
*****************************************************************************/ *****************************************************************************/
u8 XUartPs_RecvByte(u32 BaseAddress) u8 XUartPs_RecvByte(u32 BaseAddress)
{ {
/* u32 RecievedByte;
* Wait until there is data /*
*/ * Wait until there is data
while (!XUartPs_IsReceiveData(BaseAddress)); */
while (!XUartPs_IsReceiveData(BaseAddress)) {
/* ;
* Return the byte received }
*/ RecievedByte = XUartPs_ReadReg(BaseAddress, XUARTPS_FIFO_OFFSET);
return (XUartPs_ReadReg(BaseAddress, XUARTPS_FIFO_OFFSET)); /*
* Return the byte received
*/
return (u8)RecievedByte;
} }
/****************************************************************************/ /****************************************************************************/
@ -137,14 +142,14 @@ void XUartPs_ResetHw(u32 BaseAddress)
* Disable receive and transmit * Disable receive and transmit
*/ */
XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET, XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
XUARTPS_CR_RX_DIS | XUARTPS_CR_TX_DIS); ((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS));
/* /*
* Software reset of receive and transmit * Software reset of receive and transmit
* This clears the FIFO. * This clears the FIFO.
*/ */
XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET, XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
XUARTPS_CR_TXRST | XUARTPS_CR_RXRST); ((u32)XUARTPS_CR_TXRST | (u32)XUARTPS_CR_RXRST));
/* /*
* Clear status flags - SW reset wont clear sticky flags. * Clear status flags - SW reset wont clear sticky flags.
@ -185,8 +190,8 @@ void XUartPs_ResetHw(u32 BaseAddress)
* RX and TX are disable by default * RX and TX are disable by default
*/ */
XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET, XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
XUARTPS_CR_RX_DIS | XUARTPS_CR_TX_DIS | ((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS |
XUARTPS_CR_STOPBRK); (u32)XUARTPS_CR_STOPBRK));
} }

216
XilinxProcessorIPLib/drivers/uartps/src/xuartps_hw.h
View file

@ -75,22 +75,22 @@ extern "C" {
* Register offsets for the UART. * Register offsets for the UART.
* @{ * @{
*/ */
#define XUARTPS_CR_OFFSET 0x00 /**< Control Register [8:0] */ #define XUARTPS_CR_OFFSET 0x0000U /**< Control Register [8:0] */
#define XUARTPS_MR_OFFSET 0x04 /**< Mode Register [9:0] */ #define XUARTPS_MR_OFFSET 0x0004U /**< Mode Register [9:0] */
#define XUARTPS_IER_OFFSET 0x08 /**< Interrupt Enable [12:0] */ #define XUARTPS_IER_OFFSET 0x0008U /**< Interrupt Enable [12:0] */
#define XUARTPS_IDR_OFFSET 0x0C /**< Interrupt Disable [12:0] */ #define XUARTPS_IDR_OFFSET 0x000CU /**< Interrupt Disable [12:0] */
#define XUARTPS_IMR_OFFSET 0x10 /**< Interrupt Mask [12:0] */ #define XUARTPS_IMR_OFFSET 0x0010U /**< Interrupt Mask [12:0] */
#define XUARTPS_ISR_OFFSET 0x14 /**< Interrupt Status [12:0]*/ #define XUARTPS_ISR_OFFSET 0x0014U /**< Interrupt Status [12:0]*/
#define XUARTPS_BAUDGEN_OFFSET 0x18 /**< Baud Rate Generator [15:0] */ #define XUARTPS_BAUDGEN_OFFSET 0x0018U /**< Baud Rate Generator [15:0] */
#define XUARTPS_RXTOUT_OFFSET 0x1C /**< RX Timeout [7:0] */ #define XUARTPS_RXTOUT_OFFSET 0x001CU /**< RX Timeout [7:0] */
#define XUARTPS_RXWM_OFFSET 0x20 /**< RX FIFO Trigger Level [5:0] */ #define XUARTPS_RXWM_OFFSET 0x0020U /**< RX FIFO Trigger Level [5:0] */
#define XUARTPS_MODEMCR_OFFSET 0x24 /**< Modem Control [5:0] */ #define XUARTPS_MODEMCR_OFFSET 0x0024U /**< Modem Control [5:0] */
#define XUARTPS_MODEMSR_OFFSET 0x28 /**< Modem Status [8:0] */ #define XUARTPS_MODEMSR_OFFSET 0x0028U /**< Modem Status [8:0] */
#define XUARTPS_SR_OFFSET 0x2C /**< Channel Status [14:0] */ #define XUARTPS_SR_OFFSET 0x002CU /**< Channel Status [14:0] */
#define XUARTPS_FIFO_OFFSET 0x30 /**< FIFO [7:0] */ #define XUARTPS_FIFO_OFFSET 0x0030U /**< FIFO [7:0] */
#define XUARTPS_BAUDDIV_OFFSET 0x34 /**< Baud Rate Divider [7:0] */ #define XUARTPS_BAUDDIV_OFFSET 0x0034U /**< Baud Rate Divider [7:0] */
#define XUARTPS_FLOWDEL_OFFSET 0x38 /**< Flow Delay [5:0] */ #define XUARTPS_FLOWDEL_OFFSET 0x0038U /**< Flow Delay [5:0] */
#define XUARTPS_TXWM_OFFSET 0x44 /**< TX FIFO Trigger Level [5:0] */ #define XUARTPS_TXWM_OFFSET 0x0044U /**< TX FIFO Trigger Level [5:0] */
/* @} */ /* @} */
/** @name Control Register /** @name Control Register
@ -100,16 +100,16 @@ extern "C" {
* Control Register Bit Definition * Control Register Bit Definition
*/ */
#define XUARTPS_CR_STOPBRK 0x00000100 /**< Stop transmission of break */ #define XUARTPS_CR_STOPBRK 0x00000100U /**< Stop transmission of break */
#define XUARTPS_CR_STARTBRK 0x00000080 /**< Set break */ #define XUARTPS_CR_STARTBRK 0x00000080U /**< Set break */
#define XUARTPS_CR_TORST 0x00000040 /**< RX timeout counter restart */ #define XUARTPS_CR_TORST 0x00000040U /**< RX timeout counter restart */
#define XUARTPS_CR_TX_DIS 0x00000020 /**< TX disabled. */ #define XUARTPS_CR_TX_DIS 0x00000020U /**< TX disabled. */
#define XUARTPS_CR_TX_EN 0x00000010 /**< TX enabled */ #define XUARTPS_CR_TX_EN 0x00000010U /**< TX enabled */
#define XUARTPS_CR_RX_DIS 0x00000008 /**< RX disabled. */ #define XUARTPS_CR_RX_DIS 0x00000008U /**< RX disabled. */
#define XUARTPS_CR_RX_EN 0x00000004 /**< RX enabled */ #define XUARTPS_CR_RX_EN 0x00000004U /**< RX enabled */
#define XUARTPS_CR_EN_DIS_MASK 0x0000003C /**< Enable/disable Mask */ #define XUARTPS_CR_EN_DIS_MASK 0x0000003CU /**< Enable/disable Mask */
#define XUARTPS_CR_TXRST 0x00000002 /**< TX logic reset */ #define XUARTPS_CR_TXRST 0x00000002U /**< TX logic reset */
#define XUARTPS_CR_RXRST 0x00000001 /**< RX logic reset */ #define XUARTPS_CR_RXRST 0x00000001U /**< RX logic reset */
/* @}*/ /* @}*/
@ -122,31 +122,31 @@ extern "C" {
* Mode Register Bit Definition * Mode Register Bit Definition
* @{ * @{
*/ */
#define XUARTPS_MR_CCLK 0x00000400 /**< Input clock selection */ #define XUARTPS_MR_CCLK 0x00000400U /**< Input clock selection */
#define XUARTPS_MR_CHMODE_R_LOOP 0x00000300 /**< Remote loopback mode */ #define XUARTPS_MR_CHMODE_R_LOOP 0x00000300U /**< Remote loopback mode */
#define XUARTPS_MR_CHMODE_L_LOOP 0x00000200 /**< Local loopback mode */ #define XUARTPS_MR_CHMODE_L_LOOP 0x00000200U /**< Local loopback mode */
#define XUARTPS_MR_CHMODE_ECHO 0x00000100 /**< Auto echo mode */ #define XUARTPS_MR_CHMODE_ECHO 0x00000100U /**< Auto echo mode */
#define XUARTPS_MR_CHMODE_NORM 0x00000000 /**< Normal mode */ #define XUARTPS_MR_CHMODE_NORM 0x00000000U /**< Normal mode */
#define XUARTPS_MR_CHMODE_SHIFT 8 /**< Mode shift */ #define XUARTPS_MR_CHMODE_SHIFT 8U /**< Mode shift */
#define XUARTPS_MR_CHMODE_MASK 0x00000300 /**< Mode mask */ #define XUARTPS_MR_CHMODE_MASK 0x00000300U /**< Mode mask */
#define XUARTPS_MR_STOPMODE_2_BIT 0x00000080 /**< 2 stop bits */ #define XUARTPS_MR_STOPMODE_2_BIT 0x00000080U /**< 2 stop bits */
#define XUARTPS_MR_STOPMODE_1_5_BIT 0x00000040 /**< 1.5 stop bits */ #define XUARTPS_MR_STOPMODE_1_5_BIT 0x00000040U /**< 1.5 stop bits */
#define XUARTPS_MR_STOPMODE_1_BIT 0x00000000 /**< 1 stop bit */ #define XUARTPS_MR_STOPMODE_1_BIT 0x00000000U /**< 1 stop bit */
#define XUARTPS_MR_STOPMODE_SHIFT 6 /**< Stop bits shift */ #define XUARTPS_MR_STOPMODE_SHIFT 6U /**< Stop bits shift */
#define XUARTPS_MR_STOPMODE_MASK 0x000000A0 /**< Stop bits mask */ #define XUARTPS_MR_STOPMODE_MASK 0x000000A0U /**< Stop bits mask */
#define XUARTPS_MR_PARITY_NONE 0x00000020 /**< No parity mode */ #define XUARTPS_MR_PARITY_NONE 0x00000020U /**< No parity mode */
#define XUARTPS_MR_PARITY_MARK 0x00000018 /**< Mark parity mode */ #define XUARTPS_MR_PARITY_MARK 0x00000018U /**< Mark parity mode */
#define XUARTPS_MR_PARITY_SPACE 0x00000010 /**< Space parity mode */ #define XUARTPS_MR_PARITY_SPACE 0x00000010U /**< Space parity mode */
#define XUARTPS_MR_PARITY_ODD 0x00000008 /**< Odd parity mode */ #define XUARTPS_MR_PARITY_ODD 0x00000008U /**< Odd parity mode */
#define XUARTPS_MR_PARITY_EVEN 0x00000000 /**< Even parity mode */ #define XUARTPS_MR_PARITY_EVEN 0x00000000U /**< Even parity mode */
#define XUARTPS_MR_PARITY_SHIFT 3 /**< Parity setting shift */ #define XUARTPS_MR_PARITY_SHIFT 3U /**< Parity setting shift */
#define XUARTPS_MR_PARITY_MASK 0x00000038 /**< Parity mask */ #define XUARTPS_MR_PARITY_MASK 0x00000038U /**< Parity mask */
#define XUARTPS_MR_CHARLEN_6_BIT 0x00000006 /**< 6 bits data */ #define XUARTPS_MR_CHARLEN_6_BIT 0x00000006U /**< 6 bits data */
#define XUARTPS_MR_CHARLEN_7_BIT 0x00000004 /**< 7 bits data */ #define XUARTPS_MR_CHARLEN_7_BIT 0x00000004U /**< 7 bits data */
#define XUARTPS_MR_CHARLEN_8_BIT 0x00000000 /**< 8 bits data */ #define XUARTPS_MR_CHARLEN_8_BIT 0x00000000U /**< 8 bits data */
#define XUARTPS_MR_CHARLEN_SHIFT 1 /**< Data Length shift */ #define XUARTPS_MR_CHARLEN_SHIFT 1U /**< Data Length shift */
#define XUARTPS_MR_CHARLEN_MASK 0x00000006 /**< Data length mask */ #define XUARTPS_MR_CHARLEN_MASK 0x00000006U /**< Data length mask */
#define XUARTPS_MR_CLKSEL 0x00000001 /**< Input clock selection */ #define XUARTPS_MR_CLKSEL 0x00000001U /**< Input clock selection */
/* @} */ /* @} */
@ -164,20 +164,20 @@ extern "C" {
* *
* @{ * @{
*/ */
#define XUARTPS_IXR_TOVR 0x00001000 /**< Tx FIFO Overflow interrupt */ #define XUARTPS_IXR_TOVR 0x00001000U /**< Tx FIFO Overflow interrupt */
#define XUARTPS_IXR_TNFUL 0x00000800 /**< Tx FIFO Nearly Full interrupt */ #define XUARTPS_IXR_TNFUL 0x00000800U /**< Tx FIFO Nearly Full interrupt */
#define XUARTPS_IXR_TTRIG 0x00000400 /**< Tx Trig interrupt */ #define XUARTPS_IXR_TTRIG 0x00000400U /**< Tx Trig interrupt */
#define XUARTPS_IXR_DMS 0x00000200 /**< Modem status change interrupt */ #define XUARTPS_IXR_DMS 0x00000200U /**< Modem status change interrupt */
#define XUARTPS_IXR_TOUT 0x00000100 /**< Timeout error interrupt */ #define XUARTPS_IXR_TOUT 0x00000100U /**< Timeout error interrupt */
#define XUARTPS_IXR_PARITY 0x00000080 /**< Parity error interrupt */ #define XUARTPS_IXR_PARITY 0x00000080U /**< Parity error interrupt */
#define XUARTPS_IXR_FRAMING 0x00000040 /**< Framing error interrupt */ #define XUARTPS_IXR_FRAMING 0x00000040U /**< Framing error interrupt */
#define XUARTPS_IXR_OVER 0x00000020 /**< Overrun error interrupt */ #define XUARTPS_IXR_OVER 0x00000020U /**< Overrun error interrupt */
#define XUARTPS_IXR_TXFULL 0x00000010 /**< TX FIFO full interrupt. */ #define XUARTPS_IXR_TXFULL 0x00000010U /**< TX FIFO full interrupt. */
#define XUARTPS_IXR_TXEMPTY 0x00000008 /**< TX FIFO empty interrupt. */ #define XUARTPS_IXR_TXEMPTY 0x00000008U /**< TX FIFO empty interrupt. */
#define XUARTPS_IXR_RXFULL 0x00000004 /**< RX FIFO full interrupt. */ #define XUARTPS_IXR_RXFULL 0x00000004U /**< RX FIFO full interrupt. */
#define XUARTPS_IXR_RXEMPTY 0x00000002 /**< RX FIFO empty interrupt. */ #define XUARTPS_IXR_RXEMPTY 0x00000002U /**< RX FIFO empty interrupt. */
#define XUARTPS_IXR_RXOVR 0x00000001 /**< RX FIFO trigger interrupt. */ #define XUARTPS_IXR_RXOVR 0x00000001U /**< RX FIFO trigger interrupt. */
#define XUARTPS_IXR_MASK 0x00001FFF /**< Valid bit mask */ #define XUARTPS_IXR_MASK 0x00001FFFU /**< Valid bit mask */
/* @} */ /* @} */
@ -191,9 +191,9 @@ extern "C" {
* in the MR register. * in the MR register.
* @{ * @{
*/ */
#define XUARTPS_BAUDGEN_DISABLE 0x00000000 /**< Disable clock */ #define XUARTPS_BAUDGEN_DISABLE 0x00000000U /**< Disable clock */
#define XUARTPS_BAUDGEN_MASK 0x0000FFFF /**< Valid bits mask */ #define XUARTPS_BAUDGEN_MASK 0x0000FFFFU /**< Valid bits mask */
#define XUARTPS_BAUDGEN_RESET_VAL 0x0000028B /**< Reset value */ #define XUARTPS_BAUDGEN_RESET_VAL 0x0000028BU /**< Reset value */
/** @name Baud Divisor Rate register /** @name Baud Divisor Rate register
* *
@ -205,8 +205,8 @@ extern "C" {
* the MR_CCLK bit in the MR register. * the MR_CCLK bit in the MR register.
* @{ * @{
*/ */
#define XUARTPS_BAUDDIV_MASK 0x000000FF /**< 8 bit baud divider mask */ #define XUARTPS_BAUDDIV_MASK 0x000000FFU /**< 8 bit baud divider mask */
#define XUARTPS_BAUDDIV_RESET_VAL 0x0000000F /**< Reset value */ #define XUARTPS_BAUDDIV_RESET_VAL 0x0000000FU /**< Reset value */
/* @} */ /* @} */
@ -217,8 +217,8 @@ extern "C" {
* *
* @{ * @{
*/ */
#define XUARTPS_RXTOUT_DISABLE 0x00000000 /**< Disable time out */ #define XUARTPS_RXTOUT_DISABLE 0x00000000U /**< Disable time out */
#define XUARTPS_RXTOUT_MASK 0x000000FF /**< Valid bits mask */ #define XUARTPS_RXTOUT_MASK 0x000000FFU /**< Valid bits mask */
/** @name Receiver FIFO Trigger Level Register /** @name Receiver FIFO Trigger Level Register
* *
@ -227,9 +227,9 @@ extern "C" {
* @{ * @{
*/ */
#define XUARTPS_RXWM_DISABLE 0x00000000 /**< Disable RX trigger interrupt */ #define XUARTPS_RXWM_DISABLE 0x00000000U /**< Disable RX trigger interrupt */
#define XUARTPS_RXWM_MASK 0x0000003F /**< Valid bits mask */ #define XUARTPS_RXWM_MASK 0x0000003FU /**< Valid bits mask */
#define XUARTPS_RXWM_RESET_VAL 0x00000020 /**< Reset value */ #define XUARTPS_RXWM_RESET_VAL 0x00000020U /**< Reset value */
/* @} */ /* @} */
/** @name Transmit FIFO Trigger Level Register /** @name Transmit FIFO Trigger Level Register
@ -239,8 +239,8 @@ extern "C" {
* @{ * @{
*/ */
#define XUARTPS_TXWM_MASK 0x0000003F /**< Valid bits mask */ #define XUARTPS_TXWM_MASK 0x0000003FU /**< Valid bits mask */
#define XUARTPS_TXWM_RESET_VAL 0x00000020 /**< Reset value */ #define XUARTPS_TXWM_RESET_VAL 0x00000020U /**< Reset value */
/* @} */ /* @} */
/** @name Modem Control Register /** @name Modem Control Register
@ -250,9 +250,9 @@ extern "C" {
* *
* @{ * @{
*/ */
#define XUARTPS_MODEMCR_FCM 0x00000010 /**< Flow control mode */ #define XUARTPS_MODEMCR_FCM 0x00000010U /**< Flow control mode */
#define XUARTPS_MODEMCR_RTS 0x00000002 /**< Request to send */ #define XUARTPS_MODEMCR_RTS 0x00000002U /**< Request to send */
#define XUARTPS_MODEMCR_DTR 0x00000001 /**< Data terminal ready */ #define XUARTPS_MODEMCR_DTR 0x00000001U /**< Data terminal ready */
/* @} */ /* @} */
/** @name Modem Status Register /** @name Modem Status Register
@ -268,15 +268,15 @@ extern "C" {
* *
* @{ * @{
*/ */
#define XUARTPS_MODEMSR_FCMS 0x00000100 /**< Flow control mode (FCMS) */ #define XUARTPS_MODEMSR_FCMS 0x00000100U /**< Flow control mode (FCMS) */
#define XUARTPS_MODEMSR_DCD 0x00000080 /**< Complement of DCD input */ #define XUARTPS_MODEMSR_DCD 0x00000080U /**< Complement of DCD input */
#define XUARTPS_MODEMSR_RI 0x00000040 /**< Complement of RI input */ #define XUARTPS_MODEMSR_RI 0x00000040U /**< Complement of RI input */
#define XUARTPS_MODEMSR_DSR 0x00000020 /**< Complement of DSR input */ #define XUARTPS_MODEMSR_DSR 0x00000020U /**< Complement of DSR input */
#define XUARTPS_MODEMSR_CTS 0x00000010 /**< Complement of CTS input */ #define XUARTPS_MODEMSR_CTS 0x00000010U /**< Complement of CTS input */
#define XUARTPS_MODEMSR_DDCD 0x00000008 /**< Delta DCD indicator */ #define XUARTPS_MODEMSR_DDCD 0x00000008U /**< Delta DCD indicator */
#define XUARTPS_MODEMSR_TERI 0x00000004 /**< Trailing Edge Ring Indicator */ #define XUARTPS_MODEMSR_TERI 0x00000004U /**< Trailing Edge Ring Indicator */
#define XUARTPS_MODEMSR_DDSR 0x00000002 /**< Change of DSR */ #define XUARTPS_MODEMSR_DDSR 0x00000002U /**< Change of DSR */
#define XUARTPS_MODEMSR_DCTS 0x00000001 /**< Change of CTS */ #define XUARTPS_MODEMSR_DCTS 0x00000001U /**< Change of CTS */
/* @} */ /* @} */
/** @name Channel Status Register /** @name Channel Status Register
@ -287,21 +287,21 @@ extern "C" {
* *
* @{ * @{
*/ */
#define XUARTPS_SR_TNFUL 0x00004000 /**< TX FIFO Nearly Full Status */ #define XUARTPS_SR_TNFUL 0x00004000U /**< TX FIFO Nearly Full Status */
#define XUARTPS_SR_TTRIG 0x00002000 /**< TX FIFO Trigger Status */ #define XUARTPS_SR_TTRIG 0x00002000U /**< TX FIFO Trigger Status */
#define XUARTPS_SR_FLOWDEL 0x00001000 /**< RX FIFO fill over flow delay */ #define XUARTPS_SR_FLOWDEL 0x00001000U /**< RX FIFO fill over flow delay */
#define XUARTPS_SR_TACTIVE 0x00000800 /**< TX active */ #define XUARTPS_SR_TACTIVE 0x00000800U /**< TX active */
#define XUARTPS_SR_RACTIVE 0x00000400 /**< RX active */ #define XUARTPS_SR_RACTIVE 0x00000400U /**< RX active */
#define XUARTPS_SR_DMS 0x00000200 /**< Delta modem status change */ #define XUARTPS_SR_DMS 0x00000200U /**< Delta modem status change */
#define XUARTPS_SR_TOUT 0x00000100 /**< RX timeout */ #define XUARTPS_SR_TOUT 0x00000100U /**< RX timeout */
#define XUARTPS_SR_PARITY 0x00000080 /**< RX parity error */ #define XUARTPS_SR_PARITY 0x00000080U /**< RX parity error */
#define XUARTPS_SR_FRAME 0x00000040 /**< RX frame error */ #define XUARTPS_SR_FRAME 0x00000040U /**< RX frame error */
#define XUARTPS_SR_OVER 0x00000020 /**< RX overflow error */ #define XUARTPS_SR_OVER 0x00000020U /**< RX overflow error */
#define XUARTPS_SR_TXFULL 0x00000010 /**< TX FIFO full */ #define XUARTPS_SR_TXFULL 0x00000010U /**< TX FIFO full */
#define XUARTPS_SR_TXEMPTY 0x00000008 /**< TX FIFO empty */ #define XUARTPS_SR_TXEMPTY 0x00000008U /**< TX FIFO empty */
#define XUARTPS_SR_RXFULL 0x00000004 /**< RX FIFO full */ #define XUARTPS_SR_RXFULL 0x00000004U /**< RX FIFO full */
#define XUARTPS_SR_RXEMPTY 0x00000002 /**< RX FIFO empty */ #define XUARTPS_SR_RXEMPTY 0x00000002U /**< RX FIFO empty */
#define XUARTPS_SR_RXOVR 0x00000001 /**< RX FIFO fill over trigger */ #define XUARTPS_SR_RXOVR 0x00000001U /**< RX FIFO fill over trigger */
/* @} */ /* @} */
/** @name Flow Delay Register /** @name Flow Delay Register
@ -352,7 +352,7 @@ extern "C" {
* *
******************************************************************************/ ******************************************************************************/
#define XUartPs_ReadReg(BaseAddress, RegOffset) \ #define XUartPs_ReadReg(BaseAddress, RegOffset) \
Xil_In32((BaseAddress) + (RegOffset)) Xil_In32((BaseAddress) + (u32)(RegOffset))
/***************************************************************************/ /***************************************************************************/
/** /**
@ -371,7 +371,7 @@ extern "C" {
* *
******************************************************************************/ ******************************************************************************/
#define XUartPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \ #define XUartPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue)) Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))
/****************************************************************************/ /****************************************************************************/
/** /**
@ -387,7 +387,7 @@ extern "C" {
******************************************************************************/ ******************************************************************************/
#define XUartPs_IsReceiveData(BaseAddress) \ #define XUartPs_IsReceiveData(BaseAddress) \
!((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \ !((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \
XUARTPS_SR_RXEMPTY) == XUARTPS_SR_RXEMPTY) (u32)XUARTPS_SR_RXEMPTY) == (u32)XUARTPS_SR_RXEMPTY)
/****************************************************************************/ /****************************************************************************/
/** /**
@ -404,7 +404,7 @@ extern "C" {
******************************************************************************/ ******************************************************************************/
#define XUartPs_IsTransmitFull(BaseAddress) \ #define XUartPs_IsTransmitFull(BaseAddress) \
((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \ ((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \
XUARTPS_SR_TXFULL) == XUARTPS_SR_TXFULL) (u32)XUARTPS_SR_TXFULL) == (u32)XUARTPS_SR_TXFULL)
/************************** Function Prototypes ******************************/ /************************** Function Prototypes ******************************/

68
XilinxProcessorIPLib/drivers/uartps/src/xuartps_intr.c
View file

@ -59,15 +59,15 @@
/************************** Function Prototypes *****************************/ /************************** Function Prototypes *****************************/
static void ReceiveDataHandler(XUartPs *InstancePtr); static void ReceiveDataHandler(XUartPs *InstancePtr);
static void SendDataHandler(XUartPs *InstancePtr, u32 isrstatus); static void SendDataHandler(XUartPs *InstancePtr, u32 IsrStatus);
static void ReceiveErrorHandler(XUartPs *InstancePtr); static void ReceiveErrorHandler(XUartPs *InstancePtr);
static void ReceiveTimeoutHandler(XUartPs *InstancePtr); static void ReceiveTimeoutHandler(XUartPs *InstancePtr);
static void ModemHandler(XUartPs *InstancePtr); static void ModemHandler(XUartPs *InstancePtr);
/* Internal function prototypes implemented in xuartps.c */ /* Internal function prototypes implemented in xuartps.c */
extern unsigned int XUartPs_ReceiveBuffer(XUartPs *InstancePtr); extern u32 XUartPs_ReceiveBuffer(XUartPs *InstancePtr);
extern unsigned int XUartPs_SendBuffer(XUartPs *InstancePtr); extern u32 XUartPs_SendBuffer(XUartPs *InstancePtr);
/************************** Variable Definitions ****************************/ /************************** Variable Definitions ****************************/
@ -117,24 +117,25 @@ u32 XUartPs_GetInterruptMask(XUartPs *InstancePtr)
*****************************************************************************/ *****************************************************************************/
void XUartPs_SetInterruptMask(XUartPs *InstancePtr, u32 Mask) void XUartPs_SetInterruptMask(XUartPs *InstancePtr, u32 Mask)
{ {
u32 TempMask = Mask;
/* /*
* Assert validates the input arguments * Assert validates the input arguments
*/ */
Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr != NULL);
Mask &= XUARTPS_IXR_MASK; TempMask &= (u32)XUARTPS_IXR_MASK;
/* /*
* Write the mask to the IER Register * Write the mask to the IER Register
*/ */
XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
XUARTPS_IER_OFFSET, Mask); XUARTPS_IER_OFFSET, TempMask);
/* /*
* Write the inverse of the Mask to the IDR register * Write the inverse of the Mask to the IDR register
*/ */
XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
XUARTPS_IDR_OFFSET, (~Mask)); XUARTPS_IDR_OFFSET, (~TempMask));
} }
@ -204,31 +205,32 @@ void XUartPs_InterruptHandler(XUartPs *InstancePtr)
XUARTPS_ISR_OFFSET); XUARTPS_ISR_OFFSET);
/* /*
* Dispatch an appropiate handler. * Dispatch an appropriate handler.
*/ */
if(0 != (IsrStatus & (XUARTPS_IXR_RXOVR | XUARTPS_IXR_RXEMPTY | if((IsrStatus & ((u32)XUARTPS_IXR_RXOVR | (u32)XUARTPS_IXR_RXEMPTY |
XUARTPS_IXR_RXFULL))) { (u32)XUARTPS_IXR_RXFULL)) != (u32)0) {
/* Recieved data interrupt */ /* Received data interrupt */
ReceiveDataHandler(InstancePtr); ReceiveDataHandler(InstancePtr);
} }
if(0 != (IsrStatus & (XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_TXFULL))) { if((IsrStatus & ((u32)XUARTPS_IXR_TXEMPTY | (u32)XUARTPS_IXR_TXFULL))
!= (u32)0) {
/* Transmit data interrupt */ /* Transmit data interrupt */
SendDataHandler(InstancePtr, IsrStatus); SendDataHandler(InstancePtr, IsrStatus);
} }
if(0 != (IsrStatus & (XUARTPS_IXR_OVER | XUARTPS_IXR_FRAMING | if((IsrStatus & ((u32)XUARTPS_IXR_OVER | (u32)XUARTPS_IXR_FRAMING |
XUARTPS_IXR_PARITY))) { (u32)XUARTPS_IXR_PARITY)) != (u32)0) {
/* Recieved Error Status interrupt */ /* Received Error Status interrupt */
ReceiveErrorHandler(InstancePtr); ReceiveErrorHandler(InstancePtr);
} }
if(0 != (IsrStatus & XUARTPS_IXR_TOUT )) { if((IsrStatus & ((u32)XUARTPS_IXR_TOUT)) != (u32)0) {
/* Recieved Timeout interrupt */ /* Received Timeout interrupt */
ReceiveTimeoutHandler(InstancePtr); ReceiveTimeoutHandler(InstancePtr);
} }
if(0 != (IsrStatus & XUARTPS_IXR_DMS)) { if((IsrStatus & ((u32)XUARTPS_IXR_DMS)) != (u32)0) {
/* Modem status interrupt */ /* Modem status interrupt */
ModemHandler(InstancePtr); ModemHandler(InstancePtr);
} }
@ -261,8 +263,8 @@ static void ReceiveErrorHandler(XUartPs *InstancePtr)
* go ahead and receive them. Removing bytes from the RX FIFO will * go ahead and receive them. Removing bytes from the RX FIFO will
* clear the interrupt. * clear the interrupt.
*/ */
if (InstancePtr->ReceiveBuffer.RemainingBytes != 0) { if (InstancePtr->ReceiveBuffer.RemainingBytes != (u32)0) {
XUartPs_ReceiveBuffer(InstancePtr); (void)XUartPs_ReceiveBuffer(InstancePtr);
} }
/* /*
@ -300,8 +302,8 @@ static void ReceiveTimeoutHandler(XUartPs *InstancePtr)
* go ahead and receive them. Removing bytes from the RX FIFO will * go ahead and receive them. Removing bytes from the RX FIFO will
* clear the interrupt. * clear the interrupt.
*/ */
if (InstancePtr->ReceiveBuffer.RemainingBytes != 0) { if (InstancePtr->ReceiveBuffer.RemainingBytes != (u32)0) {
XUartPs_ReceiveBuffer(InstancePtr); (void)XUartPs_ReceiveBuffer(InstancePtr);
} }
/* /*
@ -311,7 +313,7 @@ static void ReceiveTimeoutHandler(XUartPs *InstancePtr)
* don't rely on previous test of remaining bytes since receive * don't rely on previous test of remaining bytes since receive
* function updates it * function updates it
*/ */
if (InstancePtr->ReceiveBuffer.RemainingBytes != 0) { if (InstancePtr->ReceiveBuffer.RemainingBytes != (u32)0) {
Event = XUARTPS_EVENT_RECV_TOUT; Event = XUARTPS_EVENT_RECV_TOUT;
} else { } else {
Event = XUARTPS_EVENT_RECV_DATA; Event = XUARTPS_EVENT_RECV_DATA;
@ -345,17 +347,16 @@ static void ReceiveDataHandler(XUartPs *InstancePtr)
* go ahead and receive them. Removing bytes from the RX FIFO will * go ahead and receive them. Removing bytes from the RX FIFO will
* clear the interrupt. * clear the interrupt.
*/ */
if (InstancePtr->ReceiveBuffer.RemainingBytes != 0) { if (InstancePtr->ReceiveBuffer.RemainingBytes != (u32)0) {
XUartPs_ReceiveBuffer(InstancePtr); (void)XUartPs_ReceiveBuffer(InstancePtr);
} }
/* If the last byte of a message was received then call the application
/* If the last byte of a message was received then call the application
* handler, this code should not use an else from the previous check of * handler, this code should not use an else from the previous check of
* the number of bytes to receive because the call to receive the buffer * the number of bytes to receive because the call to receive the buffer
* updates the bytes ramained * updates the bytes ramained
*/ */
if (InstancePtr->ReceiveBuffer.RemainingBytes == 0) { if (InstancePtr->ReceiveBuffer.RemainingBytes == (u32)0) {
InstancePtr->Handler(InstancePtr->CallBackRef, InstancePtr->Handler(InstancePtr->CallBackRef,
XUARTPS_EVENT_RECV_DATA, XUARTPS_EVENT_RECV_DATA,
(InstancePtr->ReceiveBuffer.RequestedBytes - (InstancePtr->ReceiveBuffer.RequestedBytes -
@ -386,10 +387,10 @@ static void SendDataHandler(XUartPs *InstancePtr, u32 IsrStatus)
* the transmit interrupt so it will stop interrupting as it interrupts * the transmit interrupt so it will stop interrupting as it interrupts
* any time the FIFO is empty * any time the FIFO is empty
*/ */
if (InstancePtr->SendBuffer.RemainingBytes == 0) { if (InstancePtr->SendBuffer.RemainingBytes == (u32)0) {
XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
XUARTPS_IDR_OFFSET, XUARTPS_IDR_OFFSET,
(XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_TXFULL)); ((u32)XUARTPS_IXR_TXEMPTY | (u32)XUARTPS_IXR_TXFULL));
/* Call the application handler to indicate the sending is done */ /* Call the application handler to indicate the sending is done */
InstancePtr->Handler(InstancePtr->CallBackRef, InstancePtr->Handler(InstancePtr->CallBackRef,
@ -401,10 +402,13 @@ static void SendDataHandler(XUartPs *InstancePtr, u32 IsrStatus)
/* /*
* If TX FIFO is empty, send more. * If TX FIFO is empty, send more.
*/ */
else if(IsrStatus & XUARTPS_IXR_TXEMPTY) { else if((IsrStatus & ((u32)XUARTPS_IXR_TXEMPTY)) != (u32)0) {
XUartPs_SendBuffer(InstancePtr); (void)XUartPs_SendBuffer(InstancePtr);
}
else {
/* Else with dummy entry for MISRA-C Compliance.*/
;
} }
} }
/****************************************************************************/ /****************************************************************************/

209
XilinxProcessorIPLib/drivers/uartps/src/xuartps_options.c
View file

@ -114,9 +114,9 @@ static Mapping OptionsTable[] = {
*****************************************************************************/ *****************************************************************************/
u16 XUartPs_GetOptions(XUartPs *InstancePtr) u16 XUartPs_GetOptions(XUartPs *InstancePtr)
{ {
u16 Options = 0; u16 Options = 0U;
u32 Register; u32 Register;
unsigned int Index; u32 Index;
/* /*
* Assert validates the input arguments * Assert validates the input arguments
@ -128,7 +128,7 @@ u16 XUartPs_GetOptions(XUartPs *InstancePtr)
* Loop thru the options table to map the physical options in the * Loop thru the options table to map the physical options in the
* registers of the UART to the logical options to be returned * registers of the UART to the logical options to be returned
*/ */
for (Index = 0; Index < XUARTPS_NUM_OPTIONS; Index++) { for (Index = 0U; Index < XUARTPS_NUM_OPTIONS; Index++) {
Register = XUartPs_ReadReg(InstancePtr->Config.BaseAddress, Register = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
OptionsTable[Index]. OptionsTable[Index].
RegisterOffset); RegisterOffset);
@ -139,7 +139,7 @@ u16 XUartPs_GetOptions(XUartPs *InstancePtr)
* ignoring any bits which are zero since the options variable * ignoring any bits which are zero since the options variable
* is initialized to zero * is initialized to zero
*/ */
if (Register & OptionsTable[Index].Mask) { if ((Register & OptionsTable[Index].Mask) != (u32)0) {
Options |= OptionsTable[Index].Option; Options |= OptionsTable[Index].Option;
} }
} }
@ -170,7 +170,7 @@ u16 XUartPs_GetOptions(XUartPs *InstancePtr)
*****************************************************************************/ *****************************************************************************/
void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options) void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options)
{ {
unsigned int Index; u32 Index;
u32 Register; u32 Register;
/* /*
@ -183,7 +183,7 @@ void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options)
* Loop thru the options table to map the logical options to the * Loop thru the options table to map the logical options to the
* physical options in the registers of the UART. * physical options in the registers of the UART.
*/ */
for (Index = 0; Index < XUARTPS_NUM_OPTIONS; Index++) { for (Index = 0U; Index < XUARTPS_NUM_OPTIONS; Index++) {
/* /*
* Read the register which contains option so that the register * Read the register which contains option so that the register
@ -199,7 +199,7 @@ void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options)
* bit in the specified register, otherwise clear the bit in * bit in the specified register, otherwise clear the bit in
* the register. * the register.
*/ */
if (Options & OptionsTable[Index].Option) { if ((Options & OptionsTable[Index].Option) != (u16)0) {
Register |= OptionsTable[Index].Mask; Register |= OptionsTable[Index].Mask;
} }
else { else {
@ -248,7 +248,8 @@ u8 XUartPs_GetFifoThreshold(XUartPs *InstancePtr)
/* Return only the trigger level from the register value */ /* Return only the trigger level from the register value */
return (RtrigRegister & XUARTPS_RXWM_MASK); RtrigRegister &= (u8)XUARTPS_RXWM_MASK;
return RtrigRegister;
} }
/****************************************************************************/ /****************************************************************************/
@ -274,10 +275,10 @@ void XUartPs_SetFifoThreshold(XUartPs *InstancePtr, u8 TriggerLevel)
* Assert validates the input arguments * Assert validates the input arguments
*/ */
Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(TriggerLevel <= XUARTPS_RXWM_MASK); Xil_AssertVoid(TriggerLevel <= (u8)XUARTPS_RXWM_MASK);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
RtrigRegister = TriggerLevel & XUARTPS_RXWM_MASK; RtrigRegister = ((u32)TriggerLevel) & (u32)XUARTPS_RXWM_MASK;
/* /*
* Write the new value for the FIFO control register to it such that the * Write the new value for the FIFO control register to it such that the
@ -313,7 +314,7 @@ void XUartPs_SetFifoThreshold(XUartPs *InstancePtr, u8 TriggerLevel)
u16 XUartPs_GetModemStatus(XUartPs *InstancePtr) u16 XUartPs_GetModemStatus(XUartPs *InstancePtr)
{ {
u32 ModemStatusRegister; u32 ModemStatusRegister;
u16 TmpRegister;
/* /*
* Assert validates the input arguments * Assert validates the input arguments
*/ */
@ -324,7 +325,8 @@ u16 XUartPs_GetModemStatus(XUartPs *InstancePtr)
*/ */
ModemStatusRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress, ModemStatusRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
XUARTPS_MODEMSR_OFFSET); XUARTPS_MODEMSR_OFFSET);
return ModemStatusRegister; TmpRegister = (u16)ModemStatusRegister;
return TmpRegister;
} }
/****************************************************************************/ /****************************************************************************/
@ -344,6 +346,9 @@ u16 XUartPs_GetModemStatus(XUartPs *InstancePtr)
u32 XUartPs_IsSending(XUartPs *InstancePtr) u32 XUartPs_IsSending(XUartPs *InstancePtr)
{ {
u32 ChanStatRegister; u32 ChanStatRegister;
u32 ChanTmpSRegister;
u32 ActiveResult;
u32 EmptyResult;
/* /*
* Assert validates the input arguments * Assert validates the input arguments
@ -362,10 +367,12 @@ u32 XUartPs_IsSending(XUartPs *InstancePtr)
* If the transmitter is active, or the TX FIFO is not empty, then indicate * If the transmitter is active, or the TX FIFO is not empty, then indicate
* that the UART is still sending some data * that the UART is still sending some data
*/ */
return ((XUARTPS_SR_TACTIVE == (ChanStatRegister & ActiveResult = ChanStatRegister & ((u32)XUARTPS_SR_TACTIVE);
XUARTPS_SR_TACTIVE)) || EmptyResult = ChanStatRegister & ((u32)XUARTPS_SR_TXEMPTY);
(XUARTPS_SR_TXEMPTY != (ChanStatRegister & ChanTmpSRegister = (((u32)XUARTPS_SR_TACTIVE) == ActiveResult) ||
XUARTPS_SR_TXEMPTY))); (((u32)XUARTPS_SR_TXEMPTY) != EmptyResult);
return ChanTmpSRegister;
} }
/****************************************************************************/ /****************************************************************************/
@ -403,7 +410,7 @@ u8 XUartPs_GetOperMode(XUartPs *InstancePtr)
XUartPs_ReadReg(InstancePtr->Config.BaseAddress, XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
XUARTPS_MR_OFFSET); XUARTPS_MR_OFFSET);
ModeRegister &= XUARTPS_MR_CHMODE_MASK; ModeRegister &= (u32)XUARTPS_MR_CHMODE_MASK;
/* /*
* Return the constant * Return the constant
*/ */
@ -421,8 +428,9 @@ u8 XUartPs_GetOperMode(XUartPs *InstancePtr)
OperMode = XUARTPS_OPER_MODE_REMOTE_LOOP; OperMode = XUARTPS_OPER_MODE_REMOTE_LOOP;
break; break;
default: default:
OperMode = (u8) ((ModeRegister & XUARTPS_MR_CHMODE_MASK) >> OperMode = (u8) ((ModeRegister & (u32)XUARTPS_MR_CHMODE_MASK) >>
XUARTPS_MR_CHMODE_SHIFT); XUARTPS_MR_CHMODE_SHIFT);
break;
} }
return OperMode; return OperMode;
@ -464,21 +472,24 @@ void XUartPs_SetOperMode(XUartPs *InstancePtr, u8 OperationMode)
/* /*
* Set the correct value by masking the bits, then ORing the const. * Set the correct value by masking the bits, then ORing the const.
*/ */
ModeRegister &= ~XUARTPS_MR_CHMODE_MASK; ModeRegister &= (u32)(~XUARTPS_MR_CHMODE_MASK);
switch (OperationMode) { switch (OperationMode) {
case XUARTPS_OPER_MODE_NORMAL: case XUARTPS_OPER_MODE_NORMAL:
ModeRegister |= XUARTPS_MR_CHMODE_NORM; ModeRegister |= (u32)XUARTPS_MR_CHMODE_NORM;
break; break;
case XUARTPS_OPER_MODE_AUTO_ECHO: case XUARTPS_OPER_MODE_AUTO_ECHO:
ModeRegister |= XUARTPS_MR_CHMODE_ECHO; ModeRegister |= (u32)XUARTPS_MR_CHMODE_ECHO;
break; break;
case XUARTPS_OPER_MODE_LOCAL_LOOP: case XUARTPS_OPER_MODE_LOCAL_LOOP:
ModeRegister |= XUARTPS_MR_CHMODE_L_LOOP; ModeRegister |= (u32)XUARTPS_MR_CHMODE_L_LOOP;
break; break;
case XUARTPS_OPER_MODE_REMOTE_LOOP: case XUARTPS_OPER_MODE_REMOTE_LOOP:
ModeRegister |= XUARTPS_MR_CHMODE_R_LOOP; ModeRegister |= (u32)XUARTPS_MR_CHMODE_R_LOOP;
break; break;
default:
/* Default case made for MISRA-C Compliance. */
break;
} }
XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET, XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
@ -506,7 +517,7 @@ void XUartPs_SetOperMode(XUartPs *InstancePtr, u8 OperationMode)
*****************************************************************************/ *****************************************************************************/
u8 XUartPs_GetFlowDelay(XUartPs *InstancePtr) u8 XUartPs_GetFlowDelay(XUartPs *InstancePtr)
{ {
u32 FdelRegister; u32 FdelTmpRegister;
/* /*
* Assert validates the input arguments * Assert validates the input arguments
@ -517,13 +528,14 @@ u8 XUartPs_GetFlowDelay(XUartPs *InstancePtr)
/* /*
* Read the Mode register. * Read the Mode register.
*/ */
FdelRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress, FdelTmpRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
XUARTPS_FLOWDEL_OFFSET); XUARTPS_FLOWDEL_OFFSET);
/* /*
* Return the contents of the flow delay register * Return the contents of the flow delay register
*/ */
return (u8) (FdelRegister & XUARTPS_FLOWDEL_MASK); FdelTmpRegister = (u8)(FdelTmpRegister & (u32)XUARTPS_FLOWDEL_MASK);
return FdelTmpRegister;
} }
/****************************************************************************/ /****************************************************************************/
@ -550,14 +562,14 @@ void XUartPs_SetFlowDelay(XUartPs *InstancePtr, u8 FlowDelayValue)
* Assert validates the input arguments * Assert validates the input arguments
*/ */
Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(FlowDelayValue > XUARTPS_FLOWDEL_MASK); Xil_AssertVoid(FlowDelayValue > (u8)XUARTPS_FLOWDEL_MASK);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/* /*
* Set the correct value by shifting the input constant, then masking * Set the correct value by shifting the input constant, then masking
* the bits * the bits
*/ */
FdelRegister = (FlowDelayValue & XUARTPS_FLOWDEL_MASK); FdelRegister = ((u32)FlowDelayValue) & (u32)XUARTPS_FLOWDEL_MASK;
XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
XUARTPS_FLOWDEL_OFFSET, FdelRegister); XUARTPS_FLOWDEL_OFFSET, FdelRegister);
@ -579,6 +591,7 @@ void XUartPs_SetFlowDelay(XUartPs *InstancePtr, u8 FlowDelayValue)
u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr) u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr)
{ {
u32 RtoRegister; u32 RtoRegister;
u8 RtoRTmpRegister;
/* /*
* Assert validates the input arguments * Assert validates the input arguments
@ -587,7 +600,7 @@ u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr)
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/* /*
* Read the Recieve Timeout register. * Read the Receive Timeout register.
*/ */
RtoRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress, RtoRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
XUARTPS_RXTOUT_OFFSET); XUARTPS_RXTOUT_OFFSET);
@ -595,7 +608,8 @@ u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr)
/* /*
* Return the contents of the mode register shifted appropriately * Return the contents of the mode register shifted appropriately
*/ */
return (RtoRegister & XUARTPS_RXTOUT_MASK); RtoRTmpRegister = (u8)(RtoRegister & (u32)XUARTPS_RXTOUT_MASK);
return RtoRTmpRegister;
} }
/****************************************************************************/ /****************************************************************************/
@ -627,7 +641,7 @@ void XUartPs_SetRecvTimeout(XUartPs *InstancePtr, u8 RecvTimeout)
/* /*
* Set the correct value by masking the bits * Set the correct value by masking the bits
*/ */
RtoRegister = (RecvTimeout & XUARTPS_RXTOUT_MASK); RtoRegister = ((u32)RecvTimeout & (u32)XUARTPS_RXTOUT_MASK);
XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
XUARTPS_RXTOUT_OFFSET, RtoRegister); XUARTPS_RXTOUT_OFFSET, RtoRegister);
@ -670,10 +684,10 @@ void XUartPs_SetRecvTimeout(XUartPs *InstancePtr, u8 RecvTimeout)
* <br><br> * <br><br>
* *
*****************************************************************************/ *****************************************************************************/
int XUartPs_SetDataFormat(XUartPs *InstancePtr, s32 XUartPs_SetDataFormat(XUartPs *InstancePtr,
XUartPsFormat * FormatPtr) XUartPsFormat * FormatPtr)
{ {
int Status; s32 Status;
u32 ModeRegister; u32 ModeRegister;
Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr != NULL);
@ -683,56 +697,59 @@ int XUartPs_SetDataFormat(XUartPs *InstancePtr,
/* /*
* Verify the inputs specified are valid * Verify the inputs specified are valid
*/ */
if ((FormatPtr->DataBits > XUARTPS_FORMAT_6_BITS) || if ((FormatPtr->DataBits > ((u32)XUARTPS_FORMAT_6_BITS)) ||
(FormatPtr->StopBits > XUARTPS_FORMAT_2_STOP_BIT) || (FormatPtr->StopBits > ((u8)XUARTPS_FORMAT_2_STOP_BIT)) ||
(FormatPtr->Parity > XUARTPS_FORMAT_NO_PARITY)) { (FormatPtr->Parity > ((u32)XUARTPS_FORMAT_NO_PARITY))) {
return XST_INVALID_PARAM; Status = XST_INVALID_PARAM;
} else {
/*
* Try to set the baud rate and if it's not successful then don't
* continue altering the data format, this is done first to avoid the
* format from being altered when an error occurs
*/
Status = XUartPs_SetBaudRate(InstancePtr, FormatPtr->BaudRate);
if (Status != (s32)XST_SUCCESS) {
;
} else {
ModeRegister =
XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
XUARTPS_MR_OFFSET);
/*
* Set the length of data (8,7,6) by first clearing out the bits
* that control it in the register, then set the length in the register
*/
ModeRegister &= (u32)(~XUARTPS_MR_CHARLEN_MASK);
ModeRegister |= (FormatPtr->DataBits << XUARTPS_MR_CHARLEN_SHIFT);
/*
* Set the number of stop bits in the mode register by first clearing
* out the bits that control it in the register, then set the number
* of stop bits in the register.
*/
ModeRegister &= (u32)(~XUARTPS_MR_STOPMODE_MASK);
ModeRegister |= (((u32)FormatPtr->StopBits) << XUARTPS_MR_STOPMODE_SHIFT);
/*
* Set the parity by first clearing out the bits that control it in the
* register, then set the bits in the register, the default is no parity
* after clearing the register bits
*/
ModeRegister &= (u32)(~XUARTPS_MR_PARITY_MASK);
ModeRegister |= (FormatPtr->Parity << XUARTPS_MR_PARITY_SHIFT);
/*
* Update the mode register
*/
XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
ModeRegister);
Status = XST_SUCCESS;
}
} }
return Status;
/*
* Try to set the baud rate and if it's not successful then don't
* continue altering the data format, this is done first to avoid the
* format from being altered when an error occurs
*/
Status = XUartPs_SetBaudRate(InstancePtr, FormatPtr->BaudRate);
if (Status != XST_SUCCESS) {
return Status;
}
ModeRegister =
XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
XUARTPS_MR_OFFSET);
/*
* Set the length of data (8,7,6) by first clearing out the bits
* that control it in the register, then set the length in the register
*/
ModeRegister &= ~XUARTPS_MR_CHARLEN_MASK;
ModeRegister |= (FormatPtr->DataBits << XUARTPS_MR_CHARLEN_SHIFT);
/*
* Set the number of stop bits in the mode register by first clearing
* out the bits that control it in the register, then set the number
* of stop bits in the register.
*/
ModeRegister &= ~XUARTPS_MR_STOPMODE_MASK;
ModeRegister |= (FormatPtr->StopBits << XUARTPS_MR_STOPMODE_SHIFT);
/*
* Set the parity by first clearing out the bits that control it in the
* register, then set the bits in the register, the default is no parity
* after clearing the register bits
*/
ModeRegister &= ~XUARTPS_MR_PARITY_MASK;
ModeRegister |= (FormatPtr->Parity << XUARTPS_MR_PARITY_SHIFT);
/*
* Update the mode register
*/
XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
ModeRegister);
return XST_SUCCESS;
} }
/****************************************************************************/ /****************************************************************************/
@ -777,20 +794,20 @@ void XUartPs_GetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr)
* Get the length of data (8,7,6,5) * Get the length of data (8,7,6,5)
*/ */
FormatPtr->DataBits = FormatPtr->DataBits =
(ModeRegister & XUARTPS_MR_CHARLEN_MASK) >> ((ModeRegister & (u32)XUARTPS_MR_CHARLEN_MASK) >>
XUARTPS_MR_CHARLEN_SHIFT; XUARTPS_MR_CHARLEN_SHIFT);
/* /*
* Get the number of stop bits * Get the number of stop bits
*/ */
FormatPtr->StopBits = FormatPtr->StopBits =
(ModeRegister & XUARTPS_MR_STOPMODE_MASK) >> (u8)((ModeRegister & (u32)XUARTPS_MR_STOPMODE_MASK) >>
XUARTPS_MR_STOPMODE_SHIFT; XUARTPS_MR_STOPMODE_SHIFT);
/* /*
* Determine what parity is * Determine what parity is
*/ */
FormatPtr->Parity = FormatPtr->Parity =
(ModeRegister & XUARTPS_MR_PARITY_MASK) >> (u32)((ModeRegister & (u32)XUARTPS_MR_PARITY_MASK) >>
XUARTPS_MR_PARITY_SHIFT; XUARTPS_MR_PARITY_SHIFT);
} }

27
XilinxProcessorIPLib/drivers/uartps/src/xuartps_selftest.c
View file

@ -59,7 +59,7 @@
/***************** Macros (Inline Functions) Definitions *********************/ /***************** Macros (Inline Functions) Definitions *********************/
#define XUARTPS_TOTAL_BYTES 32 #define XUARTPS_TOTAL_BYTES (u8)32
/************************** Variable Definitions *****************************/ /************************** Variable Definitions *****************************/
@ -91,12 +91,13 @@ static u8 ReturnString[XUARTPS_TOTAL_BYTES];
* This function can hang if the hardware is not functioning properly. * This function can hang if the hardware is not functioning properly.
* *
******************************************************************************/ ******************************************************************************/
int XUartPs_SelfTest(XUartPs *InstancePtr) s32 XUartPs_SelfTest(XUartPs *InstancePtr)
{ {
int Status = XST_SUCCESS; s32 Status = XST_SUCCESS;
u32 IntrRegister; u32 IntrRegister;
u32 ModeRegister; u32 ModeRegister;
u8 Index; u8 Index;
u32 ReceiveDataResult;
/* /*
* Assert validates the input arguments * Assert validates the input arguments
@ -118,37 +119,41 @@ int XUartPs_SelfTest(XUartPs *InstancePtr)
ModeRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress, ModeRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
XUARTPS_MR_OFFSET); XUARTPS_MR_OFFSET);
XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET, XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
((ModeRegister & (~XUARTPS_MR_CHMODE_MASK)) | ((ModeRegister & (u32)(~XUARTPS_MR_CHMODE_MASK)) |
XUARTPS_MR_CHMODE_L_LOOP)); (u32)XUARTPS_MR_CHMODE_L_LOOP));
/* /*
* Send a number of bytes and receive them, one at a time. * Send a number of bytes and receive them, one at a time.
*/ */
for (Index = 0; Index < XUARTPS_TOTAL_BYTES; Index++) { for (Index = 0U; Index < XUARTPS_TOTAL_BYTES; Index++) {
/* /*
* Send out the byte and if it was not sent then the failure * Send out the byte and if it was not sent then the failure
* will be caught in the comparison at the end * will be caught in the comparison at the end
*/ */
XUartPs_Send(InstancePtr, &TestString[Index], 1); (void)XUartPs_Send(InstancePtr, &TestString[Index], 1U);
/* /*
* Wait until the byte is received. This can hang if the HW * Wait until the byte is received. This can hang if the HW
* is broken. Watch for the FIFO empty flag to be false. * is broken. Watch for the FIFO empty flag to be false.
*/ */
while (!(XUartPs_IsReceiveData(InstancePtr->Config. ReceiveDataResult = Xil_In32((InstancePtr->Config.BaseAddress) + XUARTPS_SR_OFFSET) &
BaseAddress))); XUARTPS_SR_RXEMPTY;
while (ReceiveDataResult == XUARTPS_SR_RXEMPTY ) {
ReceiveDataResult = Xil_In32((InstancePtr->Config.BaseAddress) + XUARTPS_SR_OFFSET) &
XUARTPS_SR_RXEMPTY;
}
/* /*
* Receive the byte * Receive the byte
*/ */
XUartPs_Recv(InstancePtr, &ReturnString[Index], 1); (void)XUartPs_Recv(InstancePtr, &ReturnString[Index], 1U);
} }
/* /*
* Compare the bytes received to the bytes sent to verify the exact data * Compare the bytes received to the bytes sent to verify the exact data
* was received * was received
*/ */
for (Index = 0; Index < XUARTPS_TOTAL_BYTES; Index++) { for (Index = 0U; Index < XUARTPS_TOTAL_BYTES; Index++) {
if (TestString[Index] != ReturnString[Index]) { if (TestString[Index] != ReturnString[Index]) {
Status = XST_UART_TEST_FAIL; Status = XST_UART_TEST_FAIL;
} }

8
XilinxProcessorIPLib/drivers/uartps/src/xuartps_sinit.c
View file

@ -60,7 +60,7 @@
/***************** Macros (Inline Functions) Definitions ********************/ /***************** Macros (Inline Functions) Definitions ********************/
/************************** Variable Definitions ****************************/ /************************** Variable Definitions ****************************/
extern XUartPs_Config XUartPs_ConfigTable[]; extern XUartPs_Config XUartPs_ConfigTable[XPAR_XUARTPS_NUM_INSTANCES];
/************************** Function Prototypes *****************************/ /************************** Function Prototypes *****************************/
@ -82,14 +82,14 @@ XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId)
{ {
XUartPs_Config *CfgPtr = NULL; XUartPs_Config *CfgPtr = NULL;
int Index; u32 Index;
for (Index = 0; Index < XPAR_XUARTPS_NUM_INSTANCES; Index++) { for (Index = 0U; Index < (u32)XPAR_XUARTPS_NUM_INSTANCES; Index++) {
if (XUartPs_ConfigTable[Index].DeviceId == DeviceId) { if (XUartPs_ConfigTable[Index].DeviceId == DeviceId) {
CfgPtr = &XUartPs_ConfigTable[Index]; CfgPtr = &XUartPs_ConfigTable[Index];
break; break;
} }
} }
return CfgPtr; return (XUartPs_Config *)CfgPtr;
} }