dp: Fixed compilation warnings.
Fixed compilation warnings when using: -Wall -Wextra No need for ">=0" assertions on arguments that are of unsigned type. Removed unused variables. Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
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dd5ecd1b10
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761ae699f7
4 changed files with 11 additions and 33 deletions
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@ -643,7 +643,7 @@ static void Dprx_DetectResolution(XDp *InstancePtr)
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XDp_WaitUs(InstancePtr, 1000);
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} while (((DpHres == 0) || (DpVres == 0)) && (GetResCount < 2000));
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xil_printf("\n*** Detected resolution: %d x %d ***\n", DpHres, DpVres);
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xil_printf("\n*** Detected resolution: %u x %u ***\n", DpHres, DpVres);
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}
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/******************************************************************************/
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@ -633,7 +633,7 @@ static void Dprx_DetectResolution(void *InstancePtr)
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XDp_WaitUs(InstancePtr, 1000);
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} while (((DpHres == 0) || (DpVres == 0)) && (GetResCount < 2000));
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xil_printf("\n*** Detected resolution: %d x %d ***\n", DpHres, DpVres);
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xil_printf("\n*** Detected resolution: %u x %u ***\n", DpHres, DpVres);
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}
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/******************************************************************************/
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@ -439,7 +439,6 @@ u32 XDp_TxCheckLinkStatus(XDp *InstancePtr, u8 LaneCount)
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{
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u32 Status;
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u8 RetryCount = 0;
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XDp_TxLinkConfig *LinkConfig = &InstancePtr->TxInstance.LinkConfig;
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/* Verify arguments. */
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Xil_AssertNonvoid(InstancePtr != NULL);
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@ -545,7 +544,7 @@ void XDp_TxCfgTxVsOffset(XDp *InstancePtr, u8 Offset)
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/* Verify arguments. */
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Xil_AssertVoid(InstancePtr != NULL);
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Xil_AssertVoid(XDp_GetCoreType(InstancePtr) == XDP_TX);
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Xil_AssertVoid((Offset >= 0) && (Offset < 16));
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Xil_AssertVoid(Offset < 16);
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InstancePtr->TxInstance.BoardChar.TxVsOffset = Offset;
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}
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@ -573,8 +572,8 @@ void XDp_TxCfgTxVsLevel(XDp *InstancePtr, u8 Level, u8 TxLevel)
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/* Verify arguments. */
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Xil_AssertVoid(InstancePtr != NULL);
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Xil_AssertVoid(XDp_GetCoreType(InstancePtr) == XDP_TX);
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Xil_AssertVoid((Level >= 0) && (Level < 4));
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Xil_AssertVoid((TxLevel >= 0) && (TxLevel < 16));
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Xil_AssertVoid(Level < 4);
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Xil_AssertVoid(TxLevel < 16);
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InstancePtr->TxInstance.BoardChar.TxVsLevels[Level] = TxLevel;
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}
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@ -602,8 +601,8 @@ void XDp_TxCfgTxPeLevel(XDp *InstancePtr, u8 Level, u8 TxLevel)
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/* Verify arguments. */
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Xil_AssertVoid(InstancePtr != NULL);
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Xil_AssertVoid(XDp_GetCoreType(InstancePtr) == XDP_TX);
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Xil_AssertVoid((Level >= 0) && (Level < 4));
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Xil_AssertVoid((TxLevel >= 0) && (TxLevel < 32));
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Xil_AssertVoid(Level < 4);
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Xil_AssertVoid(TxLevel < 32);
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InstancePtr->TxInstance.BoardChar.TxPeLevels[Level] = TxLevel;
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}
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@ -672,7 +671,6 @@ u32 XDp_TxAuxRead(XDp *InstancePtr, u32 DpcdAddress, u32 BytesToRead,
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void *ReadData)
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{
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u32 Status;
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XDp_AuxTransaction Request;
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/* Verify arguments. */
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Xil_AssertNonvoid(InstancePtr != NULL);
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@ -720,7 +718,6 @@ u32 XDp_TxAuxWrite(XDp *InstancePtr, u32 DpcdAddress, u32 BytesToWrite,
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void *WriteData)
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{
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u32 Status;
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XDp_AuxTransaction Request;
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/* Verify arguments. */
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Xil_AssertNonvoid(InstancePtr != NULL);
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@ -775,7 +772,6 @@ u32 XDp_TxIicRead(XDp *InstancePtr, u8 IicAddress, u16 Offset,
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u16 BytesToRead, void *ReadData)
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{
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u32 Status;
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XDp_AuxTransaction Request;
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u8 SegPtr;
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u16 NumBytesLeftInSeg;
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u16 BytesLeft;
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@ -785,9 +781,6 @@ u32 XDp_TxIicRead(XDp *InstancePtr, u8 IicAddress, u16 Offset,
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Xil_AssertNonvoid(InstancePtr != NULL);
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Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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Xil_AssertNonvoid(XDp_GetCoreType(InstancePtr) == XDP_TX);
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Xil_AssertNonvoid(IicAddress <= 0xFF);
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Xil_AssertNonvoid(Offset <= 0xFFFF);
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Xil_AssertNonvoid(BytesToRead <= 0xFFFF);
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Xil_AssertNonvoid(ReadData != NULL);
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if (!XDp_TxIsConnected(InstancePtr)) {
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@ -891,14 +884,11 @@ u32 XDp_TxIicWrite(XDp *InstancePtr, u8 IicAddress, u8 BytesToWrite,
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void *WriteData)
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{
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u32 Status;
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XDp_AuxTransaction Request;
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/* Verify arguments. */
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Xil_AssertNonvoid(InstancePtr != NULL);
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Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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Xil_AssertNonvoid(XDp_GetCoreType(InstancePtr) == XDP_TX);
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Xil_AssertNonvoid(IicAddress <= 0xFF);
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Xil_AssertNonvoid(BytesToWrite <= 0xFF);
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Xil_AssertNonvoid(WriteData != NULL);
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if (!XDp_TxIsConnected(InstancePtr)) {
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@ -1145,6 +1135,7 @@ u32 XDp_TxSetLinkRate(XDp *InstancePtr, u8 LinkRate)
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XDP_TX_PHY_CLOCK_SELECT_540GBPS);
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break;
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default:
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Status = XST_SUCCESS;
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break;
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}
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if (Status != XST_SUCCESS) {
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@ -1384,7 +1375,7 @@ void XDp_TxSetPhyPolarityLane(XDp *InstancePtr, u8 Lane, u8 Polarity)
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Xil_AssertVoid(InstancePtr != NULL);
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Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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Xil_AssertVoid(XDp_GetCoreType(InstancePtr) == XDP_TX);
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Xil_AssertVoid((Lane >= 0) && (Lane <= 3));
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Xil_AssertVoid(Lane <= 3);
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Xil_AssertVoid((Polarity == 0) || (Polarity == 1));
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/* Preserve current settings. */
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@ -2147,7 +2138,6 @@ static XDp_TxTrainingState XDp_TxTrainingStateChannelEqualization(
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u32 Status;
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u32 DelayUs;
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u32 IterationCount = 0;
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XDp_TxLinkConfig *LinkConfig = &InstancePtr->TxInstance.LinkConfig;
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/* Obtain the required delay for channel equalization as specified by
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* the RX device. */
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@ -2384,9 +2374,6 @@ static u32 XDp_TxGetLaneStatusAdjReqs(XDp *InstancePtr)
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*******************************************************************************/
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static u32 XDp_TxCheckClockRecovery(XDp *InstancePtr, u8 LaneCount)
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{
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u32 Status;
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u8 AuxData[6];
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u8 *LaneStatus = InstancePtr->TxInstance.RxConfig.LaneStatusAdjReqs;
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/* Check that all LANEx_CR_DONE bits are set. */
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@ -2441,8 +2428,6 @@ static u32 XDp_TxCheckClockRecovery(XDp *InstancePtr, u8 LaneCount)
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*******************************************************************************/
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static u32 XDp_TxCheckChannelEqualization(XDp *InstancePtr, u8 LaneCount)
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{
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u32 Status;
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u8 AuxData[6];
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u8 *LaneStatus = InstancePtr->TxInstance.RxConfig.LaneStatusAdjReqs;
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/* Check that all LANEx_CHANNEL_EQ_DONE bits are set. */
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@ -2529,7 +2514,6 @@ static u32 XDp_TxCheckChannelEqualization(XDp *InstancePtr, u8 LaneCount)
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*******************************************************************************/
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static void XDp_TxSetVswingPreemp(XDp *InstancePtr, u8 *AuxData)
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{
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u32 Status;
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u8 Data;
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u8 Index;
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u8 VsLevelRx = InstancePtr->TxInstance.LinkConfig.VsLevel;
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@ -1397,8 +1397,7 @@ u32 XDp_TxAllocatePayloadVcIdTable(XDp *InstancePtr, u8 VcId, u8 Ts)
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Xil_AssertNonvoid(InstancePtr != NULL);
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Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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Xil_AssertNonvoid(XDp_GetCoreType(InstancePtr) == XDP_TX);
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Xil_AssertNonvoid(VcId >= 0);
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Xil_AssertNonvoid((Ts >= 0) && (Ts <= 64));
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Xil_AssertNonvoid(Ts <= 64);
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/* Clear the VC payload ID table updated bit. */
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AuxData[0] = 0x1;
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@ -1493,7 +1492,6 @@ u32 XDp_TxAllocatePayloadVcIdTable(XDp *InstancePtr, u8 VcId, u8 Ts)
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u32 XDp_TxClearPayloadVcIdTable(XDp *InstancePtr)
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{
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u32 Status;
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u8 Index;
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/* Verify arguments. */
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Xil_AssertNonvoid(InstancePtr != NULL);
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@ -1750,8 +1748,6 @@ u32 XDp_TxSendSbMsgRemoteIicWrite(XDp *InstancePtr, u8 LinkCountTotal,
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Xil_AssertNonvoid(XDp_GetCoreType(InstancePtr) == XDP_TX);
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Xil_AssertNonvoid(LinkCountTotal > 0);
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Xil_AssertNonvoid((RelativeAddress != NULL) || (LinkCountTotal == 1));
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Xil_AssertNonvoid(IicDeviceId <= 0xFF);
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Xil_AssertNonvoid(BytesToWrite <= 0xFF);
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Xil_AssertNonvoid(WriteData != NULL);
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Msg.FragmentNum = 0;
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@ -1842,8 +1838,6 @@ u32 XDp_TxSendSbMsgRemoteIicRead(XDp *InstancePtr, u8 LinkCountTotal,
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Xil_AssertNonvoid(XDp_GetCoreType(InstancePtr) == XDP_TX);
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Xil_AssertNonvoid(LinkCountTotal > 0);
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Xil_AssertNonvoid((RelativeAddress != NULL) || (LinkCountTotal == 1));
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Xil_AssertNonvoid(IicDeviceId <= 0xFF);
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Xil_AssertNonvoid(BytesToRead <= 0xFF);
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Xil_AssertNonvoid(ReadData != NULL);
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Msg.FragmentNum = 0;
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@ -3111,7 +3105,7 @@ static void XDp_RxAllocatePayload(XDp *InstancePtr, XDp_SidebandMsg *Msg)
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u8 StreamId;
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u8 StartTs;
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u8 NumTs;
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u8 PbnReq;
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u8 PbnReq = 0;
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PayloadTable = &InstancePtr->RxInstance.Topology.PayloadTable[0];
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