stv0g/embeddedsw
1
0
Fork 0
Code Issues Pull requests Releases Wiki Activity

vtc: Modified vtc_v7_0 source files.

Browse source 
Added interlaced and progressive mode switching functionality.
Removed XVtc_RegUpdate as there were 2 APIS with same functionality
provided backward compatibility.

Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
This commit is contained in:
VNSL Durga 2015-02-25 14:48:59 +05:30 • committed by Nava kishore Manne
parent 57fe691a62
commit 76c56a17d6
3 changed files with 38 additions and 25 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

27
XilinxProcessorIPLib/drivers/vtc/src/xvtc.c
View file

@ -151,6 +151,10 @@
* XVtc_GetVersion.
* Modified return type of XVtc_GetVersion from
* void to u32.
* 7.0 vns 25/02/15 Added progressive and interlaced mode switching feature.
* Modified XVtc_SetGenerator, XVtc_GetGenerator,
* XVtc_GetDetector, XVtc_ConvTiming2Signal and
* XVtc_ConvSignal2Timing APIs
* </pre>
*
******************************************************************************/
@ -1360,6 +1364,11 @@ void XVtc_SetGenerator(XVtc *InstancePtr, XVtc_Signal *SignalCfgPtr)
RegValue = (((SCPtr->V0ChromaStart - SCPtr->V0ActiveStart) <<
XVTC_ENC_CPARITY_SHIFT) &
XVTC_ENC_CPARITY_MASK) | RegValue;
RegValue &= ~XVTC_ENC_PROG_MASK;
RegValue |= (SCPtr->Interlaced << XVTC_ENC_PROG_SHIFT) &
XVTC_ENC_PROG_MASK;
XVtc_WriteReg(InstancePtr->Config.BaseAddress,
XVTC_GFENC_OFFSET, RegValue);
@ -1432,6 +1441,11 @@ void XVtc_SetGenerator(XVtc *InstancePtr, XVtc_Signal *SignalCfgPtr)
RegValue = (((SCPtr->V0ChromaStart - SCPtr->V0ActiveStart) <<
XVTC_ENC_CPARITY_SHIFT)
& XVTC_ENC_CPARITY_MASK) | RegValue;
RegValue &= ~XVTC_ENC_PROG_MASK;
RegValue |= (SCPtr->Interlaced << XVTC_ENC_PROG_SHIFT) &
XVTC_ENC_PROG_MASK;
XVtc_WriteReg(InstancePtr->Config.BaseAddress,
XVTC_GFENC_OFFSET, RegValue);
@ -1526,7 +1540,7 @@ void XVtc_GetGenerator(XVtc *InstancePtr, XVtc_Signal *SignalCfgPtr)
SCPtr->V1ChromaStart = (((RegValue & XVTC_ENC_CPARITY_MASK) >>
XVTC_ENC_CPARITY_SHIFT) + (SCPtr->V1Total - r_vactive - 1)) & XVTC_SB_START_MASK;
SCPtr->Interlaced = (RegValue & XVTC_ENC_PROG_MASK) >> XVTC_ENC_PROG_SHIFT;
SCPtr->HFrontPorchStart = 0;
SCPtr->V0FrontPorchStart = 0;
}
@ -1577,7 +1591,7 @@ void XVtc_GetGenerator(XVtc *InstancePtr, XVtc_Signal *SignalCfgPtr)
XVTC_ENC_CPARITY_SHIFT)) & XVTC_SB_START_MASK;
SCPtr->V1ChromaStart = (((RegValue & XVTC_ENC_CPARITY_MASK) >>
XVTC_ENC_CPARITY_SHIFT)) & XVTC_SB_START_MASK;
SCPtr->Interlaced = (RegValue & XVTC_ENC_PROG_MASK) >> XVTC_ENC_PROG_SHIFT;
SCPtr->HActiveStart = 0;
SCPtr->V0ActiveStart = 0;
@ -1679,6 +1693,7 @@ void XVtc_GetDetector(XVtc *InstancePtr, XVtc_Signal *SignalCfgPtr)
SCPtr->V1ChromaStart = (((RegValue & XVTC_ENC_CPARITY_MASK) >>
XVTC_ENC_CPARITY_SHIFT) +
(SCPtr->V1Total - r_vactive - 1)) & XVTC_SB_START_MASK;
SCPtr->Interlaced = (RegValue & XVTC_ENC_PROG_MASK) >> XVTC_ENC_PROG_SHIFT;
SCPtr->HFrontPorchStart = 0;
SCPtr->V0FrontPorchStart = 0;
@ -1734,7 +1749,7 @@ void XVtc_GetDetector(XVtc *InstancePtr, XVtc_Signal *SignalCfgPtr)
SCPtr->V1ChromaStart = (((RegValue & XVTC_ENC_CPARITY_MASK) >>
XVTC_ENC_CPARITY_SHIFT)) & XVTC_SB_START_MASK;
SCPtr->Interlaced = (RegValue & XVTC_ENC_PROG_MASK) >> XVTC_ENC_PROG_SHIFT;
SCPtr->HActiveStart = 0;
SCPtr->V0ActiveStart = 0;
@ -2151,6 +2166,7 @@ void XVtc_ConvTiming2Signal(XVtc *InstancePtr, XVtc_Timing *TimingPtr,
SignalCfgPtr->V1Total =
SignalCfgPtr->V1BackPorchStart +
TimingPtr->V1BackPorch;
SignalCfgPtr->Interlaced = 1;
/* Align to H blank */
HOffPtr->V1BlankHoriStart = SignalCfgPtr->HFrontPorchStart;
@ -2174,6 +2190,7 @@ void XVtc_ConvTiming2Signal(XVtc *InstancePtr, XVtc_Timing *TimingPtr,
SignalCfgPtr->V1BackPorchStart =
SignalCfgPtr->V0BackPorchStart;
SignalCfgPtr->V1Total = SignalCfgPtr->V0Total;
SignalCfgPtr->Interlaced = 0;
HOffPtr->V1BlankHoriStart = HOffPtr->V0BlankHoriStart;
HOffPtr->V1BlankHoriEnd = HOffPtr->V0BlankHoriEnd;
@ -2254,10 +2271,10 @@ void XVtc_ConvSignal2Timing(XVtc *InstancePtr, XVtc_Signal *SignalCfgPtr,
SignalCfgPtr->V1BackPorchStart;
/* Interlaced */
if ((SignalCfgPtr->V1Total != 0x0) &&
(SignalCfgPtr->V1Total != SignalCfgPtr->V0Total)) {
if (SignalCfgPtr->Interlaced == 1) {
TimingPtr->Interlaced = 1;
}
}
/*****************************************************************************/

34
XilinxProcessorIPLib/drivers/vtc/src/xvtc.h
View file

@ -257,6 +257,10 @@
* 6.1 adk 23/08/14 Implemented XVtc_SelfTest in
* xvtc_selftest.c.
* Modified prototype of XVtc_GetVersion API.
* 7.0 vns 02/25/15 Added Interlaced field to XVtc_Signal structure,
* Removed XVtc_RegUpdate as there are is one more API,
* XVtc_RegUpdateEnable with same functionality but
* provided backward compatability.
*
* Modifications from xvtc.c file are:
* Modified HActiveVideo value to 1920 for
@ -265,6 +269,10 @@
* XVtc_GetVersion.
* Modified return type of XVtc_GetVersion from
* void to u32.
* Added progressive and interlaced mode switching feature.
* Modified XVtc_SetGenerator, XVtc_GetGenerator,
* XVtc_GetDetector, XVtc_ConvTiming2Signal and
* XVtc_ConvSignal2Timing APIs
*
* Modifications from xvtc_hw.h file are:
* Removed XVTC_ERR_FIL_MASK macro because it is not
@ -444,6 +452,7 @@ typedef struct {
* Count (Field 1) */
u16 V1ChromaStart; /**< Active Chroma Start Line Count
* (Field 1) */
u8 Interlaced; /**< Interlaced / Progressive video */
} XVtc_Signal;
/**
@ -625,26 +634,6 @@ typedef struct {
XVtc_ReadReg((InstancePtr)->Config.BaseAddress, \
(XVTC_CTL_OFFSET)) | (XVTC_CTL_SE_MASK))
/*****************************************************************************/
/**
*
* This function macro enables updating timing registers at the end of each
* Generator frame. (DEPRECATED - replaced with XVtc_RegUpdateEnable).
*
* @param InstancePtr is a pointer to the VTC core instance to be
* worked on.
*
* @return None.
*
* @note C-style signature:
* void XVtc_RegUpdate(XVtc *InstancePtr)
*
******************************************************************************/
#define XVtc_RegUpdate(InstancePtr) \
XVtc_WriteReg((InstancePtr)->Config.BaseAddress, (XVTC_CTL_OFFSET), \
XVtc_ReadReg((InstancePtr)->Config.BaseAddress, \
(XVTC_CTL_OFFSET)) | (XVTC_CTL_RU_MASK))
/*****************************************************************************/
/**
*
@ -861,6 +850,11 @@ typedef struct {
******************************************************************************/
#define XVtc_Sync_Reset XVtc_SyncReset
/** @name Compatibility Macros
* @{
*/
#define XVtc_RegUpdate XVtc_RegUpdateEnable
/*@}*/
/************************** Function Prototypes ******************************/
/* Initialization and control functions in xvtc.c */

2
XilinxProcessorIPLib/drivers/vtc/src/xvtc_hw.h
View file

@ -455,6 +455,8 @@ extern "C" {
#define XVTC_ENC_FPARITY_MASK 0x00000080 /**< Field Parity Mask */
#define XVTC_ENC_PROG_MASK 0x00000040 /**< Progressive/Interlaced
* Mask */
#define XVTC_ENC_PROG_SHIFT 6 /**< Progressive/Interlaced
* Shift */
#define XVTC_ENC_GACLS_MASK 0x00000001 /**< Generator Active Chroma
* Line Skip/parity Mask */
/*@}*/