stv0g/embeddedsw
1
0
Fork 0
Code Issues Pull requests Releases Wiki Activity

uartns550_v3_3: Updated the Modification History

Browse source 
This patch updates the Modification history.

Signed-off-by: naga sureshkumar relli <nagasure@xilinx.com>
This commit is contained in:
naga sureshkumar relli 2015-05-21 12:37:31 +05:30 • committed by Nava kishore Manne
parent 6574c9ffbd
commit 784faa52e1
4 changed files with 6 additions and 16 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

9
XilinxProcessorIPLib/drivers/uartns550/src/xuartns550.c
View file

@ -62,13 +62,8 @@
* XUartNs550_CfgInitialize function. Removed compiler
* warnings for unused variables in the
* XUartNs550_StubHandler.
* 3.3 nsk 04/13/15 Clock Divisor Enhancement. i.e when odd clock given
* as input clock, say 31.725MHz and Baud as 1000000
* then divisor = (31725000) / (1000000 * 16), This returns
* 1.9828, since this is integer math, it becomes 1.
* Which is almost half of the necessary value. so
* we are truncating it to nearest integer. in our
* case 1.9828 rounded to 2.
* 3.3 nsk 04/13/15 Fixed Clock Divisor Enhancement.
* (CR 857013)
* </pre>
*
*****************************************************************************/

3
XilinxProcessorIPLib/drivers/uartns550/src/xuartns550.h
View file

@ -159,7 +159,8 @@
* 3.2 adk 15/10/14 Fixed CR:824444 changes are made in the example file
* xuartns550_intr_example.c.
* 3.2 adk 15/10/14 Fixed CR:826435 changes are made in the driver tcl file.
* 3.3 nsk 04/13/15 Fixed CR:857013 changes are made in xuartns550.c
* 3.3 nsk 04/13/15 Fixed CR:857013 changes are made in xuartns550.c and
* xuartns550_l.c.
* </pre>
*
*****************************************************************************/

9
XilinxProcessorIPLib/drivers/uartns550/src/xuartns550_l.c
View file

@ -49,13 +49,8 @@
* 2.00a ktn 10/20/09 Converted all register accesses to 32 bit access.
* Updated to use HAL Processor APIs. _m is removed from the
* name of all the macro definitions.
* 3.3 nsk 04/13/15 Clock Divisor Enhancement. i.e when odd clock given
* as inputclock, say 31.725MHz and Baud as 1000000
* then divisor = (31725000) / (1000000 * 16), This returns
* 1.9828, since this is integer math, it becomes 1.
* Which is almost half of the necessary value. so
* we are truncating it to nearest integer. in our
* case 1.9828 rounded to 2.
* 3.3 nsk 04/13/15 Fixed Clock Divisor Enhancement.
* (CR 857013)
* </pre>
*
******************************************************************************/

1
XilinxProcessorIPLib/drivers/uartns550/src/xuartns550_l.h
View file

@ -50,7 +50,6 @@
* 2.00a ktn 10/20/09 Converted all register accesses to 32 bit access.
* Updated to use HAL Processor APIs. _m is removed from the
* name of all the macro definitions.
* 3.3 nsk 04/13/15 Fixed CR:857013 changes are made in xuartns550_l.c
* </pre>
*
******************************************************************************/