stv0g/embeddedsw
1
0
Fork 0
Code Issues Pull requests Releases Wiki Activity

dp: Export IP configuration parameter for the DisplayPort core type - TX or RX.

Browse source 
Exporting the C_FLOW_DIRECTION configuration parameter.
XDp_Config's IsRx member specifies that the core is an RX if = 0, TX if = 1.

Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
This commit is contained in:
Andrei-Liviu Simion 2015-01-09 13:54:30 -08:00 • committed by Nava kishore Manne
parent 204d93a1fe
commit 81cb2fe913
3 changed files with 29 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
XilinxProcessorIPLib/drivers/dp/data/dp.tcl
View file

@ -30,9 +30,9 @@
##
##*****************************************************************************/
proc generate {drv_handle} {
xdefine_include_file $drv_handle "xparameters.h" "XDp" "NUM_INSTANCES" "DEVICE_ID" "C_BASEADDR" "C_LANE_COUNT" "C_LINK_RATE" "C_MAX_BITS_PER_COLOR" "C_QUAD_PIXEL_ENABLE" "C_DUAL_PIXEL_ENABLE" "C_YCRCB_ENABLE" "C_YONLY_ENABLE" "C_GT_DATAWIDTH" "C_SECONDARY_SUPPORT" "C_AUDIO_CHANNELS" "C_MST_ENABLE" "C_NUMBER_OF_MST_STREAMS" "C_PROTOCOL_SELECTION" "S_AXI_ACLK"
xdefine_config_file $drv_handle "xdptx_g.c" "XDp" "DEVICE_ID" "C_BASEADDR" "S_AXI_ACLK" "C_LANE_COUNT" "C_LINK_RATE" "C_MAX_BITS_PER_COLOR" "C_QUAD_PIXEL_ENABLE" "C_DUAL_PIXEL_ENABLE" "C_YCRCB_ENABLE" "C_YONLY_ENABLE" "C_GT_DATAWIDTH" "C_SECONDARY_SUPPORT" "C_AUDIO_CHANNELS" "C_MST_ENABLE" "C_NUMBER_OF_MST_STREAMS" "C_PROTOCOL_SELECTION"
xdefine_canonical_xpars $drv_handle "xparameters.h" "XDp" "NUM_INSTANCES" "DEVICE_ID" "C_BASEADDR" "C_LANE_COUNT" "C_LINK_RATE" "C_MAX_BITS_PER_COLOR" "C_QUAD_PIXEL_ENABLE" "C_DUAL_PIXEL_ENABLE" "C_YCRCB_ENABLE" "C_YONLY_ENABLE" "C_GT_DATAWIDTH" "C_SECONDARY_SUPPORT" "C_AUDIO_CHANNELS" "C_MST_ENABLE" "C_NUMBER_OF_MST_STREAMS" "C_PROTOCOL_SELECTION" "S_AXI_ACLK"
xdefine_include_file $drv_handle "xparameters.h" "XDp" "NUM_INSTANCES" "DEVICE_ID" "C_BASEADDR" "C_LANE_COUNT" "C_LINK_RATE" "C_MAX_BITS_PER_COLOR" "C_QUAD_PIXEL_ENABLE" "C_DUAL_PIXEL_ENABLE" "C_YCRCB_ENABLE" "C_YONLY_ENABLE" "C_GT_DATAWIDTH" "C_SECONDARY_SUPPORT" "C_AUDIO_CHANNELS" "C_MST_ENABLE" "C_NUMBER_OF_MST_STREAMS" "C_PROTOCOL_SELECTION" "C_FLOW_DIRECTION" "S_AXI_ACLK"
xdefine_config_file $drv_handle "xdptx_g.c" "XDp" "DEVICE_ID" "C_BASEADDR" "S_AXI_ACLK" "C_LANE_COUNT" "C_LINK_RATE" "C_MAX_BITS_PER_COLOR" "C_QUAD_PIXEL_ENABLE" "C_DUAL_PIXEL_ENABLE" "C_YCRCB_ENABLE" "C_YONLY_ENABLE" "C_GT_DATAWIDTH" "C_SECONDARY_SUPPORT" "C_AUDIO_CHANNELS" "C_MST_ENABLE" "C_NUMBER_OF_MST_STREAMS" "C_PROTOCOL_SELECTION" "C_FLOW_DIRECTION"
xdefine_canonical_xpars $drv_handle "xparameters.h" "XDp" "NUM_INSTANCES" "DEVICE_ID" "C_BASEADDR" "C_LANE_COUNT" "C_LINK_RATE" "C_MAX_BITS_PER_COLOR" "C_QUAD_PIXEL_ENABLE" "C_DUAL_PIXEL_ENABLE" "C_YCRCB_ENABLE" "C_YONLY_ENABLE" "C_GT_DATAWIDTH" "C_SECONDARY_SUPPORT" "C_AUDIO_CHANNELS" "C_MST_ENABLE" "C_NUMBER_OF_MST_STREAMS" "C_PROTOCOL_SELECTION" "C_FLOW_DIRECTION" "S_AXI_ACLK"
}
#

24
XilinxProcessorIPLib/drivers/dp/src/xdp.h
View file

@ -244,6 +244,8 @@ typedef struct {
u8 DpProtocol; /**< The DisplayPort protocol version that this
core instance is configured for.
0 = v1.1a, 1 = v1.2. */
u8 IsRx; /**< The type of DisplayPort core.
0 = TX, 1 = RX. */
} XDp_Config;
/**************************** Function Prototypes *****************************/
@ -251,6 +253,28 @@ typedef struct {
/* xdp_sinit.c: Configuration extraction function.*/
XDp_Config *XDp_LookupConfig(u16 DeviceId);
/******************* Macros (Inline Functions) Definitions ********************/
#define XDP_TX 0
#define XDP_RX 1
/******************************************************************************/
/**
* This is function determines whether the DisplayPort core that the
* configuration structure represents is a transmitter (TX) or a receiver (RX).
*
* @param ConfigPtr is a pointer to the DisplayPort core's configuration
* structure.
*
* @return XDP_RX if the configuration structure is for a core of type RX.
* XDP_TX if the configuration structure is for a core of type TX.
*
* @note C-style signature:
* u32 XDp_CfgGetCoreType(XDp_Config *ConfigPtr)
*
*******************************************************************************/
#define XDp_CfgGetCoreType(ConfigPtr) ((ConfigPtr)->IsRx ? XDP_RX : XDP_TX)
/******************************* Compatibility ********************************/
#define XDptx_LookupConfig XDp_LookupConfig

2
XilinxProcessorIPLib/drivers/dp/src/xdptx.c
View file

@ -277,6 +277,8 @@ void XDptx_CfgInitialize(XDptx *InstancePtr, XDp_Config *ConfigPtr,
InstancePtr->Config.DpProtocol = ConfigPtr->DpProtocol;
InstancePtr->Config.IsRx = ConfigPtr->IsRx;
/* Set the DisplayPort TX's voltage swing and pre-emphasis levels to
* their defaults. */
XDptx_CfgTxVsOffset(InstancePtr, XDPTX_VS_LEVEL_OFFSET);