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dp: rx: Fix interrupt masking.

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The interrupt mask and interrupt cause registers are independent. The interrupt
handler has been modified to ignore interrupts that have been masked out.

Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
This commit is contained in:
Andrei-Liviu Simion 2015-08-04 01:38:18 -07:00 • committed by Nava kishore Manne
parent 0ebb5dbdfe
commit 83cfd59989
1 changed files with 5 additions and 2 deletions
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7
XilinxProcessorIPLib/drivers/dp/src/xdp_intr.c
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@ -139,7 +139,7 @@ void XDp_RxInterruptEnable(XDp *InstancePtr, u32 Mask)
Xil_AssertVoid(XDp_GetCoreType(InstancePtr) == XDP_RX);
MaskVal = XDp_ReadReg(InstancePtr->Config.BaseAddr,
XDP_RX_INTERRUPT_CAUSE);
XDP_RX_INTERRUPT_MASK);
MaskVal &= ~Mask;
XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_RX_INTERRUPT_MASK,
MaskVal);
@ -168,7 +168,7 @@ void XDp_RxInterruptDisable(XDp *InstancePtr, u32 Mask)
Xil_AssertVoid(XDp_GetCoreType(InstancePtr) == XDP_RX);
MaskVal = XDp_ReadReg(InstancePtr->Config.BaseAddr,
XDP_RX_INTERRUPT_CAUSE);
XDP_RX_INTERRUPT_MASK);
MaskVal |= Mask;
XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_RX_INTERRUPT_MASK,
MaskVal);
@ -1032,6 +1032,9 @@ static void XDp_RxInterruptHandler(XDp *InstancePtr)
* Note: XDP_RX_INTERRUPT_CAUSE is a RC (read-clear) register. */
IntrStatus = XDp_ReadReg(InstancePtr->Config.BaseAddr,
XDP_RX_INTERRUPT_CAUSE);
/* Mask out required interrupts. */
IntrStatus &= ~XDp_ReadReg(InstancePtr->Config.BaseAddr,
XDP_RX_INTERRUPT_MASK);
/* Training pattern 1 has started. */
if (IntrStatus & XDP_RX_INTERRUPT_CAUSE_TP1_MASK) {