dp: rx: Fix interrupt masking.
The interrupt mask and interrupt cause registers are independent. The interrupt handler has been modified to ignore interrupts that have been masked out. Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
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1 changed files with 5 additions and 2 deletions
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@ -139,7 +139,7 @@ void XDp_RxInterruptEnable(XDp *InstancePtr, u32 Mask)
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Xil_AssertVoid(XDp_GetCoreType(InstancePtr) == XDP_RX);
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MaskVal = XDp_ReadReg(InstancePtr->Config.BaseAddr,
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XDP_RX_INTERRUPT_CAUSE);
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XDP_RX_INTERRUPT_MASK);
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MaskVal &= ~Mask;
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XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_RX_INTERRUPT_MASK,
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MaskVal);
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@ -168,7 +168,7 @@ void XDp_RxInterruptDisable(XDp *InstancePtr, u32 Mask)
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Xil_AssertVoid(XDp_GetCoreType(InstancePtr) == XDP_RX);
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MaskVal = XDp_ReadReg(InstancePtr->Config.BaseAddr,
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XDP_RX_INTERRUPT_CAUSE);
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XDP_RX_INTERRUPT_MASK);
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MaskVal |= Mask;
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XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_RX_INTERRUPT_MASK,
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MaskVal);
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@ -1032,6 +1032,9 @@ static void XDp_RxInterruptHandler(XDp *InstancePtr)
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* Note: XDP_RX_INTERRUPT_CAUSE is a RC (read-clear) register. */
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IntrStatus = XDp_ReadReg(InstancePtr->Config.BaseAddr,
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XDP_RX_INTERRUPT_CAUSE);
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/* Mask out required interrupts. */
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IntrStatus &= ~XDp_ReadReg(InstancePtr->Config.BaseAddr,
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XDP_RX_INTERRUPT_MASK);
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/* Training pattern 1 has started. */
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if (IntrStatus & XDP_RX_INTERRUPT_CAUSE_TP1_MASK) {
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