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dp: rx: Optimized initialization.

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RX initialization is not dependent on PLL and reset checks.
- Training will not be initiated until the RX is ready.

The clock is transmitted only once the cable is connected.
- This means that the CPLLs will never lock if no cable is plugged
in resulting in DP RX core initialization time out.

Moved core and interrupt mask enables towards end of function.

Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
This commit is contained in:
Andrei-Liviu Simion 2015-08-04 01:38:08 -07:00 • committed by Nava kishore Manne
parent 3b39183e40
commit 8518d9a3da
1 changed files with 6 additions and 39 deletions
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45
XilinxProcessorIPLib/drivers/dp/src/xdp.c
View file

@ -1838,8 +1838,6 @@ static u32 XDp_TxInitialize(XDp *InstancePtr)
*******************************************************************************/
static u32 XDp_RxInitialize(XDp *InstancePtr)
{
u32 Status;
/* Disable the main link. */
XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_RX_LINK_ENABLE, 0x0);
@ -1856,20 +1854,6 @@ static u32 XDp_RxInitialize(XDp *InstancePtr)
XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_RX_PHY_CONFIG,
XDP_RX_PHY_CONFIG_GTRX_RESET_MASK);
/* Wait until all lane CPLLs have locked. */
if (InstancePtr->Config.MaxLaneCount > 2) {
Status = XDp_WaitPhyReady(InstancePtr,
XDP_RX_PHY_STATUS_PLL_LANE0_1_LOCK_MASK |
XDP_RX_PHY_STATUS_PLL_LANE2_3_LOCK_MASK);
}
else {
Status = XDp_WaitPhyReady(InstancePtr,
XDP_RX_PHY_STATUS_PLL_LANE0_1_LOCK_MASK);
}
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/* Remove the reset from the PHY and configure to issue reset after
* every training iteration, link rate change, and start of training
* pattern. */
@ -1879,26 +1863,6 @@ static u32 XDp_RxInitialize(XDp *InstancePtr)
XDP_RX_PHY_CONFIG_RESET_AT_LINK_RATE_CHANGE_MASK |
XDP_RX_PHY_CONFIG_RESET_AT_TP1_START_MASK);
/* Wait until the PHY has completed the reset cycle. */
if (InstancePtr->Config.MaxLaneCount > 2) {
Status = XDp_WaitPhyReady(InstancePtr,
XDP_RX_PHY_STATUS_ALL_LANES_READY_MASK |
XDP_RX_PHY_STATUS_PLL_FABRIC_LOCK_MASK |
XDP_RX_PHY_STATUS_RX_CLK_LOCK_MASK);
}
else {
Status = XDp_WaitPhyReady(InstancePtr,
XDP_RX_PHY_STATUS_LANES_0_1_READY_MASK |
XDP_RX_PHY_STATUS_PLL_FABRIC_LOCK_MASK |
XDP_RX_PHY_STATUS_RX_CLK_LOCK_MASK);
}
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/* Set the interrupt masks. */
XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_RX_INTERRUPT_MASK, 0x0);
if (InstancePtr->Config.MstSupport) {
XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_RX_MST_CAP,
XDP_RX_MST_CAP_ENABLE_MASK |
@ -1919,9 +1883,6 @@ static u32 XDp_RxInitialize(XDp *InstancePtr)
XDP_RX_SINK_COUNT, 0x1);
}
/* Enable the RX core. */
XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_RX_LINK_ENABLE, 0x1);
/* Set other user parameters. */
XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_RX_MIN_VOLTAGE_SWING,
0x01);
@ -1937,6 +1898,12 @@ static u32 XDp_RxInitialize(XDp *InstancePtr)
XDp_RxSetLaneCount(InstancePtr,
InstancePtr->RxInstance.LinkConfig.LaneCount);
/* Set the interrupt masks. */
XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_RX_INTERRUPT_MASK, 0x0);
/* Enable the RX core. */
XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_RX_LINK_ENABLE, 0x1);
/* Enable the display timing generator. */
XDp_RxDtgEn(InstancePtr);