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dp: tx: Updated PHY status done checks with single lane.

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Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Acked-by: Srikanth Vemula <svemula@xilinx.com>
This commit is contained in:
Andrei-Liviu Simion 2015-09-02 01:05:17 -07:00 • committed by Nava kishore Manne
parent 2099c0ae3e
commit 86d2cde9d0
2 changed files with 24 additions and 29 deletions
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31
XilinxProcessorIPLib/drivers/dp/src/xdp.c
View file

@ -1295,14 +1295,8 @@ void XDp_TxResetPhy(XDp *InstancePtr, u32 Reset)
XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_TX_PHY_CONFIG, PhyVal);
/* Wait for the PHY to be ready. */
if (InstancePtr->Config.MaxLaneCount > 2) {
XDp_WaitPhyReady(InstancePtr,
XDP_TX_PHY_STATUS_ALL_LANES_READY_MASK);
}
else {
XDp_WaitPhyReady(InstancePtr,
XDP_TX_PHY_STATUS_LANES_0_1_READY_MASK);
}
XDp_WaitPhyReady(InstancePtr, XDP_TX_PHY_STATUS_LANES_READY_MASK(
InstancePtr->Config.MaxLaneCount));
XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_TX_ENABLE, 0x1);
}
@ -1878,14 +1872,8 @@ static u32 XDp_TxInitialize(XDp *InstancePtr)
XDp_WriteReg(ConfigPtr->BaseAddr, XDP_TX_PHY_CONFIG, RegVal);
/* Wait for the PHY to be ready. */
if (ConfigPtr->MaxLaneCount > 2) {
Status = XDp_WaitPhyReady(InstancePtr,
XDP_TX_PHY_STATUS_ALL_LANES_READY_MASK);
}
else {
Status = XDp_WaitPhyReady(InstancePtr,
XDP_TX_PHY_STATUS_LANES_0_1_READY_MASK);
}
Status = XDp_WaitPhyReady(InstancePtr,
XDP_TX_PHY_STATUS_LANES_READY_MASK(ConfigPtr->MaxLaneCount));
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
@ -3251,14 +3239,9 @@ static u32 XDp_TxSetClkSpeed(XDp *InstancePtr, u32 Speed)
}
/* Wait until the PHY is ready. */
if (InstancePtr->Config.MaxLaneCount > 2) {
Status = XDp_WaitPhyReady(InstancePtr,
XDP_TX_PHY_STATUS_ALL_LANES_READY_MASK);
}
else {
Status = XDp_WaitPhyReady(InstancePtr,
XDP_TX_PHY_STATUS_LANES_0_1_READY_MASK);
}
Status = XDp_WaitPhyReady(InstancePtr,
XDP_TX_PHY_STATUS_LANES_READY_MASK(
InstancePtr->Config.MaxLaneCount));
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}

22
XilinxProcessorIPLib/drivers/dp/src/xdp_hw.h
View file

@ -689,9 +689,10 @@
#define XDP_TX_PE_LEVEL_2 0x14 /**< Pre-emphasis level 2. */
#define XDP_TX_PE_LEVEL_3 0x1B /**< Pre-emphasis level 3. */
/* 0x280: PHY_STATUS */
#define XDP_TX_PHY_STATUS_RESET_LANE_0_1_DONE_MASK \
0x00000003 /**< Reset done for lanes
0 and 1. */
#define XDP_TX_PHY_STATUS_RESET_LANE_0_DONE_MASK \
0x00000001 /**< Reset done for lane 0. */
#define XDP_TX_PHY_STATUS_RESET_LANE_1_DONE_MASK \
0x00000002 /**< Reset done for lane 1. */
#define XDP_TX_PHY_STATUS_RESET_LANE_2_3_DONE_MASK \
0x0000000C /**< Reset done for lanes
2 and 3. */
@ -747,10 +748,21 @@
#define XDP_TX_PHY_STATUS_TX_ERROR_LANE_3_SHIFT \
30 /**< Shift bits for TX error on
lane 3. */
#define XDP_TX_PHY_STATUS_LANE_0_READY_MASK \
XDP_TX_PHY_STATUS_RESET_LANE_0_DONE_MASK \
XDP_TX_PHY_STATUS_PLL_LANE0_1_LOCK_MASK /**< Lane 0 is ready. */
#define XDP_TX_PHY_STATUS_LANES_0_1_READY_MASK \
0x00000013 /**< Lanes 0 and 1 are ready. */
XDP_TX_PHY_STATUS_LANE_0_READY_MASK \
XDP_TX_PHY_STATUS_RESET_LANE_1_DONE_MASK /**< Lanes 0,1 are ready. */
#define XDP_TX_PHY_STATUS_ALL_LANES_READY_MASK \
0x0000003F /**< All lanes are ready. */
XDP_TX_PHY_STATUS_RESET_LANE_2_3_DONE_MASK \
XDP_TX_PHY_STATUS_PLL_LANE2_3_LOCK_MASK /**< Lanes 0,1,2,3 are ready. */
#define XDP_TX_PHY_STATUS_LANES_READY_MASK(n) \
((n > 2) ? XDP_TX_PHY_STATUS_ALL_LANES_READY_MASK : \
(n == 2) ? XDP_TX_PHY_STATUS_LANES_0_1_READY_MASK : \
XDP_TX_PHY_STATUS_LANE_0_READY_MASK) /**< Macro for lanes ready mask
with number of lanes as
the argument. */
/* 0x2A0: XDP_TX_GT_DRP_COMMAND */
#define XDP_TX_GT_DRP_COMMAND_DRP_ADDR_MASK \
0x000F /**< DRP address. */