v_tpg: Bug fix for vidout lock monitor read mechanism
Fixed the read API for video lock monitor to read from peripheral. Update example design to align with example design update in hw Signed-off-by: Rohit Consul <rohit.consul@xilinx.com> Acked-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
This commit is contained in:
Rohit Consul
Nava kishore Manne
parent
0c17eca07b
commit
86f6445653
1 changed files with 88 additions and 61 deletions
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@ -43,7 +43,7 @@
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* Ver Who Date Changes
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* ----- ---- -------- -------------------------------------------------------
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* 1.00 vyc 09/11/15 Initial Release
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* 1.10 rco 10/05/15 Update to support multiple PPC configurations
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* </pre>
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*
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******************************************************************************/
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@ -121,6 +121,7 @@ int driverInit()
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void videoIpConfig(XVidC_VideoMode videoMode)
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{
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XVidC_VideoTiming const *timing = XVidC_GetTimingInfo(videoMode);
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u16 PixelsPerClk;
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XV_tpg_Set_height(&tpg, timing->VActive);
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XV_tpg_Set_width(&tpg, timing->HActive);
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@ -141,10 +142,12 @@ void videoIpConfig(XVidC_VideoMode videoMode)
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XV_tpg_Set_passthruEndY(&tpg1, timing->VActive);
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XV_tpg_WriteReg(tpg1_Config->BaseAddress, XV_TPG_CTRL_ADDR_AP_CTRL, 0x81);
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vtc_timing.HActiveVideo = timing->HActive/2;
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vtc_timing.HFrontPorch = timing->HFrontPorch/2;
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vtc_timing.HSyncWidth = timing->HSyncWidth/2;
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vtc_timing.HBackPorch = timing->HBackPorch/2;
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PixelsPerClk = tpg1.Config.PixPerClk;
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vtc_timing.HActiveVideo = timing->HActive/PixelsPerClk;
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vtc_timing.HFrontPorch = timing->HFrontPorch/PixelsPerClk;
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vtc_timing.HSyncWidth = timing->HSyncWidth/PixelsPerClk;
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vtc_timing.HBackPorch = timing->HBackPorch/PixelsPerClk;
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vtc_timing.HSyncPolarity = timing->HSyncPolarity;
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vtc_timing.VActiveVideo = timing->VActive;
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vtc_timing.V0FrontPorch = timing->F0PVFrontPorch;
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@ -168,28 +171,39 @@ int videoClockConfig(XVidC_VideoMode videoMode)
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u32 clock_config_reg_2;
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u32 timeout;
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u32 lock;
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u16 PixelsPerClk, mode_index;
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const int ClkOut_Frac[3][XVIDC_PPC_NUM_SUPPORTED] =
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{ {250, 500, 0 }, //1080p
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{125, 250, 500}, //4K30
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{0, 125, 250} //4K60
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};
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const int ClkOut_Div[3][XVIDC_PPC_NUM_SUPPORTED] =
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{ {6, 12, 25}, //1080p
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{3, 6 , 12}, //4K30
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{0, 3 , 6 } //4K60
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};
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/* Validate TPG Parameters */
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Xil_AssertNonvoid((tpg1.Config.PixPerClk == XVIDC_PPC_1) ||
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(tpg1.Config.PixPerClk == XVIDC_PPC_2) ||
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(tpg1.Config.PixPerClk == XVIDC_PPC_4));
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if(videoMode == XVIDC_VM_1080_60_P)
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{
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CLKOUT0_FRAC = 500;
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CLKOUT0_DIVIDE = 12;
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}
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else if(videoMode == XVIDC_VM_UHD_30_P)
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{
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CLKOUT0_FRAC = 250;
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CLKOUT0_DIVIDE = 6;
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}
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else if(videoMode == XVIDC_VM_UHD_60_P)
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{
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CLKOUT0_FRAC = 125;
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CLKOUT0_DIVIDE = 3;
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}
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else
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{
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print("ERR:: Invalid video mode\r\n");
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return(XST_FAILURE);
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}
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mode_index = ((videoMode == XVIDC_VM_1080_60_P) ? 0 :
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(videoMode == XVIDC_VM_UHD_30_P) ? 1 :
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(videoMode == XVIDC_VM_UHD_60_P) ? 2 : 3);
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if(mode_index > 2)
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{
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xil_printf("ERR:: Video Mode %s not supported\r\n", XVidC_GetVideoModeStr(videoMode));
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return(XST_FAILURE);
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}
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//map PPC to array index
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PixelsPerClk = (tpg1.Config.PixPerClk>>1);
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CLKOUT0_FRAC = ClkOut_Frac[mode_index][PixelsPerClk];
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CLKOUT0_DIVIDE = ClkOut_Div[mode_index][PixelsPerClk];
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clock_config_reg_0 = (1<<26) | (CLKFBOUT_FRAC<<16) | (CLKFBOUT_MULT<<8) | DIVCLK_DIVIDE;
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clock_config_reg_2 = (1<<18) | (CLKOUT0_FRAC<<8) | CLKOUT0_DIVIDE;
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@ -197,7 +211,7 @@ int videoClockConfig(XVidC_VideoMode videoMode)
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VideoClockGen_WriteReg(0x200, clock_config_reg_0);
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VideoClockGen_WriteReg(0x208, clock_config_reg_2);
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MB_Sleep(100);
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MB_Sleep(300);
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lock = VideoClockGen_ReadReg(0x4) & 0x1;
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if(!lock) //check for lock
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@ -227,17 +241,18 @@ void resetIp(void)
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{
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*gpio_hlsIpReset = 0; //reset IPs
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MB_Sleep(100);
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MB_Sleep(300);
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*gpio_hlsIpReset = 1; // release reset
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MB_Sleep(100);
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MB_Sleep(300);
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}
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int main()
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{
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int status;
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XVidC_VideoMode TestMode;
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print("Start test\r\n");
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@ -245,72 +260,84 @@ int main()
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gpio_videoLockMonitor = (u32*)XPAR_VIDEO_LOCK_MONITOR_BASEADDR;
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status = driverInit();
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if(status != XST_SUCCESS)
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{
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if(status != XST_SUCCESS) {
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return(XST_FAILURE);
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}
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resetIp();
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if(*gpio_videoLockMonitor)
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{
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if(*gpio_videoLockMonitor) {
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print("ERR:: Video should not be locked\r\n");
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return(XST_FAILURE);
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}
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videoClockConfig(XVIDC_VM_1080_60_P);
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videoIpConfig(XVIDC_VM_1080_60_P);
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TestMode = XVIDC_VM_1080_60_P;
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xil_printf("\r\nTest: %s\r\n", XVidC_GetVideoModeStr(TestMode));
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status = videoClockConfig(TestMode);
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if(status != XST_SUCCESS) {
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return(XST_FAILURE);
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}
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videoIpConfig(TestMode);
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MB_Sleep(100);
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MB_Sleep(300);
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if(!gpio_videoLockMonitor)
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{
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if(!(*gpio_videoLockMonitor)) {
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print("ERR:: Video Lock failed for 1080P60\r\n");
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return(XST_FAILURE);
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}
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else
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{
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else {
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print("1080P60 passed\r\n");
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}
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resetIp();
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videoClockConfig(XVIDC_VM_UHD_30_P);
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videoIpConfig(XVIDC_VM_UHD_30_P);
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TestMode = XVIDC_VM_UHD_30_P;
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xil_printf("\r\nTest: %s\r\n", XVidC_GetVideoModeStr(TestMode));
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status = videoClockConfig(TestMode);
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if(status != XST_SUCCESS){
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return(XST_FAILURE);
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}
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videoIpConfig(TestMode);
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MB_Sleep(100);
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MB_Sleep(300);
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if(!gpio_videoLockMonitor)
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{
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if(!(*gpio_videoLockMonitor)) {
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print("ERR:: Video Lock failed for 4KP30\r\n");
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return(XST_FAILURE);
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}
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else
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{
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print("4KP30 passed\r\n");
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else {
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print("4KP30 passed\r\n\r\n");
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}
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resetIp();
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/* Run 4k60 Test if supported by HW
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* Check if TPG is configured for 2/4 Pixels/Clock
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* Required to support 4K60
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*/
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if((tpg1.Config.PixPerClk == XVIDC_PPC_2) ||
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(tpg1.Config.PixPerClk == XVIDC_PPC_4)) {
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videoClockConfig(XVIDC_VM_UHD_60_P);
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videoIpConfig(XVIDC_VM_UHD_60_P);
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resetIp();
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MB_Sleep(100);
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TestMode = XVIDC_VM_UHD_60_P;
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xil_printf("\r\nTest: %s\r\n", XVidC_GetVideoModeStr(TestMode));
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status = videoClockConfig(TestMode);
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if(status != XST_SUCCESS) {
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return(XST_FAILURE);
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}
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videoIpConfig(TestMode);
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if(!gpio_videoLockMonitor)
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{
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MB_Sleep(300);
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if(!(*gpio_videoLockMonitor)) {
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print("ERR:: Video Lock failed for 4KP60\r\n");
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return(XST_FAILURE);
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}
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else
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{
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print("4KP60 passed\r\n");
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}
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}
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else {
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print("4KP60 passed\r\n\r\n");
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}
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}
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print("TEST PASS\r\n");
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return 0;
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}
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