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tpg: Added files to tpg_v3_0.

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Added source files, intgration files and selftest example.

Signed-off-by: Durga challa <vnsldurg@xilinx.com>
This commit is contained in:
Durga challa 2014-07-08 18:13:35 +05:30 • committed by Jagannadha Sutradharudu Teki
parent 1d84de041d
commit 898c9b41c8
10 changed files with 3316 additions and 402 deletions
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160
XilinxProcessorIPLib/drivers/tpg/examples/tpg_selftest_example.c Executable file
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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xtpg_selftest_example.c
*
* This file contains an example using the XTpg driver to do self test
* on the device.
*
* @note
*
* None
*
* MODIFICATION HISTORY:
* <pre>
* Ver Who Date Changes
* ----- ------ -------- -----------------------------------------------
* 3.0 adk 01/15/14 First release
*
* </pre>
******************************************************************************/
/***************************** Include Files *********************************/
#include "xtpg.h"
#include "xparameters.h"
#include "xil_printf.h"
/************************** Constant Definitions *****************************/
/*
* The following constants map to the XPAR parameters created in the
* xparameters.h file. They are defined here such that a user can easily
* change all the needed parameters in one place.
*/
#define TPG_DEVICE_ID XPAR_TPG_0_DEVICE_ID /**< TPG Device ID */
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
int XTpgSelfTestExample(u16 DeviceId);
/************************** Variable Definitions *****************************/
XTpg Tpg; /**<Instance of the TPG Device */
/*****************************************************************************/
/**
*
* Main function to call the example.
*
* @return
* - XST_SUCCESS if XTpgSelfTestExample is successful.
* - XST_FAILURE if XTpgSelfTestExample is failed.
*
* @note None
*
******************************************************************************/
int main(void)
{
int Status;
/*
* Run the self test example
*/
Status = XTpgSelfTestExample((u16)TPG_DEVICE_ID);
if (Status != XST_SUCCESS) {
xil_printf("TPG Selftest Example Failed\r\n");
return XST_FAILURE;
}
xil_printf("Successfully ran TPG Selftest Example\r\n");
return XST_SUCCESS;
}
/*****************************************************************************/
/**
*
* This function does a minimal test on the XTpg driver.
*
*
* @param DeviceId is the XPAR_<TPG_instance>_DEVICE_ID value from
* xparameters.h.
*
* @return
* - XST_SUCCESS if successful
* - XST_FAILURE if failed.
*
* @note None
*
******************************************************************************/
int XTpgSelfTestExample(u16 DeviceId)
{
int Status;
XTpg_Config *Config;
/*
* Initialize the TPG driver so that it's ready to use
* Look up the configuration in the config table,
* then initialize it.
*/
Config = XTpg_LookupConfig(DeviceId);
if (NULL == Config) {
return XST_FAILURE;
}
Status = XTpg_CfgInitialize(&Tpg, Config, Config->BaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Perform a self-test to check hardware build.
*/
Status = XTpg_SelfTest(&Tpg);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
return XST_SUCCESS;
}

53
XilinxProcessorIPLib/drivers/tpg/src/tpg.c
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/*****************************************************************************
*
* Copyright (C) 2001 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"),to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
*****************************************************************************/
/**
*
* @file tpg.c
*
* This is the body of the Xilinx Test Pattern Generator
* (tpg) core driver. Most of the driver functionality is implemented as
* macros in the tpg.h header file.
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a se 10/01/12 Initial creation
* 2.0 se 01/24/13 Cleaned up comments
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "tpg.h"
#include "xenv.h"

349
XilinxProcessorIPLib/drivers/tpg/src/tpg.h
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/*****************************************************************************
*
* Copyright (C) 2001 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"),to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
*****************************************************************************/
/**
*
* @file tpg.h
*
* This header file contains identifiers and register-level driver functions (or
* macros) that can be used to access the Xilinx Test Pattern Generator
* (TPG) core instance.
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a se 10/01/12 Initial creation
* 2.0a se 02/12/14 Cleaned up comments, updated masks and registers
* 2.0 adk 19/12/13 Updated as per the New Tcl API's
*
******************************************************************************/
#ifndef TPG_DRIVER_H /* prevent circular inclusions */
#define TPG_DRIVER_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_io.h"
/************************** Constant Definitions *****************************/
/**
* Register Offsets
*/
/* General Control Registers */
#define TPG_CONTROL 0x000 /**< Control (R/W) */
#define TPG_STATUS 0x004 /**< Status (R/W) */
#define TPG_ERROR 0x008 /**< Error (R/W) */
#define TPG_IRQ_EN 0x00C /**< IRQ Enable */
#define TPG_VERSION 0x010 /**< Version */
/* Timing Control Registers */
#define TPG_ACTIVE_SIZE 0x020 /**< Active Size (V x H) */
/* Core Specific Registers */
#define TPG_PATTERN_CONTROL 0x100
#define TPG_MOTION_SPEED 0x104
#define TPG_CROSS_HAIRS 0x108
#define TPG_ZPLATE_HOR_CONTROL 0x10C
#define TPG_ZPLATE_VER_CONTROL 0x110
#define TPG_BOX_SIZE 0x114
#define TPG_BOX_COLOR 0x118
#define TPG_STUCK_PIXEL_THRESH 0x11C
#define TPG_NOISE_GAIN 0x120
#define TPG_BAYER_PHASE 0x124
/**
* TPG Control Register bit definition
*/
#define TPG_CTL_EN_MASK 0x00000001 /**< TPG Enable */
#define TPG_CTL_RUE_MASK 0x00000002 /**< TPG Register Update */
#define TPG_CTL_CS_MASK 0x00000004 /**< TPG Register Clear Status */
/**
* TPG Reset Register bit definition
*/
#define TPG_RST_RESET 0x80000000 /**< Software Reset - Instantaneous */
#define TPG_RST_AUTORESET 0x40000000 /**< Software Reset - Auto-synchronize to SOF */
/**
* TPG Pattern Control Register bit definition
*/
#define TPG_PASS_THROUGH 0x00000000
#define TPG_HOR_RAMP 0x00000001
#define TPG_VER_RAMP 0x00000002
#define TPG_TEMP_RAMP 0x00000003
#define TPG_SOLID_RED 0x00000004
#define TPG_SOLID_GREEN 0x00000005
#define TPG_SOLID_BLUE 0x00000006
#define TPG_SOILD_BLACK 0x00000007
#define TPG_SOLID_WHITE 0x00000008
#define TPG_COLOR_BARS 0x00000009
#define TPG_ZONE_PLATE 0x0000000A
#define TPG_TARTAN_BARS 0x0000000B
#define TPG_CROSS_HATCH 0x0000000C
#define TPG_VER_HOR_RAMP 0x0000000E
#define TPG_CHECKER_BOARD 0x0000000F
#define TPG_CROSS_HAIRS 0x00000010
#define TPG_MOVING_BOX 0x00000020
#define TPG_MASK_RED_CR 0x00000040
#define TPG_MASK_GREEN_Y 0x00000080
#define TPG_MASK_BLUE_CB 0x00000100
#define TPG_ENABLE_STUCK 0x00000200
#define TPG_ENABLE_NOISE 0x00000400
#define TPG_ENABLE_MOTION 0x00001000
/***************** Macros (Inline Functions) Definitions *********************/
#define TPG_In32 Xil_In32
#define TPG_Out32 Xil_Out32
/**
*
* Read the given register.
*
* @param BaseAddress is the Xilinx EDK base address of the TPG core (from xparameters.h)
* @param RegOffset is the register offset of the register (defined at top of this file)
*
* @return The 32-bit value of the register
*
* @note
* C-style signature:
* u32 TPG_ReadReg(u32 BaseAddress, u32 RegOffset)
*
******************************************************************************/
#define TPG_ReadReg(BaseAddress, RegOffset) \
TPG_In32((BaseAddress) + (RegOffset))
/*****************************************************************************/
/**
*
* Write the given register.
*
* @param BaseAddress is the Xilinx EDK base address of the TPG core (from xparameters.h)
* @param RegOffset is the register offset of the register (defined at top of this file)
* @param Data is the 32-bit value to write to the register
*
* @return None.
*
* @note
* C-style signature:
* void TPG_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
*
******************************************************************************/
#define TPG_WriteReg(BaseAddress, RegOffset, Data) \
TPG_Out32((BaseAddress) + (RegOffset), (Data))
/*****************************************************************************/
/**
*
* This macro enables a TPG core instance.
*
* @param BaseAddress is the Xilinx EDK base address of the TPG core (from xparameters.h)
*
* @return None.
*
* @note
* C-style signature:
* void TPG_Enable(u32 BaseAddress);
*
******************************************************************************/
#define TPG_Enable(BaseAddress) \
TPG_WriteReg(BaseAddress, TPG_CONTROL, \
TPG_ReadReg(BaseAddress, TPG_CONTROL) | \
TPG_CTL_EN_MASK)
/*****************************************************************************/
/**
*
* This macro disables a TPG core instance.
*
* @param BaseAddress is the Xilinx EDK base address of the TPG core (from xparameters.h)
*
* @return None.
*
* @note
* C-style signature:
* void TPG_Disable(u32 BaseAddress);
*
******************************************************************************/
#define TPG_Disable(BaseAddress) \
TPG_WriteReg(BaseAddress, TPG_CONTROL, \
TPG_ReadReg(BaseAddress, TPG_CONTROL) & \
~TPG_CTL_EN_MASK)
/*****************************************************************************/
/**
*
* This macro commits all the register value changes made so far by the software
* to the TPG core instance. The registers will be automatically updated
* on the next rising-edge of the VBlank_in signal on the core.
* It is up to the user to manually disable the register update after a sufficient
* amount if time.
*
* This function only works when the TPG core is enabled.
*
* @param BaseAddress is the Xilinx EDK base address of the TPG core (from xparameters.h)
*
* @return None.
*
* @note
* C-style signature:
* void TPG_RegUpdateEnable(u32 BaseAddress);
*
******************************************************************************/
#define TPG_RegUpdateEnable(BaseAddress) \
TPG_WriteReg(BaseAddress, TPG_CONTROL, \
TPG_ReadReg(BaseAddress, TPG_CONTROL) | \
TPG_CTL_RUE_MASK)
/*****************************************************************************/
/**
*
* This macro prevents the TPG core instance from committing recent changes made
* so far by the software. When disabled, changes to other configuration registers
* are stored, but do not effect the behavior of the core.
*
* This function only works when the TPG core is enabled.
*
* @param BaseAddress is the Xilinx EDK base address of the TPG core (from xparameters.h)
*
* @return None.
*
* @note
* C-style signature:
* void TPG_RegUpdateDisable(u32 BaseAddress);
*
******************************************************************************/
#define TPG_RegUpdateDisable(BaseAddress) \
TPG_WriteReg(BaseAddress, TPG_CONTROL, \
TPG_ReadReg(BaseAddress, TPG_CONTROL) & \
~TPG_CTL_RUE_MASK)
/*****************************************************************************/
/**
*
* This macro clears the status register of the TPG instance, by first asserting then
* deasserting the CLEAR_STATUS flag of TPG_CONTROL.
* This function only works when the TPG core is enabled.
*
* @param BaseAddress is the Xilinx EDK base address of the TPG core (from xparameters.h)
*
* @return None.
*
* @note
* C-style signature:
* void TPG_ClearStatus(u32 BaseAddress);
*
******************************************************************************/
#define TPG_ClearStatus(BaseAddress) \
TPG_WriteReg(BaseAddress, TPG_CONTROL, TPG_ReadReg(BaseAddress, TPG_CONTROL) | TPG_CTL_CS_MASK); \
TPG_WriteReg(BaseAddress, TPG_CONTROL, TPG_ReadReg(BaseAddress, TPG_CONTROL) & ~TPG_CTL_CS_MASK)
/*****************************************************************************/
/**
*
* This macro resets a TPG core instance. This reset effects the core immediately,
* and may cause image tearing.
*
* This reset resets the TPG's configuration registers, and holds the core's outputs
* in their reset state until TPG_ClearReset() is called.
*
*
* @param BaseAddress is the Xilinx EDK base address of the TPG core (from xparameters.h)
*
* @return None.
*
* @note
* C-style signature:
* void TPG_Reset(u32 BaseAddress);
*
******************************************************************************/
#define TPG_Reset(BaseAddress) \
TPG_WriteReg(BaseAddress, TPG_CONTROL, TPG_RST_RESET) \
/*****************************************************************************/
/**
*
* This macro clears the TPG's reset flag (which is set using TPG_Reset(), and
* returns it to normal operation. This ClearReset effects the core immediately,
* and may cause image tearing.
*
*
* @param BaseAddress is the Xilinx EDK base address of the TPG core (from xparameters.h)
*
* @return None.
*
* @note
* C-style signature:
* void TPG_ClearReset(u32 BaseAddress);
*
******************************************************************************/
#define TPG_ClearReset(BaseAddress) \
TPG_WriteReg(BaseAddress, TPG_CONTROL, 0) \
/*****************************************************************************/
/**
*
* This macro resets a TPG instance, but differs from TPG_Reset() in that it
* automatically synchronizes to the SOF of the core to prevent tearing.
*
* On the next rising-edge of SOF following a call to TPG_AutoSyncReset(),
* all of the core's configuration registers and outputs will be reset, then the
* reset flag will be immediately released, allowing the core to immediately resume
* default operation.
*
* @param BaseAddress is the Xilinx EDK base address of the TPG core (from xparameters.h)
*
* @return None.
*
* @note
* C-style signature:
* void TPG_FSyncReset(u32 BaseAddress);
*
******************************************************************************/
#define TPG_FSyncReset(BaseAddress) \
TPG_WriteReg(BaseAddress, TPG_CONTROL, TPG_RST_AUTORESET) \
/************************** Function Prototypes ******************************/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

1504
XilinxProcessorIPLib/drivers/tpg/src/xtpg.c Executable file
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XilinxProcessorIPLib/drivers/tpg/src/xtpg.h Executable file
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/******************************************************************************
*
* Copyright (C) 2001 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xtpg.h
*
* This header file contains identifiers and register-level driver functions (or
* macros) that can be used to access the Xilinx Test Pattern Generator
* (TPG) core instance.
*
* The TPG core provides a wide variety of tests patterns enabling you to debug
* and assess video system color, quality, edge, and motion performance.
*
* The Test Pattern Generator core produces the following patterns in RGB,
* YCbCr 444, or YCbCr 422 video format.
* - Video input pass through
* - Horizontal ramp
* - Vertical ramp
* - Temporal ramp
* - Flat fields (red, green, blue, black and white)
* - Combined vertical and horizontal ramp
* - Color bars
* - Tartan bars
* - Zone plate
* - Cross hairs
* - Cross hatch
* - Solid box
* - Motion effect for ramps, zone plate, and solid box
*
* <b>Initialization & Configuration</b>
*
* The device driver enables higher layer software (e.g., an application) to
* communicate to the TPG core.
*
* XTpg_CfgInitialize() API is used to initialize the TPG core.
* The user needs to first call the XTpg_LookupConfig() API which returns
* the Configuration structure pointer which is passed as a parameter to the
* XTpg_CfgInitialize() API.
*
* <b> Interrupts </b>
*
* The driver provides an interrupt handler XTpg_IntrHandler for handling
* the interrupt from the TPG core. The users of this driver have to
* register this handler with the interrupt system and provide the callback
* functions by using XTpg_SetCallBack API.
*
* <b> Virtual Memory </b>
*
* This driver supports Virtual Memory. The RTOS is responsible for calculating
* the correct device base address in Virtual Memory space.
*
* <b> Threads </b>
*
* This driver is not thread safe. Any needs for threads or thread mutual
* exclusion must be satisfied by the layer above this driver.
*
* <b> Asserts </b>
*
* Asserts are used within all Xilinx drivers to enforce constraints on argument
* values. Asserts can be turned off on a system-wide basis by defining, at
* compile time, the NDEBUG identifier. By default, asserts are turned on and it
* is recommended that users leave asserts on during development.
*
* <b> Building the driver </b>
*
* The XTpg driver is composed of several source files. This allows the user
* to build and link only those parts of the driver that are necessary.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- --------------------------------------------------
* 1.00a se 10/01/12 Initial creation.
* 2.0a se 02/12/14 Cleaned up comments, updated masks and registers.
* 2.0 adk 19/12/13 Updated as per the New Tcl API's.
* 3.0 adk 02/19/14 Changed the file name from "tpg.h" to "xtpg.h"
* Register offsets, TPG_In32, TPG_In32, TPG_ReadReg,
* TPG_WriteReg and bit definitions of tpg.h file
* were moved to xtpg_hw.h file.
*
* Removed the following bit definitions :
* TPG_CTL_CS_MASK.
*
* Defined the following handler types as enum values:
* XTPG_HANDLER_PROCSTART ,XTPG_HANDLER_FRAMEDONE and
* XTPG_HANDLER_ERROR.
* Defined the following enums:
* BackgroundPattern, ComponentMask and
* BayerPhaseCombination.
*
* Defined the following range macros
* XTPG_MOTION_SPEED_MIN, XTPG_MOTION_SPEED_MAX,
* XTPG_VSIZE_FIRST, XTPG_VSIZE_LAST, XTPG_HSIZE_FIRST,
* XTPG_HSIZE_LAST.
*
* Added the following function macros:
* XTpg_Enable, XTpg_Disable, XTpg_Start, XTpg_Stop,
* XTpg_RegUpdateEnable, XTpg_RegUpdateDisable,
* XTpg_Reset, XTpg_SyncReset, XTpg_IntrEnable,
* XTpg_IntrDisable, XTpg_StatusGetPending,
* XTpg_IntrGetPending, XTpg_IntrClear.
*
* Removed following function macros:
* TPG_Enable, TPG_Disable, TPG_RegUpdateEnable,
* TPG_RegUpdateDisable, TPG_Reset, TPG_FSyncReset
* TPG_ClearStatus, TPG_ClearReset.
* Added the following structures
* XTpg and XTpg_Config.
*
* Implemented XTpg_LookupConfig in xtpg_sinit.c
* Implemented XTpg_SelfTest in xtpg_selftest.c
* Implemented XTpg_IntrHandler, XTpg_SetCallBack in
* xtpg_intr.c.
*
* Added the register offsets and bit masks for the
* registers and added backward compatibility for
* macros.in xtpg_hw.h.
*
* Modification history from xtpg.c file:
* Changed the file name form "tpg.c" to "xtpg.c".
* Implemented the following functions:
* XTpg_CfgInitialize, XTpg_Setup, XTpg_GetVersion,
* XTpg_SetActiveSize, XTpg_GetActiveSize,
* XTpg_SetBackground, XTpg_GetBackground,
* XTpg_EnableCrossHair, XTpg_DisableCrossHair,
* XTpg_EnableBox, XTpg_DisableBox, XTpg_SetComponentMask,
* XTpg_GetComponentMask, XTpg_EnableStuckPixel,
* XTpg_DisableStuckPixel, XTPg_EnableNoise,
* XTPg_DisableNoise, XTpg_EnableMotion,
* XTpg_DisableMotion, XTpg_SetMotionSpeed,
* XTpg_GetMotionSpeed, XTpg_SetCrosshairPosition,
* XTpg_GetCrosshairPosition, XTpg_SetZPlateHStart,
* XTpg_GetZPlateHStart, XTpg_SetZPlateHSpeed,
* XTpg_GetZPlateHSpeed, XTpg_SetZPlateVStart,
* XTpg_GetZPlateVStart, XTpg_SetZPlateVSpeed,
* XTpg_GetZPlateVSpeed, XTpg_SetBoxSize, XTpg_GetBoxSize,
* XTpg_SetBoxColor, XTpg_GetBoxColor,
* XTpg_SetStuckPixelThreshold,
* XTpg_GetStuckPixelThreshold, XTpg_SetNoiseGain,
* XTpg_GetNoiseGain, XTpg_SetBayerPhase,
* XTpg_GetBayerPhase, XTpg_SetPattern, XTpg_GetPattern.
*
* </pre>
*
******************************************************************************/
#ifndef XTPG_H_
#define XTPG_H_ /**< Prevent circular inclusions
* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_assert.h"
#include "xstatus.h"
#include "xtpg_hw.h"
/************************** Constant Definitions *****************************/
/** @name Handler Types
* @{
*/
/**
* These constants specify different types of handlers and used to differentiate
* interrupt requests from core.
*/
enum {
XTPG_HANDLER_PROCSTART = 1, /**< A processing start event interrupt
* type */
XTPG_HANDLER_FRAMEDONE, /**< A frame done event interrupt
* type */
XTPG_HANDLER_ERROR /**< An error condition event interrupt
* type */
} ;
/*@}*/
/** @name BackgroundPattern
* @{
*/
/**
* These constants specify different types of background patterns supported by
* the core.
*/
enum BackgroundPattern {
XTPG_PASS_THROUGH, /**< Pass video input straight through
* the video output */
XTPG_H_RAMP, /**< Horizontal ramp */
XTPG_V_RAMP, /**< Vertical ramp */
XTPG_T_RAMP, /**< Temporal ramp */
XTPG_RED_PLANE, /**< Solid red output */
XTPG_GREEN_PLANE, /**< Solid green output */
XTPG_BLUE_PLANE, /**< Solid blue output */
XTPG_BLACK_PLANE, /**< Solid black output */
XTPG_WHITE_PLANE, /**< Solid white output */
XTPG_COLOR_BARS, /**< Color bars */
XTPG_ZONE_PLATE, /**< Zone plate output (sinusoidal) */
XTPG_TARAN_BARS, /**< Tartan color bars */
XTPG_CROSS_HATCH, /**< Cross hatch pattern */
XTPG_HV_RAMP = 0xE, /**< Horizontal vertical ramp */
XTPG_BLACK_AND_WHITE_CHECKERBOARD /**< Black and white checker board */
};
/*@}*/
/** @name ComponentMask
* @{
*/
/**
* These constants specify mask outs for a particular color component.
*/
enum ComponentMask {
XTPG_NOMASK, /**< No masking */
XTPG_MASKOUT_RED, /**< Mask out red,
* Cr(for YCbCr mode) component */
XTPG_MASKOUT_GREEN, /**< Mask out green,
* Y( for YCbCr mode) component */
XTPG_MASKOUT_BLUE = 0x4 /**< Mask out blue,
* Cr(for YCbCr mode) component */
};
/*@}*/
/** @name Bayer phase combinations
* @{
*/
/**
* These constants specify Bayer phase combinations of the core.
*/
enum BayerPhaseCombination {
XTPG_BAYER_PHASE_RGRG, /**< Red green combination */
XTPG_BAYER_PHASE_GRGR, /**< Green red combination */
XTPG_BAYER_PHASE_GBGB, /**< Green blue combination */
XTPG_BAYER_PHASE_BGBG, /**< Blue green combination */
XTPG_BAYER_PHASE_TURNOFF /**< Turn off the Bayer phase */
} ;
/*@}*/
/** @name Motion Speed Ranges
* @{
*/
#define XTPG_MOTION_SPEED_MIN 0 /**< Motion Speed minimum value */
#define XTPG_MOTION_SPEED_MAX 255 /**< Motion Speed maximum value */
/*@}*/
/** @name Active Size Ranges
* @{
*/
#define XTPG_VSIZE_FIRST 32 /**< Vertical Size starting value */
#define XTPG_VSIZE_LAST 7680 /**< Vertical Size ending value */
#define XTPG_HSIZE_FIRST 32 /**< Horizontal Size starting
* value */
#define XTPG_HSIZE_LAST 7680 /**< Horizontal Size ending value */
/*@}*/
/***************** Macros (Inline Functions) Definitions *********************/
/** @name Macros for operating a TPG core
* @{
*/
/*****************************************************************************/
/**
*
* This function macro enables the TPG core.
*
* @param InstancePtr is a pointer to the XTpg instance to be worked on.
*
* @return None.
*
* @note C-style signature:
* void XTpg_Enable(XTpg *InstancePtr)
*
******************************************************************************/
#define XTpg_Enable(InstancePtr) \
XTpg_WriteReg((InstancePtr)->Config.BaseAddress, \
(XTPG_CONTROL_OFFSET), \
(XTpg_ReadReg((InstancePtr)->Config.BaseAddress, \
(XTPG_CONTROL_OFFSET)) | (XTPG_CTL_SW_EN_MASK)))
/*****************************************************************************/
/**
*
* This function macro disables the TPG core.
*
* @param InstancePtr is a pointer to the XTpg instance to be worked on.
*
* @return None.
*
* @note C-style signature:
* void XTpg_Disable(XTpg *InstancePtr)
*
******************************************************************************/
#define XTpg_Disable(InstancePtr) \
XTpg_WriteReg((InstancePtr)->Config.BaseAddress, \
(XTPG_CONTROL_OFFSET), \
(XTpg_ReadReg((InstancePtr)->Config.BaseAddress, \
(XTPG_CONTROL_OFFSET)) & \
(~(XTPG_CTL_SW_EN_MASK))))
/*****************************************************************************/
/**
*
* This function macro enables/starts the TPG core.
*
* @param InstancePtr is a pointer to the XTpg instance to be worked on.
*
* @return None.
*
* @note C-style signature:
* void XTpg_Start(XTpg *InstancePtr)
*
******************************************************************************/
#define XTpg_Start XTpg_Enable
/*****************************************************************************/
/**
*
* This function macro disables/stops the TPG core.
*
* @param InstancePtr is a pointer to the XTpg instance to be worked on.
*
* @return None.
*
* @note C-style signature:
* void XTpg_Stop(XTpg *InstancePtr)
*
******************************************************************************/
#define XTpg_Stop XTpg_Disable
/*****************************************************************************/
/**
*
* This function macro commits all the register value changes made so far by
* the software to the TPG core.
*
* This function only works when the TPG core is enabled.
*
* @param InstancePtr is a pointer to the XTpg instance to be worked on.
*
* @return None.
*
* @note C-style signature:
* void XTpg_RegUpdateEnable(XTpg *InstancePtr)
*
******************************************************************************/
#define XTpg_RegUpdateEnable(InstancePtr) \
XTpg_WriteReg((InstancePtr)->Config.BaseAddress, \
(XTPG_CONTROL_OFFSET), \
(XTpg_ReadReg((InstancePtr)->Config.BaseAddress, \
(XTPG_CONTROL_OFFSET)) | (XTPG_CTL_RUE_MASK)))
/*****************************************************************************/
/**
*
* This function macro prevents the TPG core from committing recent changes made
* so far by the software. When disabled, changes to other configuration
* registers are stored, but do not effect the behavior of the core.
*
* This function only works when the TPG core is enabled.
*
* @param InstancePtr is a pointer to the XTpg instance to be worked on.
*
* @return None.
*
* @note C-style signature:
* void XTpg_RegUpdateDisable(XTpg *InstancePtr)
*
******************************************************************************/
#define XTpg_RegUpdateDisable(InstancePtr) \
XTpg_WriteReg((InstancePtr)->Config.BaseAddress, \
(XTPG_CONTROL_OFFSET), \
(XTpg_ReadReg((InstancePtr)->Config.BaseAddress, \
(XTPG_CONTROL_OFFSET)) & (~(XTPG_CTL_RUE_MASK))))
/*****************************************************************************/
/**
*
* This function macro resets a TPG core at the end of the frame being
* processed. It enables core automatically synchronizes to the SOF of the core
* to prevent image tearing. This function macro is differ from XTpg_Reset().
*
* On the next rising-edge of SOF following a call to XTpg_SyncReset(),
* all of the core's configuration registers and outputs will be reset, then the
* reset flag will be immediately released, allowing the core to immediately
* resume default operation.
*
* @param InstancePtr is a pointer to the XTpg instance to be worked on.
*
* @return None.
*
* @note C-style signature:
* void XTpg_SyncReset(XTpg *InstancePtr)
*
******************************************************************************/
#define XTpg_SyncReset(InstancePtr) \
XTpg_WriteReg(((InstancePtr)->Config.BaseAddress), \
(XTPG_CONTROL_OFFSET), (XTPG_CTL_AUTORESET_MASK))
/*****************************************************************************/
/**
*
* This function macro resets a TPG core. This reset effects the core
* immediately and may cause image tearing.
*
* @param InstancePtr is a pointer to the XTpg instance to be worked on.
*
* @return None.
*
* @note This reset resets the TPG configuration registers.
* C-style signature:
* void XTpg_Reset(XTpg *InstancePtr)
*
******************************************************************************/
#define XTpg_Reset(InstancePtr) \
XTpg_WriteReg((InstancePtr)->Config.BaseAddress, \
(XTPG_CONTROL_OFFSET), (XTPG_CTL_RESET_MASK))
/*****************************************************************************/
/**
*
* This function macro enables individual interrupts of the TPG core by updating
* the IRQ_ENABLE register.
*
* @param InstancePtr is a pointer to the XTpg instance to be worked on.
* @param IntrType is the bit-mask of the interrupts to be enabled.
* Bit positions of 1 will be enabled. Bit positions of 0 will
* keep the previous setting. This mask is formed by OR'ing
* XTPG_IXR_*_MASK bits defined in xtpg_hw.h.
*
* @return None.
*
* @note The existing enabled interrupt(s) will remain enabled.
* C-style signature:
* void XTpg_IntrEnable(XTpg *InstancePtr, u32 IntrType)
*
******************************************************************************/
#define XTpg_IntrEnable(InstancePtr, IntrType) \
XTpg_WriteReg((InstancePtr)->Config.BaseAddress, (XTPG_IRQ_EN_OFFSET),\
((IntrType) & (XTPG_IXR_ALLINTR_MASK)) | \
(XTpg_ReadReg((InstancePtr)->Config.BaseAddress, \
(XTPG_IRQ_EN_OFFSET))))
/*****************************************************************************/
/**
*
* This function macro disables individual interrupts of the TPG core by
* updating the IRQ_ENABLE register.
*
* @param InstancePtr is a pointer to the XTpg instance to be worked on.
* @param IntrType is the bit-mask of the interrupts to be disabled.
* Bit positions of 1 will be disabled. Bit positions of 0 will
* keep the previous setting. This mask is formed by OR'ing
* XTPG_IXR_*_MASK bits defined in xtpg_hw.h.
*
* @return None.
*
* @note Any other interrupt not covered by parameter IntrType, if
* enabled before this macro is called, will remain enabled.
* C-style signature:
* void XTpg_IntrDisable(XTpg *InstancePtr, u32 IntrType)
*
******************************************************************************/
#define XTpg_IntrDisable(InstancePtr, IntrType) \
XTpg_WriteReg((InstancePtr)->Config.BaseAddress, (XTPG_IRQ_EN_OFFSET),\
XTpg_ReadReg((InstancePtr)->Config.BaseAddress, \
(XTPG_IRQ_EN_OFFSET)) & ((~(IntrType)) & \
(XTPG_IXR_ALLINTR_MASK)))
/*****************************************************************************/
/**
*
* This function macro returns the pending interrupt status of the TPG core read
* from the Status register.
*
* @param InstancePtr is a pointer to the XTpg instance to be worked on.
*
* @return The pending interrupts of the TPG. Use XTPG_IXR_*_MASK
* constants defined in xtpg_hw.h to interpret this value.
*
* @note C-style signature:
* u32 XTpg_StatusGePending(XTpg *InstancePtr)
*
******************************************************************************/
#define XTpg_StatusGetPending(InstancePtr) \
XTpg_ReadReg((InstancePtr)->Config.BaseAddress, \
(XTPG_STATUS_OFFSET)) & \
(XTPG_IXR_ALLINTR_MASK)
/*****************************************************************************/
/**
*
* This function macro returns the pending interrupts of the TPG core for the
* interrupts that have been enabled.
*
* @param InstancePtr is a pointer to the XTpg instance to be worked on.
*
* @return The pending interrupts of the TPG. Use XTPG_IXR_*_MASK
* constants defined in xtpg_hw.h to interpret this value.
* The returned value is a logical AND of the contents of the
* Status Register and the IRQ_ENABLE Register.
*
* @note C-style signature:
* u32 XTpg_IntrGetPending(XTpg *InstancePtr)
*
******************************************************************************/
#define XTpg_IntrGetPending(InstancePtr) \
XTpg_ReadReg((InstancePtr)->Config.BaseAddress, \
(XTPG_IRQ_EN_OFFSET)) &\
(XTpg_ReadReg((InstancePtr)->Config.BaseAddress, \
(XTPG_STATUS_OFFSET)) & ((u32)XTPG_IXR_ALLINTR_MASK))
/*****************************************************************************/
/**
*
* This function macro clears/acknowledges pending interrupts of the TPG core
* in the Status register. Bit positions of 1 will be cleared.
*
* @param InstancePtr is a pointer to the XTpg instance to be worked on.
* @param IntrType is the pending interrupts to clear/acknowledge.
* Use OR'ing of XTPG_IXR_*_MASK constants defined in xtpg_hw.h to
* create this parameter value.
*
* @return None.
*
* @note C-style signature:
* void XTpg_IntrClear(XTpg *InstancePtr, u32 IntrType)
*
******************************************************************************/
#define XTpg_IntrClear(InstancePtr, IntrType) \
XTpg_WriteReg((InstancePtr)->Config.BaseAddress, \
(XTPG_STATUS_OFFSET),\
(IntrType) & ((u32)(XTPG_IXR_ALLINTR_MASK)))
/*@}*/
/**************************** Type Definitions *******************************/
/**
* This typedef contains configuration information for a TPG core.
* Each TPG core should have a configuration structure associated.
*/
typedef struct {
u16 DeviceId; /**< DeviceId is the unique ID
* of the TPG core */
u32 BaseAddress; /**< BaseAddress is the physical
* base address of the
* TPG core registers */
u32 SlaveAxisVideoFormat; /**< Slave Axis Video Format */
u32 MasterAxisVideoFormat; /**< Master Axis Video Format */
u32 SlaveAxiClkFreqHz; /**< Slave Clock Frequency */
u32 ActiveRows; /**< Active Rows */
u32 ActiveColumns; /**< Active Columns */
u32 PatternControl; /**< Pattern Control */
u8 MotionSpeed; /**< Motion Speed */
u32 CrossHairs; /**< Cross Hair */
u32 ZPlateHorizontalControl; /**< ZPlate Horizontal Control */
u32 ZPlateVerticalControl; /**< ZPlate Vertical Control */
u16 BoxSize; /**< Box Size */
u32 BoxColor; /**< Box Color */
u16 StuckPixelThreshold; /**< Stuck Pixel Threshold */
u8 NoiseGain; /**< Noise Gain */
u8 BayerPhase; /**< Bayer Phase */
u16 HasIntcIf; /**< Has Interrupt Control Flag */
u16 EnableMotion; /**< Enable Motion */
} XTpg_Config;
/**
*
* Callback type for all interrupts except error interrupt.
*
* @param CallBackRef is a callback reference passed in by the upper
* layer when setting the callback functions, and passed back to
* the upper layer when the callback is invoked.
*/
typedef void (*XTpg_CallBack)(void *CallBackRef);
/**
*
* Callback type for Error interrupt.
*
* @param CallBackRef is a callback reference passed in by the upper
* layer when setting the callback functions, and passed back to
* the upper layer when the callback is invoked.
* @param ErrorMask is a bit mask indicating the cause of the error. Its
* value equals 'OR'ing one or more XTPG_IXR_*_MASK values defined
* in xtpg_hw.h.
*/
typedef void (*XTpg_ErrorCallBack)(void *CallBackRef, u32 ErrorMask);
/**
*
* The XTpg driver instance data structure. A pointer to an instance data
* structure is passed around by functions to refer to a specific driver
* instance.
*/
typedef struct {
XTpg_Config Config; /**< Hardware configuration */
u32 IsReady; /**< Core and the driver instance
* are initialized */
u16 HSize; /**< Active Video Horizontal Size */
u16 VSize; /**< Active Video Vertical Size */
/* IRQ Callbacks Here */
XTpg_CallBack ProcStartCallBack;/**< Callback for Processing Start
* interrupt */
void *ProcStartRef; /**< To be passed to the Process Start
* interrupt callback */
XTpg_CallBack FrameDoneCallBack;/**< Callback for Frame Done
* interrupt */
void *FrameDoneRef; /**< To be passed to the Frame Done
* interrupt callback */
XTpg_ErrorCallBack ErrCallBack; /**< Callback for Error interrupt */
void *ErrRef; /**< To be passed to the Error
* interrupt callback */
} XTpg;
/************************** Function Prototypes ******************************/
/*
* Static lookup function implemented in xtpg_sinit.c
*/
XTpg_Config *XTpg_LookupConfig(u16 DeviceId);
/*
* Initialization and control functions implemented in xtpg.c
*/
int XTpg_CfgInitialize(XTpg *InstancePtr, XTpg_Config *CfgPtr,
u32 EffectiveAddr);
void XTpg_Setup(XTpg *InstancePtr);
u32 XTpg_GetVersion(XTpg *InstancePtr);
void XTpg_SetActiveSize(XTpg *InstancePtr, u16 HSize, u16 VSize);
void XTpg_GetActiveSize(XTpg *InstancePtr, u16 *HSize, u16 *VSize);
void XTpg_SetPattern(XTpg *InstancePtr, u32 Pattern);
u32 XTpg_GetPattern(XTpg *InstancePtr);
void XTpg_SetBackground(XTpg *InstancePtr, enum BackgroundPattern Pattern);
u32 XTpg_GetBackground(XTpg *InstancePtr);
void XTpg_EnableCrossHair(XTpg *InstancePtr);
void XTpg_DisableCrossHair(XTpg *InstancePtr);
void XTpg_EnableMotion(XTpg *InstancePtr);
void XTpg_DisableMotion(XTpg *InstancePtr);
void XTpg_EnableBox(XTpg *InstancePtr);
void XTpg_DisableBox(XTpg *InstancePtr);
void XTpg_SetComponentMask(XTpg *InstancePtr, enum ComponentMask Mask);
u32 XTpg_GetComponentMask(XTpg *InstancePtr);
void XTpg_EnableStuckPixel(XTpg *InstancePtr);
void XTpg_DisableStuckPixel(XTpg *InstancePtr);
void XTPg_EnableNoise(XTpg *InstancePtr);
void XTPg_DisableNoise(XTpg *InstancePtr);
void XTpg_SetMotionSpeed(XTpg *InstancePtr, u32 MotionSpeed);
u32 XTpg_GetMotionSpeed(XTpg *InstancePtr);
void XTpg_SetCrosshairPosition(XTpg *InstancePtr, u16 HPos, u16 VPos);
void XTpg_GetCrosshairPosition(XTpg *InstancePtr, u16 *HPos, u16 *VPos);
void XTpg_SetZPlateHStart(XTpg *InstancePtr, u16 ZPlateHStart);
u16 XTpg_GetZPlateHStart (XTpg *InstancePtr);
void XTpg_SetZPlateHSpeed(XTpg *InstancePtr, u16 ZPlateHSpeed);
u16 XTpg_GetZPlateHSpeed(XTpg *InstancePtr);
void XTpg_SetZPlateVStart(XTpg *InstancePtr, u16 ZPlateVStart);
u16 XTpg_GetZPlateVStart (XTpg *InstancePtr);
void XTpg_SetZPlateVSpeed(XTpg *InstancePtr, u16 ZPlateVSpeed);
u16 XTpg_GetZPlateVSpeed(XTpg *InstancePtr);
int XTpg_SetBoxSize(XTpg *InstancePtr, u32 BoxSize);
u32 XTpg_GetBoxSize(XTpg *InstancePtr);
void XTpg_SetBoxColor(XTpg *InstancePtr, u16 Blue, u16 Green, u16 Red);
void XTpg_GetBoxColor(XTpg *InstancePtr, u16 *Blue, u16 *Green, u16 *Red);
void XTpg_SetStuckPixelThreshold(XTpg *InstancePtr, u32 PixelThreshold);
u32 XTpg_GetStuckPixelThreshold (XTpg *InstancePtr);
void XTpg_SetNoiseGain(XTpg *InstancePtr, u32 NoiseGain);
u32 XTpg_GetNoiseGain(XTpg *InstancePtr);
void XTpg_SetBayerPhase(XTpg *InstancePtr,
enum BayerPhaseCombination BayerPhaseComb);
u32 XTpg_GetBayerPhase(XTpg *InstancePtr);
/*
* SelfTest function implemented in xtpg_selftest.c
*/
int XTpg_SelfTest(XTpg *InstancePtr);
/*
* Interrupt related functions implemented in xtpg_intr.c
*/
void XTpg_IntrHandler(void *InstancePtr);
int XTpg_SetCallBack(XTpg *InstancePtr, u32 HandlerType, void *CallBackFunc,
void *CallBackRef);
/************************** Variable Declarations ****************************/
#ifdef __cplusplus
}
#endif
#endif /* End of protection macro */

69
XilinxProcessorIPLib/drivers/tpg/src/xtpg_g.c Executable file
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@ -0,0 +1,69 @@
/*******************************************************************
*
* CAUTION: This file is automatically generated by HSM.
* Version:
* DO NOT EDIT.
*
* v (64-bit)
SW Build (by ) on
Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
*
* Description: Driver configuration
*
*******************************************************************/
#include "xparameters.h"
#include "xtpg.h"
/*
* The configuration table for devices
*/
XTpg_Config XTpg_ConfigTable[] =
{
{
XPAR_FMC_HDMI_INPUT_V_TPG_1_DEVICE_ID,
XPAR_FMC_HDMI_INPUT_V_TPG_1_BASEADDR,
XPAR_FMC_HDMI_INPUT_V_TPG_1_S_AXIS_VIDEO_FORMAT,
XPAR_FMC_HDMI_INPUT_V_TPG_1_M_AXIS_VIDEO_FORMAT,
XPAR_FMC_HDMI_INPUT_V_TPG_1_S_AXI_CLK_FREQ_HZ,
XPAR_FMC_HDMI_INPUT_V_TPG_1_ACTIVE_ROWS,
XPAR_FMC_HDMI_INPUT_V_TPG_1_ACTIVE_COLS,
XPAR_FMC_HDMI_INPUT_V_TPG_1_PATTERN_CONTROL,
XPAR_FMC_HDMI_INPUT_V_TPG_1_MOTION_SPEED,
XPAR_FMC_HDMI_INPUT_V_TPG_1_CROSS_HAIRS,
XPAR_FMC_HDMI_INPUT_V_TPG_1_ZPLATE_HOR_CONTROL,
XPAR_FMC_HDMI_INPUT_V_TPG_1_ZPLATE_VER_CONTROL,
XPAR_FMC_HDMI_INPUT_V_TPG_1_BOX_SIZE,
XPAR_FMC_HDMI_INPUT_V_TPG_1_BOX_COLOR,
XPAR_FMC_HDMI_INPUT_V_TPG_1_STUCK_PIXEL_THRESH,
XPAR_FMC_HDMI_INPUT_V_TPG_1_NOISE_GAIN,
XPAR_FMC_HDMI_INPUT_V_TPG_1_BAYER_PHASE,
XPAR_FMC_HDMI_INPUT_V_TPG_1_HAS_INTC_IF,
XPAR_FMC_HDMI_INPUT_V_TPG_1_ENABLE_MOTION
},
{
XPAR_FMC_SENSOR_INPUT_V_TPG_1_DEVICE_ID,
XPAR_FMC_SENSOR_INPUT_V_TPG_1_BASEADDR,
XPAR_FMC_SENSOR_INPUT_V_TPG_1_S_AXIS_VIDEO_FORMAT,
XPAR_FMC_SENSOR_INPUT_V_TPG_1_M_AXIS_VIDEO_FORMAT,
XPAR_FMC_SENSOR_INPUT_V_TPG_1_S_AXI_CLK_FREQ_HZ,
XPAR_FMC_SENSOR_INPUT_V_TPG_1_ACTIVE_ROWS,
XPAR_FMC_SENSOR_INPUT_V_TPG_1_ACTIVE_COLS,
XPAR_FMC_SENSOR_INPUT_V_TPG_1_PATTERN_CONTROL,
XPAR_FMC_SENSOR_INPUT_V_TPG_1_MOTION_SPEED,
XPAR_FMC_SENSOR_INPUT_V_TPG_1_CROSS_HAIRS,
XPAR_FMC_SENSOR_INPUT_V_TPG_1_ZPLATE_HOR_CONTROL,
XPAR_FMC_SENSOR_INPUT_V_TPG_1_ZPLATE_VER_CONTROL,
XPAR_FMC_SENSOR_INPUT_V_TPG_1_BOX_SIZE,
XPAR_FMC_SENSOR_INPUT_V_TPG_1_BOX_COLOR,
XPAR_FMC_SENSOR_INPUT_V_TPG_1_STUCK_PIXEL_THRESH,
XPAR_FMC_SENSOR_INPUT_V_TPG_1_NOISE_GAIN,
XPAR_FMC_SENSOR_INPUT_V_TPG_1_BAYER_PHASE,
XPAR_FMC_SENSOR_INPUT_V_TPG_1_HAS_INTC_IF,
XPAR_FMC_SENSOR_INPUT_V_TPG_1_ENABLE_MOTION
}
};

434
XilinxProcessorIPLib/drivers/tpg/src/xtpg_hw.h Executable file
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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xtpg_hw.h
*
* This header file contains the hardware register offsets and register bit
* definitions for the Xilinx Test Pattern Generator (TPG) core.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- -----------------------------------------------------
* 3.0 adk 02/19/14 First release.
* Added the register offsets and bit masks for the
* registers and added backward compatibility for macros.
* </pre>
*
******************************************************************************/
#ifndef XTPG_HW_H_
#define XTPG_HW_H_ /**< Prevent circular inclusions
* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_io.h"
/************************** Constant Definitions *****************************/
/** @name TPG registers offsets
* @{
*/
#define XTPG_CONTROL_OFFSET 0x000 /**< Control Offset */
#define XTPG_STATUS_OFFSET 0x004 /**< Status Offset */
#define XTPG_ERROR_OFFSET 0x008 /**< Error Offset */
#define XTPG_IRQ_EN_OFFSET 0x00C /**< IRQ Enable Offset */
#define XTPG_VERSION_OFFSET 0x010 /**< Version Offset */
#define XTPG_ACTIVE_SIZE_OFFSET 0x020 /**< Active Size (V x H)
* Offset */
#define XTPG_PATTERN_CONTROL_OFFSET 0x100 /**< Pattern Control Offset */
#define XTPG_MOTION_SPEED_OFFSET 0x104 /**< Motion Speed Offset */
#define XTPG_CROSS_HAIRS_OFFSET 0x108 /**< Cross Hair Offset */
#define XTPG_ZPLATE_HOR_CONTROL_OFFSET 0x10C /**< ZPlate Horizontal Control
* Offset */
#define XTPG_ZPLATE_VER_CONTROL_OFFSET 0x110 /**< ZPlate Vertical Control
* Offset */
#define XTPG_BOX_SIZE_OFFSET 0x114 /**< Box Size Offset */
#define XTPG_BOX_COLOR_OFFSET 0x118 /**< Box Color Offset */
#define XTPG_STUCK_PIXEL_THRESH_OFFSET 0x11C /**< Stuck Pixel Threshold
* Offset */
#define XTPG_NOISE_GAIN_OFFSET 0x120 /**< Noise Gain Offset */
#define XTPG_BAYER_PHASE_OFFSET 0x124 /**< Bayer Phase Offset */
/*@}*/
/** @name Control register bit masks
* @{
*/
#define XTPG_CTL_SW_EN_MASK 0x00000001 /**< S/W Enable Mask */
#define XTPG_CTL_RUE_MASK 0x00000002 /**< Register Update Enable
* Mask */
#define XTPG_CTL_AUTORESET_MASK 0x40000000 /**< Software Reset -
* Auto-synchronize to SOF
* Mask */
#define XTPG_CTL_RESET_MASK 0x80000000 /**< Software Reset -
* Instantaneous Mask */
/*@}*/
/** @name Interrupt register bit masks. It is applicable for
* Status and IRQ_ENABLE Registers
* @{
*/
#define XTPG_IXR_PROCS_STARTED_MASK 0x00000001/**< Process started Mask */
#define XTPG_IXR_EOF_MASK 0x00000002 /**< End-Of-Frame Mask */
#define XTPG_IXR_SE_MASK 0x00010000 /**< Slave Error Mask */
#define XTPG_IXR_ALLINTR_MASK 0x00010003 /**< Addition of all Masks */
/*@}*/
/** @name Error register bit mask definitions
* @{
*/
#define XTPG_ERR_EOL_EARLY_MASK 0x00000001 /**< End of Line Early Mask */
#define XTPG_ERR_EOL_LATE_MASK 0x00000002 /**< End of Line Late Mask */
#define XTPG_ERR_SOF_EARLY_MASK 0x00000004 /**< Start of Frame Early
* Mask */
#define XTPG_ERR_SOF_LATE_MASK 0x00000008 /**< Start of Frame Late
* Mask */
/*@}*/
/** @name Version register bit masks and shifts
* @{
*/
#define XTPG_VER_REV_NUM_MASK 0x000000FF /**< Version Revision Number
* Mask */
#define XTPG_VER_PID_MASK 0x00000F00 /**< Version Patch ID Mask */
#define XTPG_VER_REV_MASK 0x0000F000 /**< Version Revision Mask */
#define XTPG_VER_MINOR_MASK 0x00FF0000 /**< Version Minor Mask */
#define XTPG_VER_MAJOR_MASK 0xFF000000 /**< Version Major Mask */
#define XTPG_VER_INTERNAL_SHIFT 8 /**< Version Internal Shift */
#define XTPG_VER_REV_SHIFT 12 /**< Version Revision Shift */
#define XTPG_VER_MINOR_SHIFT 16 /**< Version Minor Shift */
#define XTPG_VER_MAJOR_SHIFT 24 /**< Version Major Shift */
/*@}*/
/** @name Active Size register bit masks and shifts
* @{
*/
#define XTPG_ACTSIZE_NUM_PIXEL_MASK 0x00001FFF /**< Number of Active
* pixels per
* scan line
* (Horizontal)
* Mask */
#define XTPG_ACTSIZE_NUM_LINE_MASK 0x1FFF0000 /**< Number of Active
* lines per Frame
* (Vertical)
* Mask */
#define XTPG_ACTSIZE_NUM_LINE_SHIFT 16 /**< Shift for number
* of lines */
/*@}*/
/** @name Pattern Control register bit masks
* @{
*/
#define XTPG_PTRN_CTL_SET_BG_MASK 0x0000000F /**< Set background
* pattern
* mask */
#define XTPG_PTRN_CTL_EN_CROSSHAIR_MASK 0x00000010 /**< Enable Cross Hair
* Mask */
#define XTPG_PTRN_CTL_EN_BOX_MASK 0x00000020 /**< Moving box enable
* Mask */
#define XTPG_PTRN_CTL_MASK_COLR_COMP_MASK 0x000001C0 /**< Mask out a
* particular
* color
* component
* mask */
#define XTPG_PTRN_CTL_EN_STUCK_MASK 0x00000200 /**< Enable Stuck
* Mask */
#define XTPG_PTRN_CTL_EN_NOISE_MASK 0x00000400 /**< Enable Noise
* Mask */
#define XTPG_PTRN_CTL_EN_MOTION_MASK 0x00001000 /**< Enable Motion
* Mask */
#define XTPG_PTRN_CTL_MASK_COLR_COMP_SHIFT 5 /**< Shift for a
* particular
* color component
* shift */
/*@}*/
/** @name Pattern values of Pattern Control register
* @{
*/
#define XTPG_PTRN_CTL_PASS_THROUGH 0x00000000 /**< Value for Pass
* Through */
#define XTPG_PTRN_CTL_HOR_RAMP 0x00000001 /**< Value for
* Horizontal
* Ramp */
#define XTPG_PTRN_CTL_VER_RAMP 0x00000002 /**< Value for
* Vertical Ramp */
#define XTPG_PTRN_CTL_TEMP_RAMP 0x00000003 /**< Value for Temporal
* Ramp */
#define XTPG_PTRN_CTL_SOLID_RED 0x00000004 /**< Value for Solid
* Red Output */
#define XTPG_PTRN_CTL_SOLID_GREEN 0x00000005 /**< Value for Solid
* Green Output */
#define XTPG_PTRN_CTL_SOLID_BLUE 0x00000006 /**< Value for Solid
* Blue Output */
#define XTPG_PTRN_CTL_SOLID_BLACK 0x00000007 /**< Value for Solid
* Black Output */
#define XTPG_PTRN_CTL_SOLID_WHITE 0x00000008 /**< Value for Solid
* White Output */
#define XTPG_PTRN_CTL_COLOR_BARS 0x00000009 /**< Value for Color
* Bars Output */
#define XTPG_PTRN_CTL_ZONE_PLATE 0x0000000A /**< Value for
* Zone Plate */
#define XTPG_PTRN_CTL_TARTAN_BARS 0x0000000B /**< Value for Tartan
* Bars */
#define XTPG_PTRN_CTL_CROSS_HATCH 0x0000000C /**< Value for Cross
* Hatch */
#define XTPG_PTRN_CTL_VER_HOR_RAMP 0x0000000E /**< Value for Combined
* Vertical and
* Horizontal ramp */
#define XTPG_PTRN_CTL_CHECKER_BOARD 0x0000000F /**< Value for Black
* and White Checker
* Board */
#define XTPG_PTRN_CTL_MASK_RED_CR 0x00000040 /**< Value for Masking
* Red Component */
#define XTPG_PTRN_CTL_MASK_GREEN_Y 0x00000080 /**< Value for Masking
* Green Component */
#define XTPG_PTRN_CTL_MASK_BLUE_CB 0x00000100 /**< Value for Masking
* Blue Component */
/*@}*/
/** @name Motion Speed register bit mask
* @{
*/
#define XTPG_MOTION_SPEED_MASK 0x000000FF /**< Motion Speed Mask */
/*@}*/
/** @name Cross Hair register bit masks and shift
* @{
*/
#define XTPG_CROSSHAIR_HPOS_MASK 0x00001FFF /**< CrossHair
* Horizontal
* Position Mask */
#define XTPG_CROSSHAIR_VPOS_MASK 0x1FFF0000 /**< CrossHair Vertical
* Position Mask */
#define XTPG_CROSSHAIR_SHIFT 16 /**< Cross Hair
* Shift */
/*@}*/
/** @name ZPlate Horizontal Control register bit masks and shift
* @{
*/
#define XTPG_ZPLATEHOR_START_MASK 0x0000FFFF /**< ZPlate Horizontal
* Start Mask */
#define XTPG_ZPLATEHOR_SPEED_MASK 0xFFFF0000 /**< ZPlate Horizontal
* Speed Mask */
#define XTPG_ZPLATEHOR_SPEED_SHIFT 16 /**< ZPlate Horizontal
* Speed Shift */
/*@}*/
/** @name ZPlate Vertical Control register bit masks
* @{
*/
#define XTPG_ZPLATEVER_START_MASK 0x0000FFFF /**< ZPlate Vertical
* Start Mask */
#define XTPG_ZPLATEVER_SPEED_MASK 0xFFFF0000 /**< ZPlate Vertical
* Speed Mask */
#define XTPG_ZPLATEVER_SPEED_SHIFT 16 /**< ZPlate Vertical
* Speed */
/*@}*/
/** @name Box Size register bit mask
* @{
*/
#define XTPG_BOX_SIZE_MASK 0x00001FFF /**< Box Size Mask */
/*@}*/
/** @name TPG Box Color register bit masks
* @{
*/
#define XTPG_BOXCOL_BLUE_MASK 0x000000FF /**< Blue Color Mask */
#define XTPG_BOXCOL_GREEN_MASK 0x0000FF00 /**< Green Color Mask */
#define XTPG_BOXCOL_RED_MASK 0x00FF0000 /**< Red Color Mask */
#define XTPG_BOXCOL_GREEN_SHIFT 8 /**< Green color shift */
#define XTPG_BOXCOL_RED_SHIFT 16 /**< Red color shift */
/*@}*/
/** @name Stuck Pixel Threshold register bit mask
* @{
*/
#define XTPG_STUCKPIX_THRESH_MASK 0x0000FFFF /**< Stuck Pixel
* Threshold Mask */
/*@}*/
/** @name Noise Gain register bit mask
* @{
*/
#define XTPG_NOISE_GAIN_MASK 0x000000FF /**< Nose Gain Mask */
/*@}*/
/** @name Bayer Phase register bit mask
* @{
*/
#define XTPG_BAYER_PHASE_MASK 0x00000007 /**< Bayer Phase Mask */
/*@}*/
/** @name General purpose masks
* @{
*/
#define XTPG_8_BIT_MASK 0x000000FF /**< 8-bit Mask */
/*@}*/
/**@name Backward compatibility macros
* @{
*/
#define TPG_CONTROL XTPG_CONTROL_OFFSET
#define TPG_STATUS XTPG_STATUS_OFFSET
#define TPG_ERROR XTPG_ERROR_OFFSET
#define TPG_IRQ_EN XTPG_IRQ_EN_OFFSET
#define TPG_VERSION XTPG_VERSION_OFFSET
#define TPG_ACTIVE_SIZE XTPG_ACTIVE_SIZE_OFFSET
#define TPG_PATTERN_CONTROL XTPG_PATTERN_CONTROL_OFFSET
#define TPG_MOTION_SPEED XTPG_MOTION_SPEED_OFFSET
#define TPG_CROSS_HAIRS XTPG_CROSS_HAIRS_OFFSET
#define TPG_ZPLATE_HOR_CONTROL XTPG_ZPLATE_HOR_CONTROL_OFFSET
#define TPG_ZPLATE_VER_CONTROL XTPG_ZPLATE_VER_CONTROL_OFFSET
#define TPG_BOX_SIZE XTPG_BOX_SIZE_OFFSET_OFFSET
#define TPG_BOX_COLOR XTPG_BOX_COLOR_OFFSET
#define TPG_STUCK_PIXEL_THRESH XTPG_STUCK_PIXEL_THRESH_OFFSET
#define TPG_NOISE_GAIN XTPG_NOISE_GAIN_OFFSET
#define TPG_CTL_EN_MASK XTPG_CTL_SW_EN_MASK
#define TPG_CTL_RUE_MASK XTPG_CTL_RUE_MASK
#define TPG_RST_RESET XTPG_CTL_RESET_MASK
#define TPG_RST_AUTORESET XTPG_CTL_AUTORESET_MASK
#define TPG_BAYER_PHASE XTPG_BAYER_PHASE_OFFSET
#define TPG_PASS_THROUGH XTPG_PASS_THROUGH
#define TPG_HOR_RAMP XTPG_HOR_RAMP
#define TPG_VER_RAMP XTPG_VER_RAMP
#define TPG_TEMP_RAMP XTPG_TEMP_RAMP
#define TPG_SOLID_RED XTPG_SOLID_RED
#define TPG_SOLID_GREEN XTPG_SOLID_GREEN
#define TPG_SOLID_BLUE XTPG_SOLID_BLUE
#define TPG_SOILD_BLACK XTPG_SOLID_BLACK
#define TPG_SOLID_WHITE XTPG_SOLID_WHITE
#define TPG_COLOR_BARS XTPG_COLOR_BARS
#define TPG_ZONE_PLATE XTPG_ZONE_PLATE
#define TPG_TARTAN_BARS XTPG_TARTAN_BARS
#define TPG_CROSS_HATCH XTPG_CROSS_HATCH
#define TPG_VER_HOR_RAMP XTPG_VER_HOR_RAMP
#define TPG_CHECKER_BOARD XTPG_CHECKER_BOARD
#define TPG_CROSS_HAIRS XTPG_PTRN_CTL_EN_CROSSHAIR_MASK
#define TPG_MOVING_BOX XTPG_PTRN_CTL_EN_BOX_MASK
#define TPG_MASK_RED_CR XTPG_MASK_RED_CR
#define TPG_MASK_GREEN_Y XTPG_MASK_GREEN_Y
#define TPG_MASK_BLUE_CB XTPG_MASK_BLUE_CB
#define TPG_ENABLE_STUCK XTPG_PTRN_CTL_EN_STUCK_MASK
#define TPG_ENABLE_NOISE XTPG_PTRN_CTL_EN_NOISE_MASK
#define TPG_ENABLE_MOTION XTPG_PTRN_CTL_EN_MOTION_MASK
#define TPG_In32 XTpg_In32
#define TPG_Out32 XTpg_Out32
#define XTPG_ReadReg XTpg_ReadReg
#define XTPG_WriteReg XTpg_WriteReg
/*@}*/
/** @name Interrupt Enable and Status Registers Offsets
* @{
*/
/**
* Interrupt status register generates a interrupt if the corresponding bits of
* interrupt enable register bits are set.
*/
#define XTPG_ISR_OFFSET XTPG_STATUS_OFFSET /**< Interrupt Status Offset */
#define XTPG_IER_OFFSET XTPG_IRQ_EN_OFFSET /**< Interrupt Enable Offset */
/*@}*/
/***************** Macros (Inline Functions) Definitions *********************/
#define XTpg_In32 Xil_In32 /**< Input Operation */
#define XTpg_Out32 Xil_Out32 /**< Output Operation */
/*****************************************************************************/
/**
*
* This function macro reads the given register.
*
* @param BaseAddress is the base address of the TPG core.
* @param RegOffset is the register offset of the register (defined at
* top of this file).
*
* @return 32-bit value of the register.
*
* @note C-style signature:
* u32 XTpg_ReadReg(u32 BaseAddress, u32 RegOffset)
*
******************************************************************************/
#define XTpg_ReadReg(BaseAddress, RegOffset) \
XTpg_In32((BaseAddress) + (u32)(RegOffset))
/*****************************************************************************/
/**
*
* This function macro writes the given register.
*
* @param BaseAddress is the base address of the TPG core.
* @param RegOffset is the register offset of the register (defined at
* top of this file).
* @param Data is the 32-bit value to write into the register.
*
* @return None.
*
* @note C-style signature:
* void XTpg_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
*
******************************************************************************/
#define XTpg_WriteReg(BaseAddress, RegOffset, Data) \
XTpg_Out32((BaseAddress) + (u32)(RegOffset), (Data))
/**************************** Type Definitions *******************************/
/************************** Function Prototypes ******************************/
/************************** Variable Declarations ****************************/
#ifdef __cplusplus
}
#endif
#endif /* End of protection macro */

209
XilinxProcessorIPLib/drivers/tpg/src/xtpg_intr.c Executable file
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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xtpg_intr.c
*
* This file contains interrupt related functions of the TPG core.
* Please see xtpg.h for more details of the driver.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ----- ------- --------------------------------------------------
* 3.0 adk 02/19/14 First Release
* Implemented the following functions:
* XTpg_IntrHandler and XTpg_SetCallBack.
*
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xtpg.h"
/************************** Constant Definitions *****************************/
/***************** Marcos (Inline Functions) Definitions *********************/
/**************************** Type Definitions *******************************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/************************** Function Definitions *****************************/
/*****************************************************************************/
/**
*
* This function is the interrupt handler for the TPG driver.
*
* This handler reads the pending interrupt from the STATUS register,
* determines the source of the interrupts and calls the respective
* callbacks for the interrupts that are enabled in IRQ_ENABLE register,
* and finally clears the interrupts.
*
* The application is responsible for connecting this function to the interrupt
* system. Application beyond this driver is also responsible for providing
* callbacks to handle interrupts and installing the callbacks using
* XTpg_SetCallBack() during initialization phase.
*
* @param InstancePtr is a pointer to the XTpg instance that
* just interrupted.
*
* @return None.
*
* @note Interrupt interface should be enabled.
*
******************************************************************************/
void XTpg_IntrHandler(void *InstancePtr)
{
u32 PendingIntr;
u32 ErrorStatus;
XTpg *XTpgPtr = NULL;
XTpgPtr = (XTpg *) ((void *)InstancePtr);
/* Verify Arguments. */
Xil_AssertVoid(XTpgPtr != NULL);
Xil_AssertVoid(XTpgPtr->IsReady == (u32)(XIL_COMPONENT_IS_READY));
Xil_AssertVoid(XTpgPtr->Config.HasIntcIf != (u16)0x0);
/* Get pending interrupts */
PendingIntr = (u32)XTpg_IntrGetPending(XTpgPtr);
/* Error interrupt is occurring or spurious interrupt */
if (((u32)0x0 == ((PendingIntr) & ((u32)(XTPG_IXR_ALLINTR_MASK)))) ||
(((PendingIntr) & ((u32)(XTPG_IXR_SE_MASK))) ==
(u32)(XTPG_IXR_SE_MASK))) {
ErrorStatus = (PendingIntr) & ((u32)(XTPG_IXR_SE_MASK));
XTpgPtr->ErrCallBack(XTpgPtr->ErrRef, ErrorStatus);
/*
* The Error CallBack should reset the core and so
* there is no need to handle other interrupts
*/
}
/* A Processing Start interrupt has occurred */
if (((PendingIntr) & (XTPG_IXR_PROCS_STARTED_MASK)) ==
(XTPG_IXR_PROCS_STARTED_MASK)) {
XTpgPtr->ProcStartCallBack(XTpgPtr->ProcStartRef);
}
/* A Frame Done interrupt has occurred */
if (((PendingIntr) & (XTPG_IXR_EOF_MASK)) == (XTPG_IXR_EOF_MASK)) {
XTpgPtr->FrameDoneCallBack(XTpgPtr->FrameDoneRef);
}
/* Clear pending interrupts */
XTpg_IntrClear(XTpgPtr, PendingIntr);
}
/*****************************************************************************/
/**
*
* This function installs an asynchronous callback function for the given
* HandlerType.
*
* <pre>
* HandlerType Callback Function Type
* ----------------------- ----------------------
* XTPG_HANDLER_FRAMEDONE FrameDoneCallBack
* XTPG_HANDLER_PROCSTART ProcStartCallBack
* XTPG_HANDLER_ERROR ErrCallBack
*
* </pre>
*
* @param InstancePtr is a pointer to the XTpg instance to be worked on.
* @param HandlerType specifies which callback is to be attached.
* @param CallBackFunc is the address of the callback function.
* @param CallBackRef is a user data item that will be passed to the
* callback function when it is invoked.
*
* @return
* - XST_SUCCESS when handler is installed.
* - XST_INVALID_PARAM when HandlerType is invalid.
*
* @note Invoking this function for a handler that already has been
* installed replaces it with the new handler.
*
******************************************************************************/
int XTpg_SetCallBack(XTpg *InstancePtr, u32 HandlerType,
void *CallBackFunc, void *CallBackRef)
{
int Status;
/* Verify arguments. */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady ==
(u32)(XIL_COMPONENT_IS_READY));
/* Setting the handlerType */
switch (HandlerType) {
case XTPG_HANDLER_PROCSTART:
InstancePtr->ProcStartCallBack =
(XTpg_CallBack)((void *)CallBackFunc);
InstancePtr->ProcStartRef = CallBackRef;
Status = (XST_SUCCESS);
break;
case XTPG_HANDLER_FRAMEDONE:
InstancePtr->FrameDoneCallBack =
(XTpg_CallBack)((void *)CallBackFunc);
InstancePtr->FrameDoneRef = CallBackRef;
Status = (XST_SUCCESS);
break;
case XTPG_HANDLER_ERROR:
InstancePtr->ErrCallBack =
(XTpg_ErrorCallBack)((void *)CallBackFunc);
InstancePtr->ErrRef = CallBackRef;
Status = (XST_SUCCESS);
break;
default:
Status = (XST_INVALID_PARAM);
break;
}
return Status;
}

109
XilinxProcessorIPLib/drivers/tpg/src/xtpg_selftest.c Executable file
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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xtpg_selftest.c
*
* This file contains the self-test functions for the TPG driver.
* The self test function reads the Version Register.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ----- ------- ----------------------------------------------
* 3.0 adk 02/19/14 First Release.
* Implemented XTpg_SelfTest function.
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xtpg.h"
#include "xstatus.h"
/************************** Constant Definitions *****************************/
/***************** Macros (Inline Functions) Definitions *********************/
/**************************** Type Definitions *******************************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/************************** Function Definitions *****************************/
/*****************************************************************************/
/**
*
* This function reads Version register of TPG core and compares with zero
* as part of self test.
*
* @param InstancePtr is a pointer to the TPG instance.
*
* @return
* - XST_SUCCESS if the Version register read test was successful.
* - XST_FAILURE if the Version register read test failed.
*
* @note None.
*
******************************************************************************/
int XTpg_SelfTest(XTpg *InstancePtr)
{
u32 Version;
int Status;
/* Verify arguments. */
Xil_AssertNonvoid(InstancePtr != NULL);
/* Read TPG core version register. */
Version = XTpg_ReadReg(InstancePtr->Config.BaseAddress,
(XTPG_VERSION_OFFSET));
/* Compare version with zero. */
if(Version != (u32)0x0) {
Status = (XST_SUCCESS);
}
else {
Status = (XST_FAILURE);
}
return Status;
}

108
XilinxProcessorIPLib/drivers/tpg/src/xtpg_sinit.c Executable file
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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xtpg_sinit.c
*
* This file contains static initialization methods for Xilinx TPG core
* driver.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- --------------------------------------------------
* 3.0 adk 02/19/14 First release.
* Implemented the following functions:
* XTpg_LookupConfig.
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xtpg.h"
#include "xparameters.h"
/************************** Constant Definitions *****************************/
/***************** Macros (Inline Functions) Definitions *********************/
/**************************** Type Definitions *******************************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/************************** Function Definitions *****************************/
/*****************************************************************************/
/**
*
* This function returns a reference to an XTpg_Config structure based on
* the unique device id, <i>DeviceId</i>. The return value will refer to an
* entry in the device configuration table defined in the xtpg_g.c file.
*
* @param DeviceId is the unique Device ID of the device for the lookup
* operation.
*
* @return CfgPtr is a reference to a config record in the configuration
* table (in xtpg_g.c) corresponding to <i>DeviceId</i>, or NULL
* if no match is found.
*
* @note None.
*
******************************************************************************/
XTpg_Config *XTpg_LookupConfig(u16 DeviceId)
{
extern XTpg_Config XTpg_ConfigTable[XPAR_TPG_NUM_INSTANCES];
XTpg_Config *CfgPtr = NULL;
u32 Index;
/* To get the reference pointer to XTpg_Config structure */
for (Index = (u32)0x0; Index < (u32)(XPAR_TPG_NUM_INSTANCES);
Index++) {
/* Compare device Id with configTable's device Id*/
if (XTpg_ConfigTable[Index].DeviceId == DeviceId) {
CfgPtr = &XTpg_ConfigTable[Index];
break;
}
}
return (XTpg_Config *)CfgPtr;
}