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ycrcb2rgb: Deprecated ycrcb2rgb_v6_0 driver

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Added ycrcb2rgb_v7_0 driver with ACTIVE state

Signed-off-by: Shadul Shaikh <shaduls@xilinx.com>
Acked-by: Srikanth Vemula <svemula@xilinx.com>
This commit is contained in:
Shadul Shaikh 2014-07-15 19:10:03 +05:30 • committed by Jagannadha Sutradharudu Teki
parent b52598a34e
commit 89ae17e5b3
7 changed files with 993 additions and 0 deletions
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45
XilinxProcessorIPLib/drivers/ycrcb2rgb/data/ycrcb2rgb.mdd Executable file
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###############################################################################
#
# Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
#
# Use of the Software is limited solely to applications:
# (a) running on a Xilinx device, or
# (b) that interact with a Xilinx device through a bus or interconnect.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
#
# Except as contained in this notice, the name of the Xilinx shall not be used
# in advertising or otherwise to promote the sale, use or other dealings in
# this Software without prior written authorization from Xilinx.
#
###############################################################################
OPTION psf_version = 2.1;
BEGIN driver ycrcb2rgb
OPTION supported_peripherals = (v_ycrcb2rgb);
OPTION driver_state = ACTIVE;
OPTION copyfiles = all;
OPTION VERSION = 7.0;
OPTION NAME = ycrcb2rgb;
END driver

38
XilinxProcessorIPLib/drivers/ycrcb2rgb/data/ycrcb2rgb.tcl Executable file
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###############################################################################
#
# Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
#
# Use of the Software is limited solely to applications:
# (a) running on a Xilinx device, or
# (b) that interact with a Xilinx device through a bus or interconnect.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
#
# Except as contained in this notice, the name of the Xilinx shall not be used
# in advertising or otherwise to promote the sale, use or other dealings in
# this Software without prior written authorization from Xilinx.
#
###############################################################################
proc generate {drv_handle} {
xdefine_include_file $drv_handle "xparameters.h" "YCRCB2RGB" "NUM_INSTANCES" "DEVICE_ID" "C_BASEADDR" "C_HIGHADDR" "C_S_AXIS_VIDEO_DATA_WIDTH" "C_MAX_COLS" "C_ACTIVE_COLS" "C_ACTIVE_ROWS" "C_MWIDTH" "C_COEF_RANGE" "C_ACOEF" "C_BCOEF" "C_CCOEF" "C_DCOEF" "C_ROFFSET" "C_GOFFSET" "C_BOFFSET" "C_HAS_CLIP" "C_HAS_CLAMP" "C_RGBMAX" "C_RGBMIN"
xdefine_canonical_xpars $drv_handle "xparameters.h" "YCRCB2RGB" "DEVICE_ID" "C_BASEADDR" "C_HIGHADDR" "C_S_AXIS_VIDEO_DATA_WIDTH" "C_MAX_COLS" "C_ACTIVE_COLS" "C_ACTIVE_ROWS" "C_MWIDTH" "C_COEF_RANGE" "C_ACOEF" "C_BCOEF" "C_CCOEF" "C_DCOEF" "C_ROFFSET" "C_GOFFSET" "C_BOFFSET" "C_HAS_CLIP" "C_HAS_CLAMP" "C_RGBMAX" "C_RGBMIN"
}

181
XilinxProcessorIPLib/drivers/ycrcb2rgb/examples/example.c Executable file
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/******************************************************************************
*
* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file example.c
*
* This file demonstrates how to use Xilinx YCrCb to RGB Color Space Converter
* (YCRCB2RGB) driver on Xilinx YCrCb to RGB Color Space Converter (YCRCB2RGB)
* core. This code does not cover the Xilinx TimeBase setup and any other
* configuration which might be required to get the YCRCB2RGB device working properly.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 5.00a tb 02/28/12 Updates for the v5.00.a release
* </pre>
*
* ***************************************************************************
*/
#include "ycrcb2rgb.h"
#include "xparameters.h"
/***************************************************************************/
// YCrCb to RGB Color Space Converter Register Reading Example
// This function provides an example of how to read the current configuration
// settings of the YCRCB2RGB core.
/***************************************************************************/
void report_ycc_settings(u32 BaseAddress) {
xil_printf("YCrCb to RGB Color Space Converter Core Configuration:\r\n");
xil_printf(" Version: 0x%08x\r\n", YCC_ReadReg(BaseAddress, YCC_VERSION));
xil_printf(" Enable Bit: %1d\r\n", YCC_ReadReg(BaseAddress, YCC_CONTROL) & YCC_CTL_EN_MASK);
xil_printf(" Register Update Bit: %1d\r\n", (YCC_ReadReg(BaseAddress, YCC_CONTROL) & YCC_CTL_RUE_MASK) >> 1);
xil_printf(" Reset Bit: %1d\r\n", (YCC_ReadReg(BaseAddress, YCC_CONTROL) & YCC_RST_RESET) >> 31);
xil_printf(" AutoReset Bit: %1d\r\n", (YCC_ReadReg(BaseAddress, YCC_CONTROL) & YCC_RST_AUTORESET) >> 30);
xil_printf(" Columns=0x%08x, Rows=0x%08x\r\n",
(YCC_ReadReg(BaseAddress, YCC_ACTIVE_SIZE)>>16),
(YCC_ReadReg(BaseAddress, YCC_ACTIVE_SIZE)&0xFFFF));
xil_printf(" Acoef=0x%08x, Bcoef=0x%08x, Ccoef=0x%08x, Dcoef=0x%08x\r\n",
YCC_ReadReg(BaseAddress, YCC_ACOEF),
YCC_ReadReg(BaseAddress, YCC_BCOEF),
YCC_ReadReg(BaseAddress, YCC_CCOEF),
YCC_ReadReg(BaseAddress, YCC_DCOEF));
xil_printf(" R Offset=0x%08x, G Offset=0x%08x, B Offset=0x%08x\r\n",
YCC_ReadReg(BaseAddress, YCC_ROFFSET),
YCC_ReadReg(BaseAddress, YCC_GOFFSET),
YCC_ReadReg(BaseAddress, YCC_BOFFSET));
xil_printf(" RGB Max=0x%08x, RGB Min=0x%08x\r\n",
YCC_ReadReg(BaseAddress, YCC_RGBMAX),
YCC_ReadReg(BaseAddress, YCC_RGBMIN));
}
/***************************************************************************/
// RGB to YCrCb Color Space Converter Register Update Example
// This function provides an example of the process used to update
// the coefficient and offset registers in the YCrCb2RGB core.
// In most video systems, it is expected that this process would be executed
// in response to an interrupt connected to the SOF timing signal
// or a timeout signal associated with a watchdog timer.
/***************************************************************************/
void YCC_Update_Example() {
//Enable the YCRCB2RGB software enable
YCC_Enable(XPAR_YCRCB2RGB_0_BASEADDR);
//Disable register updates.
//This is the default operating mode for the CCM core, and allows
//registers to be updated without effecting the core's behavior.
YCC_RegUpdateDisable(XPAR_YCRCB2RGB_0_BASEADDR);
//Set the Active Columns and Rows
YCC_WriteReg(XPAR_YCRCB2RGB_0_BASEADDR, YCC_ACTIVE_SIZE, (1280<<16)+720); //1280x720
//Set the coefficients
// These values are floating point values in the range: [0.0, 1.0)
// These are represented as integers by multiplying by 2^16,
// resulting in an integer value in the range from [0, 65535]
YCC_WriteReg(XPAR_YCRCB2RGB_0_BASEADDR, YCC_ACOEF, 22978);
YCC_WriteReg(XPAR_YCRCB2RGB_0_BASEADDR, YCC_BCOEF, -11704);
YCC_WriteReg(XPAR_YCRCB2RGB_0_BASEADDR, YCC_CCOEF, -5641);
YCC_WriteReg(XPAR_YCRCB2RGB_0_BASEADDR, YCC_DCOEF, 29049);
//Set the offsets
// For Valid range = [-2147483648, 2147483647]
YCC_WriteReg(XPAR_YCRCB2RGB_0_BASEADDR, YCC_ROFFSET, -6390272); //ROFFSET = 16
YCC_WriteReg(XPAR_YCRCB2RGB_0_BASEADDR, YCC_GOFFSET, 3932416); //GOFFSET = 128
YCC_WriteReg(XPAR_YCRCB2RGB_0_BASEADDR, YCC_BOFFSET, -7944448); //BOFFSET = 128
//Set the Clip/Clamp
// For 8-bit color: Valid range = [0, 255]
// For 10-bit color: Valid range = [0, 1023]
// For 12-bit color: Valid range = [0, 4095]
// For 16-bit color: Valid range = [0, 65535]
YCC_WriteReg(XPAR_YCRCB2RGB_0_BASEADDR, YCC_RGBMAX, 240); //RGBMAX = 240
YCC_WriteReg(XPAR_YCRCB2RGB_0_BASEADDR, YCC_RGBMIN, 16); //RGBMIN = 16
//Enable register updates.
//This mode will cause the coefficient and offset registers internally
//to the CCM core to automatically be updated on the next SOF.
YCC_RegUpdateEnable(XPAR_YCRCB2RGB_0_BASEADDR);
}
/*****************************************************************************/
//
// This is the main function for the YCrCb2RGB example.
//
/*****************************************************************************/
int main(void)
{
struct ycc_coef_inputs coef_in;
struct ycc_coef_outputs coef_out;
// Print the current settings for the YCrCb2RGB core
report_ycc_settings(XPAR_YCRCB2RGB_0_BASEADDR);
// Call the YCrCb2RGB example, specify the Device ID generated in xparameters.h
YCC_Update_Example(XPAR_YCRCB2RGB_0_BASEADDR);
// Read the current YCrCb2RGB core coefficients
YCC_get_coefficients(XPAR_YCRCB2RGB_0_BASEADDR, &coef_out);
// Setup coef_in for SD_ITU_601, 16_to_235_for_Studio_Equipment
// and data width of 8-bits
YCC_select_standard(0, 1, XPAR_YCRCB2RGB_0_S_AXIS_VIDEO_DATA_WIDTH, &coef_in);
// Translate into YCrCb2RGB core coefficients
YCC_coefficient_translation(&coef_in, &coef_out, XPAR_YCRCB2RGB_0_S_AXIS_VIDEO_DATA_WIDTH, XPAR_YCRCB2RGB_0_MWIDTH);
// Program the new YCrCb2RGB core coefficients
YCC_set_coefficients(XPAR_YCRCB2RGB_0_BASEADDR, &coef_out);
// Print the current settings for the YCrCb2RGB core
report_ycc_settings(XPAR_YCRCB2RGB_0_BASEADDR);
return 0;
}

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XilinxProcessorIPLib/drivers/ycrcb2rgb/examples/index.html Executable file
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2 Final//EN">
<html>
<head>
<meta http-equiv="Content-Language" content="en-us">
<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
<title>Driver example applications</title>
<link rel="stylesheet" type="text/css" href="../help.css">
</head>
<body bgcolor="#FFFFFF">
<h1> Example Applications for the driver ycrcb2rgb_v6_0 </h1>
<HR>
<ul>
<li>example.c <a href="example.c">(source)</a> </li>
</ul>
<p><font face="Times New Roman" color="#800000">Copyright <20> 1995-2014 Xilinx, Inc. All rights reserved.</font></p>
</body>
</html>

29
XilinxProcessorIPLib/drivers/ycrcb2rgb/src/Makefile Executable file
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COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
LEVEL=0
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}
INCLUDEFILES=*.h
LIBSOURCES=*.c
OUTS = *.o
libs:
echo "Compiling ycrcb2rgb"
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
make clean
include:
${CP} $(INCLUDEFILES) $(INCLUDEDIR)
clean:
rm -rf ${OUTS}

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XilinxProcessorIPLib/drivers/ycrcb2rgb/src/ycrcb2rgb.c Executable file
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/******************************************************************************
*
* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file rgb2ycrcb.c
*
* This is main code of Xilinx YCrCb to RGB Color Space Converter (YCRCB2RGB)
* device driver. Please see ycrcb2rgb.h for more details of the driver.
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 5.00a tb 02/28/12 Updated for YCRCB2RGB v5.00.a
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "ycrcb2rgb.h"
#include "xenv.h"
#include "stdio.h"
double ycc_pow2(u32 a) { return( (a>0) ? (1 << a) : 1.0/(1 << (-a)) ); }
/*****************************************************************************/
// Note: Most of the functions are currently implemented as high-performance
// macros within ycrcb2rgb.h
/*****************************************************************************/
/*****************************************************************************/
/**
*
* Select input coefficients for 4 supported Standards and 3 Input Ranges.
*
* @param standard_sel is the standards selection: 0 = SD_ITU_601
* 1 = HD_ITU_709__1125_NTSC
* 2 = HD_ITU_709__1250_PAL
* 3 = YUV
* @param input_range is the limit on the range of the data: 0 = 16_to_240_for_TV,
* 1 = 16_to_235_for_Studio_Equipment,
* 3 = 0_to_255_for_Computer_Graphics
* @param data_width has a valid range of [8,10,12,16]
* @param coef_in is a pointer to a ycc_coef_inputs data structure.
*
* @return None.
*
* @note
*
******************************************************************************/
void YCC_select_standard(u32 standard_sel, u32 input_range, u32 data_width, struct ycc_coef_inputs *coef_in)
{
double acoef[4][3] = {0.299, 0.299, 0.2568, 0.299, 0.299, 0.2568, 0.2126, 0.2126, 0.1819, 0.299, 0.299, 0.299};
double bcoef[4][3] = {0.114, 0.114, 0.0979, 0.114, 0.114, 0.0979, 0.0722, 0.0722, 0.0618, 0.114, 0.114, 0.114};
double ccoef[4][3] = {0.713, 0.7295, 0.5910, 0.713, 0.7295, 0.5910, 0.6350, 0.6495, 0.6495, 0.877283, 0.877283, 0.877283};
double dcoef[4][3] = {0.564, 0.5772, 0.5772, 0.564, 0.5772, 0.5772, 0.5389, 0.5512, 0.5512, 0.492111, 0.492111, 0.492111};
u32 yoffset = 1<<(data_width-4);
u32 coffset = 1<<(data_width-1);
u32 max[3] = {(240*(1<<(data_width-8))), (235*(1<<(data_width-8))), ((1<<data_width)-1)};
u32 min[3] = { (16*(1<<(data_width-8))), (16*(1<<(data_width-8))), 0};
coef_in->acoef = acoef[standard_sel][input_range];
coef_in->bcoef = bcoef[standard_sel][input_range];
coef_in->ccoef = ccoef[standard_sel][input_range];
coef_in->dcoef = dcoef[standard_sel][input_range];
coef_in->yoffset = yoffset;
coef_in->cboffset = coffset;
coef_in->croffset = coffset;
coef_in->rgbmax = max[input_range];
coef_in->rgbmin = min[input_range];
}
/*****************************************************************************/
/**
*
* Translate input coefficients into coefficients that can be programmed into the
* YCrCb2RGB core.
*
* @param coef_in is a pointer to a rgb_coef_inputs data structure.
* @param coef_out is a pointer to a rgb_coef_output data structure.
*
* @return The 32-bit value: bit(0)= 1=data width outside range [8, 10, 12, 16]
* bit(1)= Acoef + Bcoef > 1.0
* bit(2)= Y Offset outside data width range [-2^data_width, (2^data_width)-1]
* bit(3)= Cb Offset outside data width range [-2^data_width, (2^data_width)-1]
* bit(4)= Cr Offset outside data width range [-2^data_width, (2^data_width)-1]
* bit(5)= RGB Max outside data width range [0, (2^data_width)-1]
* bit(6)= RGB Min outside data width range [0, (2^data_width)-1]
*
* @note
*
******************************************************************************/
u32 YCC_coefficient_translation(struct ycc_coef_inputs *coef_in, struct ycc_coef_outputs *coef_out, u32 data_width, u32 mwidth)
{
u32 ret_val = 0;
u32 scale_coeffs;
double scale_ic2m;
u32 coef_range;
double acoef, bcoef, ccoef, dcoef;
double acr, bcr, ccr, dcr;
u32 ac, bc, cc, dc;
u32 yoffset, cboffset, croffset;
u32 rgbmax, rgbmin;
u32 iwidth, owidth, cwidth;
double rounding_const;
iwidth = data_width;
owidth = data_width;
coef_range = 2;
cwidth = 17;
acoef = coef_in->acoef;
bcoef = coef_in->bcoef;
ccoef = coef_in->ccoef;
dcoef = coef_in->dcoef;
yoffset = coef_in->yoffset;
cboffset = coef_in->cboffset;
croffset = coef_in->croffset;
rgbmax = coef_in->rgbmax;
rgbmin = coef_in->rgbmin;
if((acoef + bcoef) > 1.0) {
printf("WARNING: Acoef (%lf) + Bcoef (%lf) can not be more then 1.0\r\n",acoef, bcoef);
ret_val = ret_val | 0x1;
}
if(yoffset < -(1<<iwidth) || yoffset > (1<<iwidth)-1) {
printf("WARNING: Y Offset (%u) is outside the data width range [%u, %u]\r\n",
(unsigned int)yoffset, (unsigned int)-(1<<iwidth), (unsigned int)(1<<iwidth)-1);
ret_val = ret_val | 0x2;
}
if(cboffset < -(1<<iwidth) || cboffset > (1<<iwidth)-1) {
printf("WARNING: Cb Offset (%u) is outside the data width range [%u, %u]\r\n",
(unsigned int)cboffset, (unsigned int)-(1<<iwidth), (unsigned int)(1<<iwidth)-1);
ret_val = ret_val | 0x4;
}
if(croffset < -(1<<iwidth) || croffset > (1<<iwidth)-1) {
printf("WARNING: Cr Offset (%u) is outside the data width range [%u, %u]\r\n",
(unsigned int)croffset, (unsigned int)-(1<<iwidth), (unsigned int)(1<<iwidth)-1);
ret_val = ret_val | 0x8;
}
if(rgbmax < 0 || rgbmax > (1<<iwidth)-1) {
printf("WARNING: RGB Max (%u) is outside the data width range [0, %u]\r\n",
(unsigned int)rgbmax, (unsigned int)(1<<iwidth)-1);
ret_val = ret_val | 0x10;
}
if(rgbmin < 0 || rgbmin > (1<<iwidth)-1) {
printf("WARNING: RGB Min (%u) is outside the data width range [0, %u]\r\n",
(unsigned int)rgbmin, (unsigned int)(1<<iwidth)-1);
ret_val = ret_val | 0x20;
}
acr = 1/ccoef;
bcr = -(acoef/ccoef/(1-acoef-bcoef));
ccr = -(bcoef/dcoef/(1-acoef-bcoef));
dcr = 1/dcoef;
scale_coeffs = ycc_max(1, (1 << (cwidth-coef_range-1)));
rounding_const = ycc_pow2(mwidth - owidth - coef_range -2); // +0.5 turns truncation to biased rounding
scale_ic2m = ycc_pow2(1+mwidth - iwidth - cwidth );
// Quantize coefficients:
ac = (u32) (acr*scale_coeffs); // round, wrap
bc = (u32) (bcr*scale_coeffs);
cc = (u32) (ccr*scale_coeffs);
dc = (u32) (dcr*scale_coeffs);
coef_out->acoef = ac;
coef_out->bcoef = bc;
coef_out->ccoef = cc;
coef_out->dcoef = dc;
// Assuming signals are OWIDTH+1 bits wide after the offset compensating rounders / adders:
coef_out->roffset = (u32) ((rounding_const - (ac*croffset + yoffset*scale_coeffs))*scale_ic2m);
coef_out->goffset = (u32) ((rounding_const - (((bc*croffset)+(cc*cboffset)) + yoffset*scale_coeffs))*scale_ic2m);
coef_out->boffset = (u32) ((rounding_const - (dc*cboffset + yoffset*scale_coeffs))*scale_ic2m);
coef_out->rgbmax = rgbmax;
coef_out->rgbmin = rgbmin;
return ret_val;
}
/*****************************************************************************/
/**
*
* Program the YCrCb2RGB coefficient/offset registers.
*
* @param BaseAddress is the Xilinx EDK base address of the YCrCb2RGB core (from xparameters.h)
* @param coef_out is a pointer to a rgb_coef_output data structure.
*
* @return None.
*
* @note
*
******************************************************************************/
void YCC_set_coefficients(u32 BaseAddress, struct ycc_coef_outputs *coef_out)
{
YCC_WriteReg(BaseAddress, YCC_ACOEF, coef_out->acoef); //ACOEF
YCC_WriteReg(BaseAddress, YCC_BCOEF, coef_out->bcoef); //BCOEF
YCC_WriteReg(BaseAddress, YCC_CCOEF, coef_out->ccoef); //CCOEF
YCC_WriteReg(BaseAddress, YCC_DCOEF, coef_out->dcoef); //DCOEF
YCC_WriteReg(BaseAddress, YCC_ROFFSET, coef_out->roffset); //ROFFSET
YCC_WriteReg(BaseAddress, YCC_GOFFSET, coef_out->goffset); //GOFFSET
YCC_WriteReg(BaseAddress, YCC_BOFFSET, coef_out->boffset); //BOFFSET
YCC_WriteReg(BaseAddress, YCC_RGBMAX, coef_out->rgbmax); //RGBMAX
YCC_WriteReg(BaseAddress, YCC_RGBMIN, coef_out->rgbmin); //RGBMIN
}
/*****************************************************************************/
/**
*
* Read the YCrCb2RGB coefficient/offset registers.
*
* @param BaseAddress is the Xilinx EDK base address of the YCrCb2RGB core (from xparameters.h)
* @param coef_out is a pointer to a rgb_coef_output data structure.
*
* @return None.
*
* @note
*
******************************************************************************/
void YCC_get_coefficients(u32 BaseAddress, struct ycc_coef_outputs *coef_out)
{
coef_out->acoef = YCC_ReadReg(BaseAddress, YCC_ACOEF);
coef_out->bcoef = YCC_ReadReg(BaseAddress, YCC_BCOEF);
coef_out->ccoef = YCC_ReadReg(BaseAddress, YCC_CCOEF);
coef_out->dcoef = YCC_ReadReg(BaseAddress, YCC_DCOEF);
coef_out->roffset = YCC_ReadReg(BaseAddress, YCC_ROFFSET);
coef_out->goffset = YCC_ReadReg(BaseAddress, YCC_GOFFSET);
coef_out->boffset = YCC_ReadReg(BaseAddress, YCC_BOFFSET);
coef_out->rgbmax = YCC_ReadReg(BaseAddress, YCC_RGBMAX);
coef_out->rgbmin = YCC_ReadReg(BaseAddress, YCC_RGBMIN);
}

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XilinxProcessorIPLib/drivers/ycrcb2rgb/src/ycrcb2rgb.h Executable file
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@ -0,0 +1,417 @@
/******************************************************************************
*
* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file rgb2ycrcb.h
*
* This header file contains identifiers and register-level driver functions (or
* macros) that can be used to access the Xilinx YCrCb to RGB Color Space Converter
* (RGB2YCRCB) device.
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 5.00a tb 02/28/12 Updated for YCRCB2RGB V5.00.a
* 5.01a bao 12/28/12 Converted from xio.h to xil_io.h, translating basic types,
* MB cache functions, exceptions and assertions to xil_io
* format
* 6.0 adk 19/12/13 Updated as per the New Tcl API's
*
******************************************************************************/
#ifndef YCRCB2RGB_DRIVER_H /* prevent circular inclusions */
#define YCRCB2RGB_DRIVER_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_io.h"
/************************** Constant Definitions *****************************/
/**
* Register Offsets
*/
/* General Control Registers */
#define YCC_CONTROL 0x000 /**< Control */
#define YCC_STATUS 0x004 /**< Status */
#define YCC_ERROR 0x008 /**< Error */
#define YCC_IRQ_EN 0x00C /**< IRQ Enable */
#define YCC_VERSION 0x010 /**< Version */
#define YCC_SYSDEBUG0 0x014 /**< System Debug 0 */
#define YCC_SYSDEBUG1 0x018 /**< System Debug 1 */
#define YCC_SYSDEBUG2 0x01C /**< System Debug 2 */
/* Timing Control Registers */
#define YCC_ACTIVE_SIZE 0x020 /**< Active Size (V x H) */
#define YCC_TIMING_STATUS 0x024 /**< Timing Measurement Status */
/* Core Specific Registers */
#define YCC_RGBMAX 0x100 /**< RGB Clipping */
#define YCC_RGBMIN 0x104 /**< RGB Clamping */
#define YCC_ROFFSET 0x108 /**< R Offset */
#define YCC_GOFFSET 0x10C /**< G Offset */
#define YCC_BOFFSET 0x110 /**< B Offset */
#define YCC_ACOEF 0x114 /**< Matrix Coversion Coefficient */
#define YCC_BCOEF 0x118 /**< Matrix Coversion Coefficient */
#define YCC_CCOEF 0x11C /**< Matrix Coversion Coefficient */
#define YCC_DCOEF 0x120 /**< Matrix Coversion Coefficient */
/*
* CCM Control Register bit definition
*/
#define YCC_CTL_EN_MASK 0x00000001 /**< CCM Enable */
#define YCC_CTL_RUE_MASK 0x00000002 /**< CCM Register Update Enable */
/*
* CCM Reset Register bit definition
*/
#define YCC_RST_RESET 0x80000000 /**< Software Reset - Instantaneous */
#define YCC_RST_AUTORESET 0x40000000 /**< Software Reset - Auto-synchronize to SOF */
/***************** Macros (Inline Functions) Definitions *********************/
#define YCC_In32 Xil_In32
#define YCC_Out32 Xil_Out32
/*****************************************************************************/
/**
*
* This macro enables a YCrCb2RGB device.
*
* @param BaseAddress is the Xilinx EDK base address of the YCrCb2RGB core (from xparameters.h)
*
* @return None.
*
* @note
* C-style signature:
* void YCC_Enable(u32 BaseAddress);
*
******************************************************************************/
#define YCC_Enable(BaseAddress) \
YCC_WriteReg(BaseAddress, YCC_CONTROL, \
YCC_ReadReg(BaseAddress, YCC_CONTROL) | \
YCC_CTL_EN_MASK)
/*****************************************************************************/
/**
*
* This macro disables a YCrCb2RGB device.
*
* @param BaseAddress is the Xilinx EDK base address of the YCrCb2RGB core (from xparameters.h)
*
* @return None.
*
* @note
* C-style signature:
* void YCC_Disable(u32 BaseAddress);
*
******************************************************************************/
#define YCC_Disable(BaseAddress) \
YCC_WriteReg(BaseAddress, YCC_CONTROL, \
YCC_ReadReg(BaseAddress, YCC_CONTROL) & \
~YCC_CTL_EN_MASK)
/*****************************************************************************/
/**
*
* This macro tells a YCrCb2RGB device to pick up all the register value changes
* made so far by the software. The registers will be automatically updated
* on the next SOF signal on the core.
* It is up to the user to manually disable the register update after a sufficient
* amount if time.
*
* This function only works when the YCrCb2RGB core is enabled.
*
* @param BaseAddress is the Xilinx EDK base address of the YCrCb2RGB core (from xparameters.h)
*
* @return None.
*
* @note
* C-style signature:
* void YCC_RegUpdateEnable(u32 BaseAddress);
*
******************************************************************************/
#define YCC_RegUpdateEnable(BaseAddress) \
YCC_WriteReg(BaseAddress, YCC_CONTROL, \
YCC_ReadReg(BaseAddress, YCC_CONTROL) | \
YCC_CTL_RUE_MASK)
/*****************************************************************************/
/**
*
* This macro tells a YCrCb2RGB device not to update it's configuration registers made
* so far by the software. When disabled, changes to other configuration registers
* are stored, but do not effect the core's behavior.
*
* This function only works when the YCrCb2RGB core is enabled.
*
* @param BaseAddress is the Xilinx EDK base address of the YCrCb2RGB core (from xparameters.h)
*
* @return None.
*
* @note
* C-style signature:
* void YCC_RegUpdateDisable(u32 BaseAddress);
*
******************************************************************************/
#define YCC_RegUpdateDisable(BaseAddress) \
YCC_WriteReg(BaseAddress, YCC_CONTROL, \
YCC_ReadReg(BaseAddress, YCC_CONTROL) & \
~YCC_CTL_RUE_MASK)
/*****************************************************************************/
/**
*
* This macro resets a YCrCb2RGB device. This reset effects the core immediately,
* and may cause image tearing.
*
* This reset resets the YCrCb2RGB's configuration registers, and holds the core's outputs
* in their reset state until YCC_ClearReset() is called.
*
*
* @param BaseAddress is the Xilinx EDK base address of the YCrCb2RGB core (from xparameters.h)
*
* @return None.
*
* @note
* C-style signature:
* void YCC_Reset(u32 BaseAddress);
*
******************************************************************************/
#define YCC_Reset(BaseAddress) \
YCC_WriteReg(BaseAddress, YCC_CONTROL, YCC_RST_RESET) \
/*****************************************************************************/
/**
*
* This macro clears the YCrCb2RGB's reset flag (which is set using YCC_Reset(), and
* returns it to normal operation. This ClearReset effects the core immediately,
* and may cause image tearing.
*
*
* @param BaseAddress is the Xilinx EDK base address of the YCrCb2RGB core (from xparameters.h)
*
* @return None.
*
* @note
* C-style signature:
* void YCC_ClearReset(u32 BaseAddress);
*
******************************************************************************/
#define YCC_ClearReset(BaseAddress) \
YCC_WriteReg(BaseAddress, YCC_CONTROL, 0) \
/*****************************************************************************/
/**
*
* This macro resets a YCrCb2RGB device, but differs from YCC_Reset() in that it
* automatically synchronizes to the VBlank_in input of the core to prevent tearing.
*
* On the next rising-edge of VBlank_in following a call to YCC_AutoSyncReset(),
* all of the core's configuration registers and outputs will be reset, then the
* reset flag will be immediately released, allowing the core to immediately resume
* default operation.
*
* @param BaseAddress is the Xilinx EDK base address of the YCrCb2RGB core (from xparameters.h)
*
* @return None.
*
* @note
* C-style signature:
* void YCC_Reset(u32 BaseAddress);
*
******************************************************************************/
#define YCC_AutoSyncReset(BaseAddress) \
YCC_WriteReg(BaseAddress, YCC_CONTROL, YCC_RST_AUTORESET) \
/*****************************************************************************/
/**
*
* Read the given register.
*
* @param BaseAddress is the Xilinx EDK base address of the YCrCb2RGB core (from xparameters.h)
* @param RegOffset is the register offset of the register (defined at top of this file)
*
* @return The 32-bit value of the register
*
* @note
* C-style signature:
* u32 YCC_ReadReg(u32 BaseAddress, u32 RegOffset)
*
******************************************************************************/
#define YCC_ReadReg(BaseAddress, RegOffset) \
YCC_In32((BaseAddress) + (RegOffset))
/*****************************************************************************/
/**
*
* Write the given register.
*
* @param BaseAddress is the Xilinx EDK base address of the YCrCb2RGB core (from xparameters.h)
* @param RegOffset is the register offset of the register (defined at top of this file)
* @param Data is the 32-bit value to write to the register
*
* @return None.
*
* @note
* C-style signature:
* void YCC_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
*
******************************************************************************/
#define YCC_WriteReg(BaseAddress, RegOffset, Data) \
YCC_Out32((BaseAddress) + (RegOffset), (Data))
/************************** Function Prototypes ******************************/
struct ycc_coef_inputs
{
/* Pre-translated coefficient/offset data */
double acoef; //@- [ 0.0 - 1.0 ] 0.0 < ACOEFF + BCOEFF < 1.0
double bcoef; //@- [ 0.0 - 1.0 ] 0.0 < ACOEFF + BCOEFF < 1.0
double ccoef; //@- [ 0.0 - 0.9 ]
double dcoef; //@- [ 0.0 - 0.9 ]
u32 yoffset; //@- Offset for the Luminance Channel
u32 cboffset; //@- Offset for the Chrominance Channels
u32 croffset; //@- Offset for the Chrominance Channels
u32 rgbmax; //@- RGB Clipping
u32 rgbmin; //@- RGB Clamping
};
struct ycc_coef_outputs
{
/* Translated coefficient/offset data */
u32 acoef; //@- Translated ACoef
u32 bcoef; //@- Translated BCoef
u32 ccoef; //@- Translated CCoef
u32 dcoef; //@- Translated DCoef
u32 roffset; //@- Translated Offset for the R Channel
u32 goffset; //@- Translated Offset for the G Channel
u32 boffset; //@- Translated Offset for the B Channel
u32 rgbmax; //@- Translated RGB Clipping
u32 rgbmin; //@- Translated RGB Clamping
};
/*****************************************************************************/
/**
*
* Select input coefficients for 4 supported Standards and 3 Input Ranges.
*
* @param standard_sel is the standards selection: 0 = SD_ITU_601
* 1 = HD_ITU_709__1125_NTSC
* 2 = HD_ITU_709__1250_PAL
* 3 = YUV
* @param input_range is the limit on the range of the data: 0 = 16_to_240_for_TV,
* 1 = 16_to_235_for_Studio_Equipment,
* 3 = 0_to_255_for_Computer_Graphics
* @param data_width has a valid range of [8, 10,12,16]
* @param coef_in is a pointer to a ycc_coef_inputs data structure.
*
* @return None.
*
* @note
*
******************************************************************************/
void YCC_select_standard(u32 standard_sel, u32 input_range, u32 data_width, struct ycc_coef_inputs *coef_in);
/*****************************************************************************/
/**
*
* Translate input coefficients into coefficients that can be programmed into the
* YCrCb2RGB core.
*
* @param coef_in is a pointer to a ycc_coef_inputs data structure.
* @param coef_out is a pointer to a ycc_coef_output data structure.
* @param data_width is the bit width of the data
* @param mwidth is multiplicatio width value calculated by the core.
*
* @return The 32-bit value: bit(0)= 1=data width outside range [8, 10, 12, 16]
* bit(1)= Acoef + Bcoef > 1.0
* bit(2)= Y Offset outside data width range [-2^data_width, (2^data_width)-1]
* bit(3)= Cb Offset outside data width range [-2^data_width, (2^data_width)-1]
* bit(4)= Cr Offset outside data width range [-2^data_width, (2^data_width)-1]
* bit(5)= RGB Max outside data width range [0, (2^data_width)-1]
* bit(6)= RGB Min outside data width range [0, (2^data_width)-1]
*
* @note
*
******************************************************************************/
u32 YCC_coefficient_translation(struct ycc_coef_inputs *coef_in, struct ycc_coef_outputs *coef_out, u32 data_width, u32 mwidth);
/*****************************************************************************/
/**
*
* Program the YCrCb2RGB coefficient/offset registers.
*
* @param BaseAddress is the Xilinx EDK base address of the YCrCb2RGB core (from xparameters.h)
* @param coef_out is a pointer to a ycc_coef_output data structure.
*
* @return None.
*
* @note
*
******************************************************************************/
void YCC_set_coefficients(u32 BaseAddress, struct ycc_coef_outputs *coef_out);
/*****************************************************************************/
/**
*
* Read the YCrCb2RGB coefficient/offset registers.
*
* @param BaseAddress is the Xilinx EDK base address of the YCrCb2RGB core (from xparameters.h)
* @param coef_out is a pointer to a ycc_coef_output data structure.
*
* @return None.
*
* @note
*
******************************************************************************/
void YCC_get_coefficients(u32 BaseAddress, struct ycc_coef_outputs *coef_out);
#define ycc_max(a,b) (((a)>(b)) ? (a) : (b))
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */