stv0g/embeddedsw
1
0
Fork 0
Code Issues Pull requests Releases Wiki Activity

sw_apps:zynqmp_fsbl: Changes in FSBL to match register changes

Browse source 
This change is done to match the change in the hardware registers
used to enable the RSA authentication during boot.
Also a small logical error is corrected.

Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
This commit is contained in:
Sarat Chand Savitala 2015-02-17 00:38:31 +05:30 • committed by Nava kishore Manne
parent b6aa8be915
commit 8b1c93702d
2 changed files with 7 additions and 13 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

16
lib/sw_apps/zynqmp_fsbl/src/xfsbl_hw.h
View file

@ -142,14 +142,8 @@ extern "C" {
/**
* Register: EFUSE_SEC_CTRL
*/
#define EFUSE_SEC_CTRL ( ( EFUSE_BASEADDR ) + 0X00001000U )
/**
* Register: EFUSE_RSA_CTRL
*/
#define EFUSE_RSA_CTRL ( ( EFUSE_BASEADDR ) + 0X00001060U )
#define EFUSE_RSA_CTRL_RSA_EN_MASK 0X00000001U
#define EFUSE_SEC_CTRL ( ( EFUSE_BASEADDR ) + 0X00001058U )
#define EFUSE_SEC_CTRL_RSA_EN_MASK 0X03000000U
/* csudma */
@ -422,14 +416,14 @@ extern "C" {
/**
* Definition for SD to be included
*/
#if !defined(FSBL_SD_EXCLUDE) & defined( XPAR_XSDPS_0_DEVICE_ID)
#if (!defined(FSBL_SD_EXCLUDE) && defined( XPAR_XSDPS_0_DEVICE_ID))
#define XFSBL_SD
#endif
/**
* Definition for QSPI to be included
*/
#if !defined(FSBL_QSPI_EXCLUDE) & defined(XPAR_XQSPIPS_0_DEVICE_ID)
#if (!defined(FSBL_QSPI_EXCLUDE) && defined(XPAR_XQSPIPS_0_DEVICE_ID))
#define XFSBL_QSPI
#define XFSBL_QSPI_BASEADDRESS XPAR_XQSPIPS_0_BASEADDR
#endif
@ -437,7 +431,7 @@ extern "C" {
/**
* Definition for NAND to be included
*/
#if !defined(FSBL_NAND_EXCLUDE) & defined(XPAR_XNANDPS8_0_DEVICE_ID)
#if (!defined(FSBL_NAND_EXCLUDE) && defined(XPAR_XNANDPS8_0_DEVICE_ID))
#define XFSBL_NAND
#endif

4
lib/sw_apps/zynqmp_fsbl/src/xfsbl_initialization.c
View file

@ -672,8 +672,8 @@ static u32 XFsbl_ValidateHeader(XFsblPs * FsblInstancePtr)
/**
* Read Efuse bit and check Boot Header for Authentication
*/
EfuseCtrl = XFsbl_In32(EFUSE_RSA_CTRL);
if (((EfuseCtrl & EFUSE_RSA_CTRL_RSA_EN_MASK) != 0) ||
EfuseCtrl = XFsbl_In32(EFUSE_SEC_CTRL);
if (((EfuseCtrl & EFUSE_SEC_CTRL_RSA_EN_MASK) != 0) ||
((BootHdrAttrb & XIH_BH_IMAGE_ATTRB_RSA_MASK)
== XIH_BH_IMAGE_ATTRB_RSA_MASK))
{