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bsp: Added PSU definitions for TEST APP.

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This patch add PSU definitions for TEST APP in
xparameters_ps.h file for a53 (32,64 bit) and r5.

Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Reviewed-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
This commit is contained in:
P L Sai Krishna 2015-08-17 19:23:02 +05:30 • committed by Nava kishore Manne
parent 0cdc67eb82
commit 8eaf69e7fc
3 changed files with 105 additions and 0 deletions
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35
lib/bsp/standalone/src/cortexa53/32bit/xparameters_ps.h
View file

@ -283,6 +283,41 @@ extern "C" {
#define XPAR_PS7_SCUTIMER_0_INTR XPS_SCU_TMR_INT_ID
#define XPAR_PS7_XADC_0_INTR XPS_SYSMON_INT_ID
#define XPAR_PSU_UART_0_INTR XPS_UART0_INT_ID
#define XPAR_PSU_UART_1_INTR XPS_UART1_INT_ID
#define XPAR_PSU_USB_0_INTR XPS_USB0_INT_ID
#define XPAR_PSU_USB_1_INTR XPS_USB1_INT_ID
#define XPAR_PSU_I2C_0_INTR XPS_I2C0_INT_ID
#define XPAR_PSU_I2C_1_INTR XPS_I2C1_INT_ID
#define XPAR_PSU_SPI_0_INTR XPS_SPI0_INT_ID
#define XPAR_PSU_SPI_1_INTR XPS_SPI1_INT_ID
#define XPAR_PSU_CAN_0_INTR XPS_CAN0_INT_ID
#define XPAR_PSU_CAN_1_INTR XPS_CAN1_INT_ID
#define XPAR_PSU_GPIO_0_INTR XPS_GPIO_INT_ID
#define XPAR_PSU_ETHERNET_0_INTR XPS_GEM0_INT_ID
#define XPAR_PSU_ETHERNET_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
#define XPAR_PSU_ETHERNET_1_INTR XPS_GEM1_INT_ID
#define XPAR_PSU_ETHERNET_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
#define XPAR_PSU_ETHERNET_2_INTR XPS_GEM2_INT_ID
#define XPAR_PSU_ETHERNET_2_WAKE_INTR XPS_GEM2_WAKE_INT_ID
#define XPAR_PSU_ETHERNET_3_INTR XPS_GEM3_INT_ID
#define XPAR_PSU_ETHERNET_3_WAKE_INTR XPS_GEM3_WAKE_INT_ID
#define XPAR_PSU_QSPI_0_INTR XPS_QSPI_INT_ID
#define XPAR_PSU_WDT_0_INTR XPS_WDT_INT_ID
#define XPAR_PSU_SCUWDT_0_INTR XPS_SCU_WDT_INT_ID
#define XPAR_PSU_SCUTIMER_0_INTR XPS_SCU_TMR_INT_ID
#define XPAR_PSU_XADC_0_INTR XPS_SYSMON_INT_ID
#define XPAR_PSU_TTC_0_INTR XPS_TTC0_0_INT_ID
#define XPAR_PSU_TTC_1_INTR XPS_TTC0_1_INT_ID
#define XPAR_PSU_TTC_2_INTR XPS_TTC0_2_INT_ID
#define XPAR_PSU_TTC_3_INTR XPS_TTC1_0_INT_ID
#define XPAR_PSU_TTC_4_INTR XPS_TTC1_1_INT_ID
#define XPAR_PSU_TTC_5_INTR XPS_TTC1_2_INT_ID
#define XPAR_PSU_TTC_6_INTR XPS_TTC1_0_INT_ID
#define XPAR_PSU_TTC_7_INTR XPS_TTC1_1_INT_ID
#define XPAR_PSU_TTC_8_INTR XPS_TTC1_2_INT_ID
#define XPAR_PSU_TTC_9_INTR XPS_TTC1_0_INT_ID
#define XPAR_XADCPS_NUM_INSTANCES 1U
#define XPAR_XADCPS_0_DEVICE_ID 0U
#define XPAR_XADCPS_0_BASEADDR (0xF8007000U)

35
lib/bsp/standalone/src/cortexa53/64bit/xparameters_ps.h
View file

@ -283,6 +283,41 @@ extern "C" {
#define XPAR_PS7_SCUTIMER_0_INTR XPS_SCU_TMR_INT_ID
#define XPAR_PS7_XADC_0_INTR XPS_SYSMON_INT_ID
#define XPAR_PSU_UART_0_INTR XPS_UART0_INT_ID
#define XPAR_PSU_UART_1_INTR XPS_UART1_INT_ID
#define XPAR_PSU_USB_0_INTR XPS_USB0_INT_ID
#define XPAR_PSU_USB_1_INTR XPS_USB1_INT_ID
#define XPAR_PSU_I2C_0_INTR XPS_I2C0_INT_ID
#define XPAR_PSU_I2C_1_INTR XPS_I2C1_INT_ID
#define XPAR_PSU_SPI_0_INTR XPS_SPI0_INT_ID
#define XPAR_PSU_SPI_1_INTR XPS_SPI1_INT_ID
#define XPAR_PSU_CAN_0_INTR XPS_CAN0_INT_ID
#define XPAR_PSU_CAN_1_INTR XPS_CAN1_INT_ID
#define XPAR_PSU_GPIO_0_INTR XPS_GPIO_INT_ID
#define XPAR_PSU_ETHERNET_0_INTR XPS_GEM0_INT_ID
#define XPAR_PSU_ETHERNET_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
#define XPAR_PSU_ETHERNET_1_INTR XPS_GEM1_INT_ID
#define XPAR_PSU_ETHERNET_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
#define XPAR_PSU_ETHERNET_2_INTR XPS_GEM2_INT_ID
#define XPAR_PSU_ETHERNET_2_WAKE_INTR XPS_GEM2_WAKE_INT_ID
#define XPAR_PSU_ETHERNET_3_INTR XPS_GEM3_INT_ID
#define XPAR_PSU_ETHERNET_3_WAKE_INTR XPS_GEM3_WAKE_INT_ID
#define XPAR_PSU_QSPI_0_INTR XPS_QSPI_INT_ID
#define XPAR_PSU_WDT_0_INTR XPS_WDT_INT_ID
#define XPAR_PSU_SCUWDT_0_INTR XPS_SCU_WDT_INT_ID
#define XPAR_PSU_SCUTIMER_0_INTR XPS_SCU_TMR_INT_ID
#define XPAR_PSU_XADC_0_INTR XPS_SYSMON_INT_ID
#define XPAR_PSU_TTC_0_INTR XPS_TTC0_0_INT_ID
#define XPAR_PSU_TTC_1_INTR XPS_TTC0_1_INT_ID
#define XPAR_PSU_TTC_2_INTR XPS_TTC0_2_INT_ID
#define XPAR_PSU_TTC_3_INTR XPS_TTC1_0_INT_ID
#define XPAR_PSU_TTC_4_INTR XPS_TTC1_1_INT_ID
#define XPAR_PSU_TTC_5_INTR XPS_TTC1_2_INT_ID
#define XPAR_PSU_TTC_6_INTR XPS_TTC1_0_INT_ID
#define XPAR_PSU_TTC_7_INTR XPS_TTC1_1_INT_ID
#define XPAR_PSU_TTC_8_INTR XPS_TTC1_2_INT_ID
#define XPAR_PSU_TTC_9_INTR XPS_TTC1_0_INT_ID
#define XPAR_XADCPS_NUM_INSTANCES 1U
#define XPAR_XADCPS_0_DEVICE_ID 0U
#define XPAR_XADCPS_0_BASEADDR (0xF8007000U)

35
lib/bsp/standalone/src/cortexr5/xparameters_ps.h
View file

@ -281,6 +281,41 @@ extern "C" {
#define XPAR_PS7_SCUTIMER_0_INTR XPS_SCU_TMR_INT_ID
#define XPAR_PS7_XADC_0_INTR XPS_SYSMON_INT_ID
#define XPAR_PSU_UART_0_INTR XPS_UART0_INT_ID
#define XPAR_PSU_UART_1_INTR XPS_UART1_INT_ID
#define XPAR_PSU_USB_0_INTR XPS_USB0_INT_ID
#define XPAR_PSU_USB_1_INTR XPS_USB1_INT_ID
#define XPAR_PSU_I2C_0_INTR XPS_I2C0_INT_ID
#define XPAR_PSU_I2C_1_INTR XPS_I2C1_INT_ID
#define XPAR_PSU_SPI_0_INTR XPS_SPI0_INT_ID
#define XPAR_PSU_SPI_1_INTR XPS_SPI1_INT_ID
#define XPAR_PSU_CAN_0_INTR XPS_CAN0_INT_ID
#define XPAR_PSU_CAN_1_INTR XPS_CAN1_INT_ID
#define XPAR_PSU_GPIO_0_INTR XPS_GPIO_INT_ID
#define XPAR_PSU_ETHERNET_0_INTR XPS_GEM0_INT_ID
#define XPAR_PSU_ETHERNET_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
#define XPAR_PSU_ETHERNET_1_INTR XPS_GEM1_INT_ID
#define XPAR_PSU_ETHERNET_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
#define XPAR_PSU_ETHERNET_2_INTR XPS_GEM2_INT_ID
#define XPAR_PSU_ETHERNET_2_WAKE_INTR XPS_GEM2_WAKE_INT_ID
#define XPAR_PSU_ETHERNET_3_INTR XPS_GEM3_INT_ID
#define XPAR_PSU_ETHERNET_3_WAKE_INTR XPS_GEM3_WAKE_INT_ID
#define XPAR_PSU_QSPI_0_INTR XPS_QSPI_INT_ID
#define XPAR_PSU_WDT_0_INTR XPS_WDT_INT_ID
#define XPAR_PSU_SCUWDT_0_INTR XPS_SCU_WDT_INT_ID
#define XPAR_PSU_SCUTIMER_0_INTR XPS_SCU_TMR_INT_ID
#define XPAR_PSU_XADC_0_INTR XPS_SYSMON_INT_ID
#define XPAR_PSU_TTC_0_INTR XPS_TTC0_0_INT_ID
#define XPAR_PSU_TTC_1_INTR XPS_TTC0_1_INT_ID
#define XPAR_PSU_TTC_2_INTR XPS_TTC0_2_INT_ID
#define XPAR_PSU_TTC_3_INTR XPS_TTC1_0_INT_ID
#define XPAR_PSU_TTC_4_INTR XPS_TTC1_1_INT_ID
#define XPAR_PSU_TTC_5_INTR XPS_TTC1_2_INT_ID
#define XPAR_PSU_TTC_6_INTR XPS_TTC1_0_INT_ID
#define XPAR_PSU_TTC_7_INTR XPS_TTC1_1_INT_ID
#define XPAR_PSU_TTC_8_INTR XPS_TTC1_2_INT_ID
#define XPAR_PSU_TTC_9_INTR XPS_TTC1_0_INT_ID
#define XPAR_XADCPS_NUM_INSTANCES 1U
#define XPAR_XADCPS_0_DEVICE_ID 0U
#define XPAR_XADCPS_0_BASEADDR (0xF8007000U)