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emacps: Disable extended mode and correct 64 bit support

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The existing changes done under EXTENDED_DESC_MODE should in fact
be done for arch 64. Extended mode needs additional BD words and since
there is no test for it at present, it is disabled.

Signed-off-by: Harini Katakam <harinik@xilinx.com>
This commit is contained in:
Harini Katakam 2015-03-14 12:26:58 +05:30 • committed by Nava kishore Manne
parent 7aec13f790
commit 93f1486370
3 changed files with 10 additions and 12 deletions
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10
XilinxProcessorIPLib/drivers/emacps/src/xemacps.c
View file

@ -48,6 +48,8 @@
* 64-bit changes.
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.0 hk 02/20/15 Added support for jumbo frames. Increase AHB burst.
* Disable extended mode. Perform all 64 bit changes under
* check for arch64.
*
* </pre>
******************************************************************************/
@ -354,12 +356,6 @@ void XEmacPs_Reset(XEmacPs *InstancePtr)
#endif
(u32)XEMACPS_DMACR_INCR16_AHB_BURST));
}
#if EXTENDED_DESC_MODE
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET,
(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET) |
XEMACPS_DMACR_TXEXTEND_MASK |
XEMACPS_DMACR_RXEXTEND_MASK));
#endif
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_TXSR_OFFSET, 0x0U);
@ -472,7 +468,7 @@ void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum,
XEMACPS_TXQ1BASE_OFFSET,
(QPtr & ULONG64_LO_MASK));
}
#if EXTENDED_DESC_MODE
#ifdef __aarch64__
/* Set the MSB of Queue start address */
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_MSBBUF_QBASE_OFFSET,

2
XilinxProcessorIPLib/drivers/emacps/src/xemacps.h
View file

@ -306,6 +306,8 @@
* test app tcl(CR:827686).
* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.0 hk 02/20/15 Added support for jumbo frames. Increase AHB burst.
* Disable extended mode. Perform all 64 bit changes under
* check for arch64.
* </pre>
*
****************************************************************************/

10
XilinxProcessorIPLib/drivers/emacps/src/xemacps_bd.h
View file

@ -65,6 +65,8 @@
* changes.
* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.0 hk 02/20/15 Added support for jumbo frames.
* Disable extended mode. Perform all 64 bit changes under
* check for arch64.
*
* </pre>
*
@ -88,11 +90,9 @@ extern "C" {
/**************************** Type Definitions *******************************/
#ifdef __aarch64__
#define EXTENDED_DESC_MODE 1
/* Minimum BD alignment */
#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 64U
#else
#define EXTENDED_DESC_MODE 0
/* Minimum BD alignment */
#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 4U
#endif
@ -172,7 +172,7 @@ typedef UINTPTR XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
* void XEmacPs_BdSetAddressTx(XEmacPs_Bd* BdPtr, UINTPTR Addr)
*
*****************************************************************************/
#if EXTENDED_DESC_MODE
#ifdef __aarch64__
#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
(u32)((Addr) & ULONG64_LO_MASK)); \
@ -197,7 +197,7 @@ typedef UINTPTR XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
* void XEmacPs_BdSetAddressRx(XEmacPs_Bd* BdPtr, UINTPTR Addr)
*
*****************************************************************************/
#if EXTENDED_DESC_MODE
#ifdef __aarch64__
#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
@ -258,7 +258,7 @@ typedef UINTPTR XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
* UINTPTR XEmacPs_BdGetBufAddr(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#if EXTENDED_DESC_MODE
#ifdef __aarch64__
#define XEmacPs_BdGetBufAddr(BdPtr) \
(XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \
(XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET)) << 32U)