stv0g/embeddedsw
1
0
Fork 0
Code Issues Pull requests Releases Wiki Activity

nandps8_v2_0: Driver for nand controller in Zynq Ultrascale Mp.

Browse source 
Added driver to supports Arasan NAND controller present in
Zynq Ultrascale Mp.

Signed-off-by: Shakti Bhatnagar <shaktib@xilinx.com>
This commit is contained in:
Shakti Bhatnagar 2014-12-09 19:56:14 +05:30 • committed by Suneel Garapati
parent cfd100fc83
commit 9a04f2c373
26 changed files with 11008 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

54
XilinxProcessorIPLib/drivers/nandps8_v2_0/data/nandps8.mdd Executable file
View file

@ -0,0 +1,54 @@
###############################################################################
#
# Copyright (C) 2014 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information of Xilinx, Inc.
# and is protected under U.S. and international copyright and other
# intellectual property laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any rights to the
# materials distributed herewith. Except as otherwise provided in a valid
# license issued to you by Xilinx, and to the maximum extent permitted by
# applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
# FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
# IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
# MERCHANTABILITY, NON- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
# and
# (2) Xilinx shall not be liable (whether in contract or tort, including
# negligence, or under any other theory of liability) for any loss or damage
# of any kind or nature related to, arising under or in connection with these
# materials, including for any direct, or any indirect, special, incidental,
# or consequential loss or damage (including loss of data, profits,
# goodwill, or any type of loss or damage suffered as a result of any
# action brought by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the possibility
# of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail- safe, or for use
# in any application requiring fail-safe performance, such as life-support
# or safety devices or systems, Class III medical devices, nuclear
# facilities, applications related to the deployment of airbags, or any
# other applications that could lead to death, personal injury, or severe
# property or environmental damage (individually and collectively,
# "Critical Applications"). Customer assumes the sole risk and liability
# of any use of Xilinx products in Critical Applications, subject only to
# applicable laws and regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART
# OF THIS FILE AT ALL TIMES.
#
###############################################################################
OPTION psf_version = 2.1;
BEGIN driver nandps8
OPTION supported_peripherals = (ps8_nand pss_nand);
OPTION driver_state = ACTIVE;
OPTION copyfiles = all;
OPTION VERSION = 2.0;
OPTION NAME = nandps8;
END driver

62
XilinxProcessorIPLib/drivers/nandps8_v2_0/data/nandps8.tcl Executable file
View file

@ -0,0 +1,62 @@
###############################################################################
#
# Copyright (C) 2014 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information of Xilinx, Inc.
# and is protected under U.S. and international copyright and other
# intellectual property laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any rights to the
# materials distributed herewith. Except as otherwise provided in a valid
# license issued to you by Xilinx, and to the maximum extent permitted by
# applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
# FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
# IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
# MERCHANTABILITY, NON- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
# and
# (2) Xilinx shall not be liable (whether in contract or tort, including
# negligence, or under any other theory of liability) for any loss or damage
# of any kind or nature related to, arising under or in connection with these
# materials, including for any direct, or any indirect, special, incidental,
# or consequential loss or damage (including loss of data, profits,
# goodwill, or any type of loss or damage suffered as a result of any
# action brought by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the possibility
# of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail- safe, or for use
# in any application requiring fail-safe performance, such as life-support
# or safety devices or systems, Class III medical devices, nuclear
# facilities, applications related to the deployment of airbags, or any
# other applications that could lead to death, personal injury, or severe
# property or environmental damage (individually and collectively,
# "Critical Applications"). Customer assumes the sole risk and liability
# of any use of Xilinx products in Critical Applications, subject only to
# applicable laws and regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART
# OF THIS FILE AT ALL TIMES.
#
###############################################################################
##############################################################################
#
# Modification History
#
# Ver Who Date Changes
# ----- ---- -------- -----------------------------------------------
# 1.00a nm 05/06/14 Created
#
##############################################################################
#uses "xillib.tcl"
proc generate {drv_handle} {
xdefine_zynq_include_file $drv_handle "xparameters.h" "XNandPs8" "NUM_INSTANCES" "DEVICE_ID" "C_S_AXI_BASEADDR" "C_S_AXI_HIGHADDR"
xdefine_zynq_config_file $drv_handle "xnandps_g.c" "XNandPs8" "DEVICE_ID" "C_S_AXI_BASEADDR"
xdefine_zynq_canonical_xpars $drv_handle "xparameters.h" "XNandPs8" "DEVICE_ID" "C_S_AXI_BASEADDR" "C_S_AXI_HIGHADDR"
}

91
XilinxProcessorIPLib/drivers/nandps8_v2_0/examples/Makefile Executable file
View file

@ -0,0 +1,91 @@
#/******************************************************************************
#*
#* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
#*
#* This file contains confidential and proprietary information of Xilinx, Inc.
#* and is protected under U.S. and international copyright and other
#* intellectual property laws.
#*
#* DISCLAIMER
#* This disclaimer is not a license and does not grant any rights to the
#* materials distributed herewith. Except as otherwise provided in a valid
#* license issued to you by Xilinx, and to the maximum extent permitted by
#* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
#* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
#* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
#* MERCHANTABILITY, NON- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
#* and
#* (2) Xilinx shall not be liable (whether in contract or tort, including
#* negligence, or under any other theory of liability) for any loss or damage
#* of any kind or nature related to, arising under or in connection with these
#* materials, including for any direct, or any indirect, special, incidental,
#* or consequential loss or damage (including loss of data, profits,
#* goodwill, or any type of loss or damage suffered as a result of any
#* action brought by a third party) even if such damage or loss was
#* reasonably foreseeable or Xilinx had been advised of the possibility
#* of the same.
#*
#* CRITICAL APPLICATIONS
#* Xilinx products are not designed or intended to be fail- safe, or for use
#* in any application requiring fail-safe performance, such as life-support
#* or safety devices or systems, Class III medical devices, nuclear
#* facilities, applications related to the deployment of airbags, or any
#* other applications that could lead to death, personal injury, or severe
#* property or environmental damage (individually and collectively,
#* "Critical Applications"). Customer assumes the sole risk and liability
#* of any use of Xilinx products in Critical Applications, subject only to
#* applicable laws and regulations governing limitations on product liability.
#*
#* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART
#* OF THIS FILE AT ALL TIMES.
#*
#******************************************************************************/
c_SOURCES := $(wildcard *.c)
INCLUDES := $(wildcard *.h)
EXECS := xnandps8_example.elf
OBJS := $(patsubst %.c, %.o, $(c_SOURCES))
ifeq '$(PROC)' 'r5'
BSP_DIR := ../../../../build/target/cortex-r5
LSCRIPT_DIR := ../../../../build/scripts/bsp_utils
CC := ${CROSS_COMPILE}gcc
AS := ${CROSS_COMPILE}gcc
LINKER := ${CROSS_COMPILE}gcc
AR := ${CROSS_COMPILE}ar
LIBPATH := $(BSP_DIR)/ps8_cortexr5_0/lib
DUMP := ${CROSS_COMPILE}objdump -xSD
INCLUDEPATH := -I$(BSP_DIR)/ps8_cortexr5_0/include -I. -I./include/
CFLAGS = -Wall -O0 -g3 -fmessage-length=0 \
-mcpu=cortex-r5 -mfloat-abi=softfp
LDFLAGS := -Wl,--start-group,-lxil,-lxilffs,-lgcc,-lc,--end-group -L$(LIBPATH) -L./
LSCRIPT := -T$(LSCRIPT_DIR)/LinkScr.ld
endif
ifeq '$(PROC)' 'a53'
BSP_DIR := ../../../../build/target/cortex-a53
LSCRIPT_DIR := ../../../../build/scripts/bsp_utils
CC := ${CROSS_COMPILE}gcc
AS := ${CROSS_COMPILE}gcc
LINKER := ${CROSS_COMPILE}gcc
AR := ${CROSS_COMPILE}gcc
DUMP := ${CROSS_COMPILE}objdump -xSD
INCLUDEPATH := -I$(BSP_DIR)/ps8_cortexa53_0/include -I. -I./include/
LIBPATH := $(BSP_DIR)/ps8_cortexa53_0/lib
CFLAGS = -Wall -O0 -g3 -fmessage-length=0 \
-march=armv8-a
LSCRIPT := -T$(LSCRIPT_DIR)/DDRA53_LinkScr.ld
LDFLAGS := -Wl,--start-group,-lxil,-lxilffs,-lgcc,-lc,--end-group -L$(LIBPATH) -L./
endif
all: $(EXECS)
%.elf: %.o $(INCLUDES)
$(LINKER) $< $(CC_FLAGS) $(LDFLAGS) $(LSCRIPT) -o $@
$(DUMP) $@ > dump
%.o:%.c
$(CC) $(CC_FLAGS) $(CFLAGS) $(ECFLAGS) -c $< -o $@ $(INCLUDEPATH)
clean:
rm -rf $(OBJS) *.elf dump

238
XilinxProcessorIPLib/drivers/nandps8_v2_0/examples/xnandps8_example.c Executable file
View file

@ -0,0 +1,238 @@
/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and
* (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits,
* goodwill, or any type of loss or damage suffered as a result of any
* action brought by a third party) even if such damage or loss was
* reasonably foreseeable or Xilinx had been advised of the possibility
* of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail- safe, or for use
* in any application requiring fail-safe performance, such as life-support
* or safety devices or systems, Class III medical devices, nuclear
* facilities, applications related to the deployment of airbags, or any
* other applications that could lead to death, personal injury, or severe
* property or environmental damage (individually and collectively,
* "Critical Applications"). Customer assumes the sole risk and liability
* of any use of Xilinx products in Critical Applications, subject only to
* applicable laws and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART
* OF THIS FILE AT ALL TIMES.
*
******************************************************************************/
/******************************************************************************
*
* @file xnandps8_example.c
*
* This file contains a design example using the NAND driver (XNandPs8).
* This example tests the erase, read and write features of the controller.
* The flash is erased and written. The data is read back and compared
* with the data written for correctness.
*
* @note
*
* None.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- ---------- -----------------------------------------------
* 1.0 nm 05/06/2014 First release.
*</pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include <stdio.h>
#include <stdlib.h>
#include <xil_types.h>
#include <xil_printf.h>
#include <xparameters.h>
#include "xnandps8.h"
/************************** Constant Definitions *****************************/
/*
* The following constants map to the XPAR parameters created in the
* xparameters.h file. They are defined here such that a user can easily
* change all the needed parameters in one place.
*/
#define NAND_DEVICE_ID 0U
#define TEST_BUF_SIZE 0x8000U
#define TEST_PAGE_START 0x2U
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
s32 NandReadWriteExample(u16 NandDeviceId);
/************************** Variable Definitions *****************************/
XNandPs8 NandInstance; /* XNand Instance */
XNandPs8 *NandInstPtr = &NandInstance;
/*
* Buffers used during read and write transactions.
*/
u8 ReadBuffer[TEST_BUF_SIZE] __attribute__ ((aligned(64))); /**< Block sized Read buffer */
u8 WriteBuffer[TEST_BUF_SIZE] __attribute__ ((aligned(64))); /**< Block sized write buffer */
/************************** Function Definitions ******************************/
/****************************************************************************/
/**
*
* Main function to execute the Nand Flash read write example.
*
* @param None.
*
* @return
* - XST_SUCCESS if the example has completed successfully.
* - XST_FAILURE if the example has failed.
*
* @note None.
*
*****************************************************************************/
s32 main(void)
{
s32 Status = XST_FAILURE;
xil_printf("Nand Flash Read Write Example Test\r\n");
/*
* Run the NAND read write example, specify the Base Address that
* is generated in xparameters.h .
*/
Status = NandReadWriteExample(NAND_DEVICE_ID);
if (Status != XST_SUCCESS) {
xil_printf("Nand Flash Read Write Example Test Failed\r\n");
goto Out;
}
Status = XST_SUCCESS;
xil_printf("Successfully ran Nand Flash Read Write Example Test\r\n");
Out:
return Status;
}
/****************************************************************************/
/**
*
* This function runs a test on the NAND flash device using the basic driver
* functions in polled mode.
* The function does the following tasks:
* - Initialize the driver.
* - Erase the flash.
* - Write data to the flash.
* - Read back the data from the flash.
* - Compare the data read against the data Written.
*
* @param NandDeviceId is is the XPAR_<NAND_instance>_DEVICE_ID value
* from xparameters.h.
*
* @return
* - XST_SUCCESS if successful.
* - XST_FAILURE if failed.
*
* @note
* None
*
****************************************************************************/
s32 NandReadWriteExample(u16 NandDeviceId)
{
s32 Status = XST_FAILURE;
XNandPs8_Config *Config;
u32 Index;
u64 Offset;
u32 Length;
Config = XNandPs8_LookupConfig(NandDeviceId);
if (Config == NULL) {
Status = XST_FAILURE;
goto Out;
}
/*
* Initialize the flash driver.
*/
Status = XNandPs8_CfgInitialize(NandInstPtr, Config,
Config->BaseAddress);
if (Status != XST_SUCCESS) {
goto Out;
}
XNandPs8_EnableDmaMode(NandInstPtr);
Offset = (u64)(TEST_PAGE_START * NandInstPtr->Geometry.BytesPerPage);
Length = TEST_BUF_SIZE;
/*
* Initialize the write buffer
*/
for (Index = 0; Index < Length;Index++) {
WriteBuffer[Index] = (u8) (rand() % 256);
}
/*
* Erase the flash
*/
Status = XNandPs8_Erase(NandInstPtr, (u64)Offset, (u64)Length);
if (Status != XST_SUCCESS) {
goto Out;
}
/*
* Write to flash
*/
Status = XNandPs8_Write(NandInstPtr, (u64)Offset, (u64)Length,
&WriteBuffer[0]);
if (Status != XST_SUCCESS) {
goto Out;
}
/*
* Read the flash after writing
*/
Status = XNandPs8_Read(NandInstPtr, (u64)Offset, (u64)Length,
&ReadBuffer[0]);
if (Status != XST_SUCCESS) {
goto Out;
}
/*
* Compare the results
*/
for (Index = 0U; Index < Length;Index++) {
if (ReadBuffer[Index] != WriteBuffer[Index]) {
xil_printf("Index 0x%x: Read 0x%x != Write 0x%x\n",
Index,
ReadBuffer[Index],
WriteBuffer[Index]);
Status = XST_FAILURE;
goto Out;
}
}
Status = XST_SUCCESS;
Out:
return Status;
}

14
XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/README.txt Executable file
View file

@ -0,0 +1,14 @@
NandPs8 Integration test
- On A53 processors use the linker script for DDR region to run the integration test
With OCM linker script which is the default linker script, the integration test may hang.
In order to run on OCM, you can use Xil_DCacheDisable() in the main and run the integration test.
- On R5 processors, you may get compilation error for bsp stating "undefined reference to `end'"
Add end = .; at the end of the linker script to remove this error
} > ps8_ocm_ram_0_S_AXI_BASEADDR
_end = .;
end = .;
}

586
XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/ct.h Executable file
View file

@ -0,0 +1,586 @@
/******************************************************************************
*
* (c) Copyright 2010-14 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file ct.h
*
* Code test (CT) utility driver.
*
* This package is intended to help designers test their Xilinx device drivers
* in unit and integration testing environments. The macros and functions
* provide the following services:
*
* - Automated data comparison
* - Xilinx driver assert testing
* - Interrupt utilities
* - Error & message logging
* - Test sequencing utilities
* - Timing utilities
*
* The main benefit of this package is to simplify test code and make it easier
* for the tester to get more coverage in their integration and unit testing
* without having to replicate common testing constructs.
*
* <b>Integrating CT Source code</b>
*
* This package consists of this header file and an implementation file. The
* implementation can be operating system specific. When including this package
* in your test, use this file and one of the CT implementation files such as
* ct_vxworks.c.
*
* There are GNU specific "C" extensions used in this package and as a result
* make it non-ANSI compliment. The tester must compile this package and their
* other test code with the GNU compiler suite.
*
* The CT package requires that there be available standard header files
* stdio.h, string.h, and stdarg.h.
*
*
* <b>Setup and Test Sequencing</b>
*
* Before calling any comparison or utility function in this package, the tester
* should call CT_Init() to initialize the library. This function only needs to
* be called once.
*
* During tests, your code may be segmented into sub tests where you would want
* separate out the results. At the end of all sub tests, you may want to
summarize
* all the tests run. The following pseudo code shows how this is done with CT
* sequencing function calls:
*
* <pre>
*
* CT_Init();
*
* // Subtest #1
* CT_TestReset("This is my Subtest #1");
* ...
* // Subtest code
* ...
* Failures = CT_GetTestFailures();
* CT_Message("Subtest #1 had %d failures\r\n", Failures);
*
* // Subtest #2
* CT_TestReset("This is my Subtest #2");
* ...
* // Subtest code
* ...
* Failures = CT_GetTestFailures();
* CT_Message("Subtest #2 had %d failures\r\n", Failures);
*
* Failures = CT_GetTotalFailures();
* CT_Message("Total test failures = %d\r\n", Failures);
*
* </pre>
*
* <b>General Usage</b>
*
* The heart of this package utilizes macros to compare variables or memory
* areas. For example,
*
* <pre>
*
* CT_CMP_NUM(int, ActualValue, ExpectedValue);
*
* </pre>
*
* compares two values of type int. If they are not equal, then an error message
* is logged and an internal counter is incremented. If they are equal, then the
* test proceeds as if nothing had occurred. Other examples:
*
* <pre>
*
* CT_CMP_NUM(int, *ActualPtr, 5);
* CT_CMP_NUM(int*, ActualPtr, 0x20002100);
*
* </pre>
*
* With each failure, a descriptive message is printed along with the line number
* of the invoking code.
*
* If the tester needs to make a comparison manually, then they can use the
* CT_LOG_FAILURE() macro to note the error in case the comparison is negative.
* If the tester needs to emit an informational message, then they can use the
* CT_Mesage() function. Calling this function does not increment error counters.
*
*
* <b>Message Logging</b>
*
* This package uses the printf() library for message logging.
*
* Ideally, the tester's environment should include some sort of UART. By
* default CT utilizes a pre-configured console UART.
*
* If your system does not contain a UART, then another method of providing
* results includes printf'ing messages to memory. To enable this method,
* enable the definition of IO_USE_BUFFER in this file. To further tailor this
* method of logging, change IO_BUF_SIZE and IO_BUF_CUSHION. All output will
* be written to the TextBuf array. Use your debugger or your own test
* utilities to examine this buffer for generated output.
*
*
* <b>Limitations</b>
*
* - This package must be compiled under the GNU compiler suite.
* - CT_CMP macros can compare only ordinal data types. Structure type
* comparisons require the tester to implement their own function.
* - Some sort of BSP is required to support implementation of string.h,
* stdio.h, and stdarg.h at a minimum.
* - Advanced BSP support of signal.h is required to use CT_SetAlarm().
* If support is not available, then this function will return an error.
* - Testing asserts requires that NDEBUG not be defined in your driver under
* test code.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* --- ---- -------- -----------------------------------------------
* 1 rmm 12/23/03 First release for VxWorks
*
* </pre>
*
******************************************************************************/
#ifndef CT_H
#define CT_H
/***************************** Include Files *********************************/
#include "xil_types.h" /* Needed for assert testing */
#include "xil_assert.h"
#include <stdio.h>
#include <string.h>
#include <stdarg.h>
#include "intg.h"
/************************** Constant Definitions *****************************/
/**
* This is what the CT_Log* lines will be prefixed with. The numerical arg
* should be the line number within the source file containing the call to
* the CT library function or macro.
*/
#define CT_ERR_FMT " FAIL: %s: %04d:"
/**************************** Type Definitions *******************************/
typedef unsigned long long CT_TIME_STAMP; /**< Type defination for Time Stamp.*/
/***************** Macros (Inline Functions) Definitions *********************/
/*****************************************************************************/
/**
*
* Log a failure with a supplied message. This provides a useful wrapper
* around the CT_LogFailure function that prints messages of the same format
* as other CT macros:
*
* <pre>
* 1 int i;
* 2
* 3 i = 10;
* 4 if (i != 5)
* 5 {
* 6 CT_LOG_FAILURE("GetDataFromDevice() returned %d instead of 5", i);
* 7 CT_LOG_FAILURE("D'oh");
* 8 }
* </pre>
*
* yields the output:
*
* FAIL: 0006: GetDataFromDevice() returned 10 instead of 5
* FAIL: 0007: D'oh
*
* @param fmt is a printf style format string
* @param args is a variable argument list that matches fields in the fmt
* string.
*
* @note
* Usage: CT_LOG_FAILURE(char* fmt, ...)
*****************************************************************************/
#define CT_LOG_FAILURE(fmt, args...) \
CT_LogFailure(CT_ERR_FMT fmt "\r\n", __FILE__, __LINE__ , ## args)
/* Note: In the preceding construct, the space between __FILE__, __LINE__ and
* the comma are needed for the ## args to work when there is no "args"
* expansion like in line 7 of the example shown above.
*/
/*****************************************************************************/
/**
*
* Test asserts for a function. This macro will verify whether the called
* function generates an assert from the provided arguments. If it does not
* then a failure message is logged.
*
* The design of this macro allows the tester to verify an assert occurs
* with a single line of code with full type checking of the called
* function. For example, if your function under test is coded as:
*
* <pre>
* void XDev_Start(Dev* Instance)
* {
* Xil_AssertVoid(Dev != NULL);
* ...
* }
* </pre>
*
* Then use CT_ASSERT in the following way to verify that the assert is caught.
*
* <pre>
* CT_ASSERT(XDev_Start, (Dev*)NULL);
* </pre>
*
* @param Function is the function being tested for asserts.
* @param args is a variable number of arguments. It contains whatever arguments
* should cause an assert. These arguments are arranged by the
* preprocessor in the order provided by the tester.
*
* @note
* Usage: CT_ASSERT(SomeFunc, arg1, arg2, ...)
*****************************************************************************/
#define CT_ASSERT(Function, args...) \
{ \
if (CT_IsAssertDisabled()) \
CT_LogFailure(CT_ERR_FMT "NDEBUG is defined, assert test failed\r\n", \
__FILE__, __LINE__); \
else \
{ \
XAssertStatus = XASSERT_NONE; \
XWaitInAssert = FALSE; \
(void)Function(args); \
XWaitInAssert = TRUE; \
if (XAssertStatus == XASSERT_NONE) \
CT_LogFailure(CT_ERR_FMT "Assert failed\r\n", __FILE__, __LINE__); \
} \
}
/*****************************************************************************/
/**
*
* Compare numbers. If not equal, then output message and increment fail
* counter. The message contains the line number of the failure, the
* name of the variable, and its actual and expected values in hex and
* decimal. An example:
*
* <pre>
* 1 UINT32 result = 5;
* 2 UINT32 expected = 17;
* 3
* 4 CT_CMP_NUM(UINT32, result, expected)
*
* yields the output:
*
* FAIL: 0004: result=5(5h), expected 17(11h)
*
* </pre>
*
* @param type is data type to compare (must be an ordinal type such as int)
* @param actual is the actual data retrieved from test
* @param expected is the expected value
*
* @note
* Usage: CT_CMP_NUM(<type>, actual, expected)
****************************************************************************/
#define CT_CMP_NUM(type, actual, expected) \
if ((type)(actual) != (type)(expected)) \
{ \
printf(CT_ERR_FMT "%s=%d(%Xh), expected %d(%Xh)\r\n", \
__FILE__, __LINE__, #actual, (int)actual, (int)actual, \
(int)expected, (int)expected); \
CT_LogFailure2(); \
}
/*****************************************************************************/
/**
*
* Like CT_CMP_NUM except an extra argument is printed. Helpful if comparing
* numbers in a loop where the loop index may prove useful if the test fails.
*
* <pre>
* 1 UINT32 result[5];
* 2 UINT32 expected[5];
* 3 int i;
* 4
* 5 for (i=0; i<5; i++)
* 6 {
* 7 CT_CMP_NUM_ARG(UINT32, result[i], expected[i], i);
* 8 }
* 9
*
* yeilds the output if for example failure occurs at i=3:
*
* FAIL: 0007: result=5(5h), expected 17(11h). i=3
* </pre>
*
* @param type is data type to compare (must be an ordinal type such as int)
* @param actual is the actual data retrieved from test
* @param expected is the expected value
* @param arg is an argument that can be treated as an integer.
*
* @note
* Usage: CT_CMP_NUM_ARG(<type>, actual, expected, arg1)
****************************************************************************/
#define CT_CMP_NUM_ARG(type, actual, expected, arg) \
if ((type)(actual) != (type)(expected)) \
{ \
CT_LogFailure(CT_ERR_FMT "%s=%d(%Xh), expected %d(%Xh). %s=%d\r\n", \
__FILE__, __LINE__, #actual, (int)actual, (int)actual, \
(int)expected, (int)expected, #arg, arg); \
}
/*****************************************************************************/
/**
*
* Like CT_CMP_NUM_ARG except a second extra argument is printed. Helpful if
* comparing numbers in a loop where the loop index may prove useful if the test
* fails.
*
* <pre>
* 1 UINT32 result[5];
* 2 UINT32 expected[5];
* 3 int i, j=(int)&result[0];
* 4
* 5 for (i=0; i<5; i++, j++)
* 6 {
* 7 CT_CMP_NUM_ARG2(UINT32, result[i], expected[i], i, j);
* 8 }
* 9
*
* yeilds the output if for example failure occurs at i=3:
*
* FAIL: 0007: result=5(5h), expected 17(11h). i=3, j=543234
* </pre>
*
* @param type is data type to compare (must be an ordinal type such as int)
* @param actual is the actual data retrieved from test
* @param expected is the expected value
* @param arg1 is an argument that can be treated as an integer.
* @param arg2 is an argument that can be treated as an integer.
*
* @note
* Usage: CT_CMP_NUM_ARG2(<type>, actual, expected, arg1, arg2)
****************************************************************************/
#define CT_CMP_NUM_ARG2(type, actual, expected, arg1, arg2) \
if ((type)(actual) != (type)(expected)) \
{ \
CT_LogFailure(CT_ERR_FMT "%s=%d(%Xh), expected %d(%Xh). %s=%d. \
%s=%d\r\n",\
__FILE__, __LINE__, #actual, (int)actual, (int)actual,\
(int)expected, (int)expected, #arg1, arg1, #arg2, arg2);\
}
/*****************************************************************************/
/**
*
* Like CT_CMP_NUM except a range of memory is compared.
*
* @param type is data type to compare (must be an ordinal type such as int)
* @param actual is the actual data retrieved from test and must be an array
* of type
* @param bytes is the number of bytes to test
* @param expected is the expected value and must be of type.
*
* @note
* Usage: CT_CMP_NUM_RANGE(<type>, <type> actual[], bytes, expected)
****************************************************************************/
#define CT_CMP_NUM_RANGE(type, actual, bytes, expected) \
{ \
int d112a; \
int words = (bytes)/sizeof(type); \
type *a = (type*)(actual); \
\
for (d112a=0; d112a<words; d112a++) \
{ \
if (a[d112a] != expected) \
{ \
CT_LogFailure(CT_ERR_FMT "%s[%d]=%d(%Xh), expected %d(%Xh)\r\n", \
__FILE__, __LINE__, #actual, d112a, a[d112a], \
a[d112a], \
expected, expected); \
break; \
} \
} \
}
/*****************************************************************************/
/**
*
* Macro that compare two ranges of memory. If the areas are not equal, then
* a message is output and the CT_NumFailures counter is incremented. Comparison
* stops at the first failure.
*
* The failure message contains the line number of the failure, the
* name of the variable, and its actual and expected values in hex and
* decimal. An example:
*
* <pre>
* 1 UINT32 result[500];
* 2 UINT32 expected[500];
* 3
* 4 CT_CMP_MEM(UINT32, result, expected, 500)
*
* yeilds the output if result[13]=100 and expected[13]=121:
*
* FAIL: 0004: result[13]=100(64h), expected 121(79h)
* </pre>
*
* @param type is data type to compare (must be an ordinal type such as int)
* @param actual is the area of memory to test
* @param expected is the expected contents
* @param words is the number of data type "type" to test.
*
* @note
* Usage: CT_CMP_MEM(<type>, <type> *actual, <type> *expected, unsigned words)
****************************************************************************/
#define CT_CMP_MEM(type, actual, expected, words) \
{ \
int d112a; \
type *a = (type*)(actual); \
type *e = (type*)(expected); \
\
for (d112a=0; d112a<words; d112a++) \
{ \
if (a[d112a] != e[d112a]) \
{ \
CT_LogFailure(CT_ERR_FMT "%s[%d]=%d(%Xh), expected %d(%Xh)\r\n", \
__FILE__, __LINE__, #actual, d112a, a[d112a], \
a[d112a], \
e[d112a], e[d112a]); \
break; \
} \
} \
}
/*****************************************************************************/
/**
*
* Like CT_CMP_MEM except an extra argument is printed. Helpful if comparing
* in a loop where the loop index may prove useful if the test fails.
*
* <pre>
* 1 UINT32 result[TEST_WORDS];
* 2 UINT32 expected[TEST_WORDS];
* 3 int i;
* 4
* 5 for (i=0; i<3; i++)
* 6 {
* 7 CT_CMP_MEM_ARG(UINT32, result, expected, TEST_WORDS, i);
* 8 taskDelay(10);
* 8 }
* 9
*
* yeilds the output if for example failure occurs at i=1, and result[2]=1,
* and expected[2]=3:
*
* FAIL: 0007: result[2]=1(1h), expected 3(3h)
* </pre>
*
* @param type is data type to compare (must be an ordinal type such as int)
* @param actual is the area of memory to test
* @param expected is the expected contents
* @param words is the number of data type "type" to test.
* @param index is an argument that can be treated as an integer.
*
* @note
* Usage: CT_CM_MEM_ARG(<type>, <type> actual[], <type> expected[], index)
****************************************************************************/
#define CT_CMP_MEM_ARG(type, actual, expected, words, index) \
{ \
int d112a; \
type *a = (type*)(actual); \
type *e = (type*)(expected); \
\
for (d112a=0; d112a<words; d112a++) \
{ \
if (a[d112a] != e[d112a]) \
{ \
CT_LogFailure(CT_ERR_FMT "%s[%d]=%d(%Xh), expected %d(%Xh). \
%s=%d\r\n",\
__FILE__, __LINE__, #actual, d112a, a[d112a],\
a[d112a], e[d112a], \
e[d112a], #index, index); \
break; \
} \
} \
}
/*****************************************************************************/
/**
*
* Duplicate the data type. Can be used on any declared type.
*
* @param type is data type to copy
* @param dest is destination data pointer
* @param src is source data pointer
*
* @note
* Usage: CT_COPY_STRUCT(<type>, <type> *dest, <type> *src)
****************************************************************************/
#define CT_COPY_STRUCT(type,dest,src) \
{ \
type *td = dest; \
type *ts = src; \
memcpy(td,ts,sizeof(type)); \
}
/************************** Function Prototypes ******************************/
void CT_Init(void);
void CT_TestReset(char *fmt, ...);
void CT_NotifyNextPass(void);
void CT_LogFailure(char* fmt, ...);
void CT_LogFailure2();
unsigned CT_GetTestFailures(void);
unsigned CT_GetTotalFailures(void);
void CT_Message(char *fmt, ...);
void CT_MemSet(void *Address, char Value, unsigned Bytes);
int CT_IsAssertDisabled(void);
#endif /* CT_H */

300
XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/ct_standalone.c Executable file
View file

@ -0,0 +1,300 @@
/******************************************************************************
*
* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file ct_standalone.c
*
* Implements Code test (CT) utility driver.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* --- ---- -------- -----------------------------------------------
* 1.0 rmm 12/23/03 First release
* 1.1 xd 03/16/04 Changed to support PPC405 without OS.
*
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include <stdio.h>
#include <string.h>
#include <stdarg.h>
#include <unistd.h>
#include "ct.h"
#include "intg.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
unsigned CT_TotalFailures; /**< Total failures flag */
unsigned CT_TestFailures; /**< Test failures flag */
unsigned CT_TestPass; /**< Test pass flag */
/*****************************************************************************/
/**
*
* Initialize the CT subsystem.
*
* @return
*
* Nothing
*
******************************************************************************/
void CT_Init(void)
{
CT_TestFailures = 0;
CT_TotalFailures = 0;
CT_TestPass = 0;
}
/*****************************************************************************/
/**
*
* Reset for a new test and display a test specific message. This involves:
*
* - Zero out test failure counter.
* - Print a message specified by the fmt parameter and its associated
* arguments.
*
* @param fmt is a "printf" style format string.
* @param ... is a variable number of arguments that match "fmt"
*
* @return Nothing
*
******************************************************************************/
void CT_TestReset(char *fmt, ...)
{
va_list args;
CT_TestFailures = 0;
CT_TestPass = 1;
/* Print out the format and its associated argument list */
va_start(args, fmt);
printf(fmt, args);
CT_Message("\r\n=====================================================");
va_end(args);
CT_Message("\r\n");
}
/*****************************************************************************/
/**
*
* Display current test pass number to user
*
* @return
*
* Nothing
*
******************************************************************************/
void CT_NotifyNextPass(void)
{
printf("\r\n=====>Pass %d\r\n\r\n", CT_TestPass);
CT_TestPass++;
}
/*****************************************************************************/
/**
*
* Log a test failure. This involves incrementing test failure and total test
* failure counters, and displaying test specific message.
*
* @param fmt is a "printf" style format string.
* @param ... is a variable number of arguments that match "fmt"
*
* @return Nothing
*
******************************************************************************/
void CT_LogFailure(char* fmt, ...)
{
va_list args;
/*
* Increment failure counters
*/
CT_TestFailures++;
CT_TotalFailures++;
/*
* Print out the format and its associated argument list.
*/
va_start(args, fmt);
printf(fmt, args);
va_end(args);
}
/*****************************************************************************/
/**
*
* Log a test failure. This involves incrementing test failure and total test
* failure counters, and displaying test specific message.
*
* param fmt is a "printf" style format string.
* param ... is a variable number of arguments that match "fmt"
*
* @return Nothing
*
******************************************************************************/
void CT_LogFailure2()
{
/*
* Increment failure counters
*/
CT_TestFailures++;
CT_TotalFailures++;
}
/*****************************************************************************/
/**
*
* Return the number of test failures since CT_TestReset() was called.
*
* @return Number of failures logged.
*
******************************************************************************/
unsigned CT_GetTestFailures(void)
{
return(CT_TestFailures);
}
/*****************************************************************************/
/**
*
* Return the number of test failures since CT_Init() was called.
*
* @return Total number of failures logged.
*
******************************************************************************/
unsigned CT_GetTotalFailures(void)
{
return(CT_TotalFailures);
}
/*****************************************************************************/
/**
* Return status of the Xilinx driver assert mechanism.
*
* @return
*
* 1 if asserts are disabled, 0 otherwise.
*****************************************************************************/
int CT_IsAssertDisabled(void)
{
#ifdef NDEBUG
return(1);
#else
return(0);
#endif
}
/*****************************************************************************/
/**
*
* Print a message based on the given format string and parameters.
*
* @param fmt is a "printf" style format string.
* @param ... is a variable number of arguments that match "fmt"
*
* @return
*
* Nothing
*
******************************************************************************/
void CT_Message(char *fmt, ...)
{
va_list args;
va_start(args, fmt);
printf(fmt, args);
va_end(args);
}
/*****************************************************************************/
/**
*
* Set a series of bytes in memory to a specific value
*
* @param Address is the start address in memory to write
* @param Value is the value to set memory to
* @param Bytes is the number of bytes to set
*
* @return
*
* Nothing
*
******************************************************************************/
void CT_MemSet(void *Address, char Value, unsigned Bytes)
{
char* Ptr = Address;
while(Bytes--)
{
*Ptr++ = Value;
}
}

889
XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/intg.c Executable file
View file

@ -0,0 +1,889 @@
/******************************************************************************
*
* (c) Copyright 2010-14 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/******************************************************************************/
/**
*
* @file intg.c
*
* DESCRIPTION:
*
* Provides integration test entry point for the XNandPs8 component.
*
* @note None
*
* <pre>
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- ----------------------------------------------------------------
* 1.0 sb 11/28/14 First release.
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "intg.h"
#include <stdio.h>
/************************** Constant Definitions *****************************/
/**
* Main menu selections.
* @{
*/
#define MENU_MAIN_TEST 1
#define MENU_MAIN_UTIL 2
#define MENU_MAIN_EXIT 99
/*@}*/
/**
* Test sub-menu selections.
* @{
*/
#define MENU_TEST_ALL 0
#define MENU_TEST_ERASE_READ 1
#define MENU_TEST_FLASH_RW 2
#define MENU_TEST_RANDOM_RW 3
#define MENU_TEST_SPAREBYTES_RW 4
#define MENU_TEST_PARTIAL_RW 5
#define MENU_TEST_ECC 6
#define MENU_TEST_EXIT 99
/*@}*/
/**
* Create unique bitmasks from the test numbers.
* @{
*/
#define INTG_TEST_ALL 0xFFFFFFFF
#define INTG_TEST_ERASE_READ (1 << MENU_TEST_ERASE_READ)
#define INTG_TEST_FLASH_RW (1 << MENU_TEST_FLASH_RW)
#define INTG_TEST_RANDOM_RW (1 << MENU_TEST_RANDOM_RW)
#define INTG_TEST_SPAREBYTES_RW (1 << MENU_TEST_SPAREBYTES_RW)
#define INTG_TEST_PARTIAL_RW (1 << MENU_TEST_PARTIAL_RW)
#define INTG_TEST_ECC (1 << MENU_TEST_ECC)
/*@}*/
/**
* Utility sub-menu selections.
* @{
*/
#define MENU_UTIL_DATA_INTERFACE 1
#define MENU_UTIL_FLASH_DETAILS 2
#define MENU_UTIL_EXIT 99
/*@}*/
typedef enum TimingMode {
Mode0 = 0U,
Mode1,
Mode2,
Mode3,
Mode4,
Mode5
}NandPs8_TimingMode;
/*
* Uncomment the following constant definition if UART16550 is standard output
* device. If UartLite is standard output device, comment the definition
*/
//#define UART16550
/*
* Uncomment the following constant definition if UARTLITE is standard output
* device. If UART16550 is standard output device, comment the definition
*/
//#define UARTLITE
#ifdef UART16550
#include "xuartns550_l.h"
#define UART_BASEADDR XPAR_RS232_UART_BASEADDR
#elif UARTLITE
#include "xuartlite_l.h"
#define UART_BASEADDR XPAR_UARTLITE_BASEADDR
#else
#include "xuartps_hw.h"
#define UART_BASEADDR XPS_UART1_BASEADDR /**< UART-1 Base Address */
#endif
//#define printf xil_printf
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Variable Definitions *****************************/
/*
* Buffers used during read and write transactions.
*/
u8 ReadBuffer[TEST_BUF_SIZE] __attribute__ ((aligned(64)));/**< Read buffer */
u8 WriteBuffer[TEST_BUF_SIZE] __attribute__ ((aligned(64)));/**< write buffer */
/**
* Nand driver instance for the Nand device.
*/
XNandPs8 NandInstance;
XNandPs8 *NandInstPtr = &NandInstance;
XNandPs8_Config *Config;
/************************** Function Prototypes ******************************/
static unsigned int GetUserInput(char* Prompt, char* Response,
unsigned int
MaxChars);
static int GetMainMenuCommand(char* CmdLine);
static void RunTestMenu(char* CmdLine);
static void RunUtilMenu(char* CmdLine);
static int ChangeTimingMode(XNandPs8 *NandInstPtr,
XNandPs8_DataInterface NewIntf,
XNandPs8_TimingMode NewMode);
extern char inbyte (); /**< Inbyte returns the byte received by device. */
s32 FlashInit(u16 NandDeviceId);
#ifdef AUTOMATIC_TEST_MODE
int Automode_Tests(int TestLoops);
#endif
/*****************************************************************************/
/*
* Retrieve a line of input from the user. A line is defined as all characters
* up to a new line.
*
* This basically implements a fgets function. The standalone EDK stdin
* is apparently buggy because it behaves differently when new line is
* entered by itself vs. when it is entered after a number of regular chars
* have been entered. Characters entered are echoed back.
*
* @param Prompt - Printed before string is accepted to ask the user to
* enter something.
* @param Response - User entered string with new line stripped
* @param MaxChars - Maximum number of characters to read
*
* @return Number of characters read (excluding newlines)
*
*****************************************************************************/
unsigned int GetUserInput(char* Prompt, char* Response, unsigned int MaxChars)
{
int Finished, i;
/* display prompt */
if (Prompt) printf(Prompt);
Finished = 0;
i = 0;
while(!Finished && (i < MaxChars - 1)) {
/* flush out any output pending in stdout */
fflush(stdout);
/* wait for a character to arrive */
Response[i] = inbyte();
/* normal chars, add them to the string and keep going */
if ((Response[i] >= 0x20) && (Response[i] <=0x7E)) {
printf("%c", Response[i++]);
continue;
}
/* control chars */
switch(Response[i]) {
/* carriage return */
case 0x0D:
/* Case Fall through */
/* Line Feed */
case 0x0A:
Response[i++] = '\n';
Finished = 1;
printf("\r\n");
break;
/* backspace */
case 0x08:
if (i != 0) {
/* erase previous character and move
cursor back one space */
printf("\b \b");
Response[--i] = 0;
}
break;
/* ignore all other control chars */
default:
continue;
}
}
Response[i] = 0;
return i;
}
/*****************************************************************************/
/**
*
* Intg_Entry
*
* Executes all unit tests for the device
*
* param None
*
* @return None
*
* @note None
*
******************************************************************************/
void Intg_Entry(void)
{
char CmdLine[132];
s32 Status = XST_FAILURE;
#ifdef AUTOMATIC_TEST_MODE
int TestLoops;
int TestFailures;
u32 t_mode = 0U;
u32 RegVal = 0U;
u32 feature;
u32 ddr_mode[2];
#endif
/* print banner */
printf("\r\n\r\nNand Driver Integration Test\r\n");
printf("Created on %s\n\n\r", __DATE__);
printf("=====================================================\r\n");
CT_Init();
Status = FlashInit(NAND_DEVICE_ID);
if(Status != XST_SUCCESS){
printf("Nand Flash Initialization Failed\r\n");
goto Out;
}
printf("Flash initialization done\r\n");
#ifndef AUTOMATIC_TEST_MODE
/* prompt user for menu selections */
while(1) {
switch(GetMainMenuCommand(CmdLine)) {
case MENU_MAIN_TEST:
RunTestMenu(CmdLine);
break;
case MENU_MAIN_UTIL:
RunUtilMenu(CmdLine);
break;
case MENU_MAIN_EXIT:
printf("\r\nByebye! Thanks for using Nand ");
printf("and Driver integration tests :)\r\n");
return;
default:
printf("Invalid selections\r\n");
}
}
#else
/* set defaults */
TestLoops = 1;
TestFailures = 0;
/*
* Setting Interface
*/
NandInstPtr->DataInterface = SDR;
for (t_mode = Mode0; t_mode <= Mode5; t_mode++){
NandInstPtr->DataInterface = SDR;
/*
* Set Timing mode
*/
Status = ChangeTimingMode(NandInstPtr, SDR, t_mode);
if (Status != XST_SUCCESS) {
goto Out;
}
/*
* Run the test cases
*/
TestFailures += Automode_Tests(TestLoops);
}
for (t_mode = Mode0; t_mode <= Mode5; t_mode++){
NandInstPtr->DataInterface = NVDDR;
/*
* Set Timing mode
*/
Status = ChangeTimingMode(NandInstPtr, NVDDR, t_mode);
if (Status != XST_SUCCESS) {
goto Out;
}
/*
* Run the test cases
*/
TestFailures += Automode_Tests(TestLoops);
}
if (TestFailures) {
XIL_FAIL(TestFailures);
} else {
XIL_PASS();
}
#endif
Out:
exit(0);
}
#ifdef AUTOMATIC_TEST_MODE
/*****************************************************************************/
/**
*
* Auto Mode Tests
*
* Executes all unit tests for the device
*
* param TestLoops: Number of times a test should run.
*
* @return Total Test failures
*
* @note None
*
******************************************************************************/
int Automode_Tests(int TestLoops)
{
volatile int failures = 0;
failures += Intg_EraseReadTest(NandInstPtr, TestLoops);
failures += Intg_FlashRWTest(NandInstPtr, TestLoops);
failures += Intg_RandomRWTest(NandInstPtr, TestLoops);
failures += Intg_SpareBytesRWTest(NandInstPtr, TestLoops);
failures += Intg_PartialRWTest(NandInstPtr, TestLoops);
failures += Intg_EccTest(NandInstPtr, TestLoops);
return failures;
}
#endif
/*****************************************************************************/
/**
*
* Prompt the user for selections in the main menu. The user is allowed to
* enter one command at a time.
*
* @param CmdLine - Storage to use for User input.
*
* @return Numeric command entered.
*
* @note None.
*
*****************************************************************************/
static int GetMainMenuCommand(char* CmdLine)
{
/* prompt user */
printf("\r\n\r\n\r\nMain Menu:\r\n");
printf("==========\r\n");
printf("%d - Test menu\r\n", MENU_MAIN_TEST);
printf("%d - Util menu\r\n", MENU_MAIN_UTIL);
printf("%d - Exit\r\n\r\n", MENU_MAIN_EXIT);
*CmdLine = '\n';
while(*CmdLine == '\n') {
printf("Enter selection: ");
GetUserInput(0, CmdLine, 131);
}
return(atoi(CmdLine));
}
/*****************************************************************************/
/**
*
* Prompt the user for a sequence of tests to run in the test sub-menu
*
* @param CmdLine - Storage to use for User input
*
* @return None
*
* @note None
*
*****************************************************************************/
static void RunTestMenu(char* CmdLine)
{
char* Token;
char* tmp;
int QuitToMain = 0;
int TestLoops;
int TestFailures;
u32 RunTestMask;
/*
* Flash Initialization Function
*/
while(!QuitToMain) {
/* set defaults */
TestLoops = 1;
RunTestMask = 0;
TestFailures = 0;
/* prompt user */
printf("\r\n\r\n\r\nTest Menu:\r\n");
printf("==========\r\n");
printf("%d - Run all tests\r\n", MENU_TEST_ALL);
printf("%d - Flash Erase Read Test\r\n", MENU_TEST_ERASE_READ);
printf("%d - Flash Read Write Test \r\n", MENU_TEST_FLASH_RW);
printf("%d - Random Block Flash Read Write Test\r\n", MENU_TEST_RANDOM_RW);
printf("%d - Spare Bytes Read Write Test \r\n",
MENU_TEST_SPAREBYTES_RW);
printf("%d - Partial Page Read Write Test\r\n",
MENU_TEST_PARTIAL_RW);
printf("%d - ECC Test.\r\n",
MENU_TEST_ECC);
printf("%d - Exit to main menu\r\n\r\n", MENU_TEST_EXIT);
printf("More than one test can be specified\r\n");
printf("Adding l <number> sets the number of test loops\n\n");
/* wait for input */
*CmdLine = '\n';
while(*CmdLine == '\n') {
printf("Enter test(s) to execute: ");
GetUserInput(0, CmdLine, 131);
}
/* parse input line */
Token = strtok_r(CmdLine, " ", &tmp);
while(Token) {
if ((*Token == 'l') || (*Token == 'L')) {
TestLoops = atoi(Token+1);
}
else {
switch(atoi(Token)) {
case MENU_TEST_ALL:
RunTestMask |= INTG_TEST_ALL;
break;
case MENU_TEST_FLASH_RW:
RunTestMask |= INTG_TEST_FLASH_RW;
break;
case MENU_TEST_ERASE_READ:
RunTestMask |= INTG_TEST_ERASE_READ;
break;
case MENU_TEST_RANDOM_RW:
RunTestMask |= INTG_TEST_RANDOM_RW;
break;
case MENU_TEST_SPAREBYTES_RW:
RunTestMask |=
INTG_TEST_SPAREBYTES_RW;
break;
case MENU_TEST_PARTIAL_RW:
RunTestMask |=
INTG_TEST_PARTIAL_RW;
break;
case MENU_TEST_ECC:
RunTestMask |=
INTG_TEST_ECC;
break;
case MENU_TEST_EXIT:
QuitToMain = 1;
break;
default:
printf("Unknown test id %s\r\n",
Token);
}
}
Token = strtok_r(0, " ", &tmp);
}
/*
* Execute selected tests
*/
if (QuitToMain == 1) break;
printf("\r\n\r\n");
if (RunTestMask & INTG_TEST_ERASE_READ) {
TestFailures += Intg_EraseReadTest(NandInstPtr, TestLoops);
}
if (RunTestMask & INTG_TEST_FLASH_RW) {
TestFailures += Intg_FlashRWTest(NandInstPtr, TestLoops);
}
if (RunTestMask & INTG_TEST_RANDOM_RW) {
TestFailures += Intg_RandomRWTest(NandInstPtr, TestLoops);
}
if (RunTestMask & INTG_TEST_SPAREBYTES_RW) {
TestFailures += Intg_SpareBytesRWTest(NandInstPtr, TestLoops);
}
if (RunTestMask & INTG_TEST_PARTIAL_RW) {
TestFailures += Intg_PartialRWTest(NandInstPtr, TestLoops);
}
if (RunTestMask & INTG_TEST_ECC) {
TestFailures += Intg_EccTest(NandInstPtr, TestLoops);
}
printf("************************************************\r\n");
if (TestFailures) {
printf("* %d test FAILURE(s) recorded\r\n", \
TestFailures);
} else {
printf("* Tests pass\r\n");
}
printf("*********************************************\r\n");
}
}
/*****************************************************************************/
/**
*
* Prompt the user for a selection in the utility sub-menu
*
* @param CmdLine - Storage to use for User input
*
* @return None.
*
* @note None.
*
*****************************************************************************/
static void RunUtilMenu(char* CmdLine)
{
int QuitToMain = 0;
int Status = XST_FAILURE;
while(!QuitToMain) {
/* prompt user */
printf("\r\n\r\n\r\nUtil Menu:\r\n");
printf("==========\r\n");
printf("%d - Change Data Interface Timing mode- 0 for SDR, 1 for NVDDR"
"\r\n",MENU_UTIL_DATA_INTERFACE);
printf("%d - Print Flash Details\r\n",
MENU_UTIL_FLASH_DETAILS);
/* wait for input */
*CmdLine = '\n';
while(*CmdLine == '\n') {
printf("Enter selection: ");
GetUserInput(0, CmdLine, 131);
}
/* execute selection */
switch(atoi(CmdLine)) {
case MENU_UTIL_DATA_INTERFACE:
printf("Type 0 for SDR, 1 for NVDDR\r\n");
/* wait for input */
*CmdLine = '\n';
while(*CmdLine == '\n') {
printf("Enter selection: ");
GetUserInput(0, CmdLine, 131);
}
switch(atoi(CmdLine)) {
case SDR:
printf("Enter Timing Mode : 0 - 5 for SDR Interface : ");
/* wait for input */
*CmdLine = '\n';
while(*CmdLine == '\n') {
GetUserInput(0, CmdLine, 131);
}
if((u8)atoi(CmdLine) >= 0 && (u8)atoi(CmdLine) <= 5){
Status = ChangeTimingMode(NandInstPtr,SDR,(u8)atoi(CmdLine));
if (Status != XST_SUCCESS) {
printf("Data Interface / Timing Mode Change"
" failed\r\n");
}
}
else{
printf("Invalid Input\n\r");
}
break;
case NVDDR:
printf("Enter Timing Mode : 0 - 5 for NVDDR Interface : ");
/* wait for input */
*CmdLine = '\n';
while(*CmdLine == '\n') {
GetUserInput(0, CmdLine, 131);
}
if((u8)atoi(CmdLine) >= 0 && (u8)atoi(CmdLine) <= 5){
Status = ChangeTimingMode(NandInstPtr,NVDDR,(XNandPs8_TimingMode)atoi(CmdLine));
if (Status != XST_SUCCESS) {
printf("Data Interface / Timing Mode Change"
" failed\r\n");
}
}
else{
printf("Invalid Input\n\r");
}
break;
default:
printf("Invalid selection\r\n");
}
break;
case MENU_UTIL_FLASH_DETAILS:
xil_printf("Bytes Per Page: 0x%x\r\n",
NandInstPtr->Geometry.BytesPerPage);
xil_printf("Spare Bytes Per Page: 0x%x\r\n",
NandInstPtr->Geometry.SpareBytesPerPage);
xil_printf("Pages Per Block: 0x%x\r\n",
NandInstPtr->Geometry.PagesPerBlock);
xil_printf("Blocks Per LUN: 0x%x\r\n",
NandInstPtr->Geometry.BlocksPerLun);
xil_printf("Number of LUNs: 0x%x\r\n",
NandInstPtr->Geometry.NumLuns);
xil_printf("Number of bits per cell: 0x%x\r\n",
NandInstPtr->Geometry.NumBitsPerCell);
xil_printf("Number of ECC bits: 0x%x\r\n",
NandInstPtr->Geometry.NumBitsECC);
xil_printf("Block Size: 0x%x\r\n",
NandInstPtr->Geometry.BlockSize);
xil_printf("Number of Target Blocks: 0x%x\r\n",
NandInstPtr->Geometry.NumTargetBlocks);
xil_printf("Number of Target Pages: 0x%x\r\n",
NandInstPtr->Geometry.NumTargetPages);
break;
case MENU_UTIL_EXIT:
QuitToMain = 1;
break;
default:
printf("Invalid selection\r\n");
}
}
}
/****************************************************************************/
/**
*
* This functions receives a single byte using the UART. It is non-blocking in
* that it returns if there is no data received.
*
* @param Data will have the received data after this function returns
* XST_SUCCESS
*
* @return XST_SUCCESS if received a byte, XST_FAILURE otherwise
*
* @note None.
*
******************************************************************************/
int UART_RecvByte(u8 *Data)
{
#ifdef UART16550
if (!XUartNs550_IsReceiveData(UART_BASEADDR)) {
return XST_FAILURE;
} else {
*Data = XUartNs550_ReadReg(UART_BASEADDR, XUN_RBR_OFFSET);
return XST_SUCCESS;
}
#elif UARTLITE
if(XUartLite_IsReceiveEmpty(UART_BASEADDR)) {
return XST_FAILURE;
} else {
*Data = (u8)Xil_In32(UART_BASEADDR + XUL_RX_FIFO_OFFSET);
return XST_SUCCESS;
}
#else
if(!XUartPs_IsReceiveData(UART_BASEADDR)) {
return XST_FAILURE;
} else {
*Data = (u8)XUartPs_ReadReg(UART_BASEADDR,
XUARTPS_FIFO_OFFSET);
return XST_SUCCESS;
}
#endif
return XST_SUCCESS;
}
/****************************************************************************/
/**
*
* This function initialize the Nand flash.
*
* @param NandDeviceId is is the XPAR_<NAND_instance>_DEVICE_ID value
* from xparameters.h.
*
* @return
* - XST_SUCCESS if successful.
* - XST_FAILURE if failed.
*
* @note
* None
*
****************************************************************************/
s32 FlashInit(u16 NandDeviceId){
s32 Status = XST_FAILURE;
Config = XNandPs8_LookupConfig(NandDeviceId);
if (Config == NULL) {
Status = XST_FAILURE;
goto Out;
}
/*
* Initialize the flash driver.
*/
Status = XNandPs8_CfgInitialize(NandInstPtr, Config,
Config->BaseAddress);
if (Status != XST_SUCCESS) {
goto Out;
}
Out:
return Status;
}
/*****************************************************************************/
/**
*
* This function changes the data interface and timing mode.
*
* @param NandInstPtr is a pointer to the XNandPs8 instance.
* @param NewIntf is the new data interface.
* @param NewMode is the new timing mode.
*
* @return
* - XST_SUCCESS if successful.
* - XST_FAILURE if failed.
*
* @note None
*
******************************************************************************/
static int ChangeTimingMode(XNandPs8 *NandInstPtr,
XNandPs8_DataInterface NewIntf,
XNandPs8_TimingMode NewMode){
s32 Status = XST_FAILURE;
u32 t_mode = NewMode;
u32 RegVal = 0U;
u32 feature = 0U;
u32 ddr_mode[2] = {0U};
if (NewIntf == SDR){
NandInstPtr->DataInterface = SDR;
/*
* Set Timing mode
*/
Status = XNandPs8_SetFeature(NandInstPtr, 0, 0x1, &t_mode);
if (Status != XST_SUCCESS) {
goto Out;
}
/*
* Setting Interface and Timing Mode
*/
NandInstPtr->TimingMode = t_mode;
}
else{
NandInstPtr->DataInterface = NVDDR;
ddr_mode[0] = t_mode | 0x10;
/*
* Set Timing mode
*/
Status = XNandPs8_SetFeature(NandInstPtr, 0, 0x1, &ddr_mode[0]);
if (Status != XST_SUCCESS) {
goto Out;
}
/*
* Setting Interface and Timing Mode
*/
NandInstPtr->TimingMode = ddr_mode[0];
}
/*
* Setting the Data Interface Register
*/
RegVal = ((NewMode % 6U) << ((NewIntf == NVDDR) ? 3U : 0U)) |
((u32)NewIntf << XNANDPS8_DATA_INTF_DATA_INTF_SHIFT);
XNandPs8_WriteReg(NandInstPtr->Config.BaseAddress,
XNANDPS8_DATA_INTF_OFFSET, RegVal);
/*
* Get the Timing mode
*/
Status = XNandPs8_GetFeature(NandInstPtr, 0, 0x1, &feature);
if (Status != XST_SUCCESS) {
goto Out;
}
xil_printf("\tCurrent Interface type : %d, Timing mode is "
"%d\r\n\n",NandInstPtr->DataInterface,t_mode);
/*
* Check if set_feature was successful
*/
if (feature != NandInstPtr->TimingMode) {
xil_printf("Interface / Mode Changed failed %x = %x\r\n",
feature,NandInstPtr->TimingMode);
Status = XST_FAILURE;
goto Out;
}
Out:
return Status;
}
/*****************************************************************************/
/**
*
* Main entry function for the whole integration test.
*
* param None.
*
* @return 0
*
* @note None.
*
*****************************************************************************/
int main()
{
Intg_Entry();
return 0;
}

162
XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/intg.h Executable file
View file

@ -0,0 +1,162 @@
/******************************************************************************
*
* (c) Copyright 2010-14 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file intg.h - defines integration test API for the can driver
*
* @note
* TEST_METHOD has to be defined whether you want
* - internal loopback (TEST_LOOPBACK) or
* - receive/send data from/to (TEST_EXTERNAL_CAN_ANALYSER) an
* external Can Analyser.
* <pre>
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ----- -------- -----------------------------------------------
* 1.00a xd/sv 01/12/09 First release
* 1.01 kvn 26/03/14 First release for xilinx.
*
* </pre>
*
*****************************************************************************/
#ifndef INTG_H /**< prevent circular inclusions */
#define INTG_H /**< by using protection macros */
/***************************** Include Files ********************************/
#include "xparameters.h"
#include "xnandps8.h"
#include "xscugic.h"
#include "xstatus.h"
#include <stdio.h>
#include <stdlib.h>
#include "ct.h"
#include "xil_exception.h"
#include "xil_testlib.h"
#ifdef __aarch64__
#include "xreg_cortexa53.h"
#else
#include "xreg_cortexr5.h"
#endif
/************************** Constant Definitions ****************************/
/**
* Nand device and other important HW properties for this build
* @{
*/
#define INTG_XPAR_INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID
#define INTG_XPAR_DEVICE_INTR_VEC XPAR_XNANDPS8_0_INTR
#define printf xil_printf
/*@}*/
#define NAND_DEVICE_ID 0U
#define TEST_BUF_SIZE 0x4000U
#define TEST_PAGE_START 0x2U
#define TEST_BLOCK_START 0x1U
/*
* Buffers used during read and write transactions.
*/
extern u8 ReadBuffer[]; /**< read buffer */
extern u8 WriteBuffer[]; /**< write buffer */
/**
* Pele Regression tests
*/
#define AUTOMATIC_TEST_MODE
/**************************** Type Definitions ******************************/
#define printf xil_printf
/***************** Macros (Inline Functions) Definitions ********************/
/**< Clear the Structure variable to zero */
#define Intg_ClearStruct(s) (memset(&(s), 0, sizeof(s)))
/************************** Variable Definitions ****************************/
/**< XCanPs instance used throughout tests */
extern XNandPs8 NandInstance;
extern XNandPs8* NandInstPtr;
s32 MismatchCounter;
/************************** Function Prototypes *****************************/
/*
* Utility test functions implemented in intg.c
*/
void Intg_Entry(void);
int Intg_ReinitializeInstance(void);
int UART_RecvByte(u8 *Data);
/*
* Flash Erase Read test implemented in intg_erase_read.c
*/
int Intg_EraseReadTest(XNandPs8 * NandInstPtr, int TestLoops);
/*
* Flash Read Write test implemented in intg_flash_rw.c
*/
int Intg_FlashRWTest(XNandPs8 * NandInstPtr, int TestLoops);
/*
* Random Block Read Write test implemented in intg_random_rw.c
*/
int Intg_RandomRWTest(XNandPs8 * NandInstPtr, int TestLoops);
/*
* SpareBytes Read Write test implemented in intg_sparebytes_rw.c
*/
int Intg_SpareBytesRWTest(XNandPs8 * NandInstPtr,int TestLoops);
/*
* Partial Page Read Write test implemented in intg_partialpage_rw.c
*/
int Intg_PartialRWTest(XNandPs8 * NandInstPtr,int TestLoops);
/*
* ECC error check tests implemented in intg_ecc_test.c
*/
int Intg_EccTest(XNandPs8 * NandInstPtr,int TestLoops);
#endif /**< End of protection macro */

256
XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/intg_ecc_test.c Executable file
View file

@ -0,0 +1,256 @@
/******************************************************************************
*
* (c) Copyright 2010-14 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file intg_ecc_test.c
*
* This file contains the design example for using NAND driver (XNandPs8).
* This example tests the erase, read and write feature of the controller
* in the spare bytes region.The flash is erased and written. The data is
* read back and compared with the data written for correctness.
*
* @note None.
*
*
* <pre>
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ----- -------- -----------------------------------------------
* 1.0 sb 11/28/2014 First release
*
*
* </pre>
*
******************************************************************************/
/***************************** Include Files ********************************/
#include "intg.h"
/************************** Constant Definitions ****************************/
/**************************** Type Definitions ******************************/
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Variable Definitions ****************************/
/************************** Function Prototypes *****************************/
s32 Ecc_Test(XNandPs8 * NandInstPtr, u16 NandDeviceId);
/************************** Function Definitions ****************************/
/****************************************************************************/
/**
*
* Entry point to call the ECC R/W test.
*
* @param NandInstPtr - Instance to the nand driver.
* @param TestLoops - Number of tests to execute.
*
* @return Number of test failures.
*
* @note None.
*
*****************************************************************************/
int Intg_EccTest(XNandPs8 * NandInstPtr, int TestLoops)
{
s32 Status = XST_FAILURE;
CT_TestReset("Module Ecc Error Check test");
while(TestLoops--) {
/* Get the configuration table entry for this CAN device */
Status = Ecc_Test(NandInstPtr, NAND_DEVICE_ID);
if (Status != XST_SUCCESS) {
CT_LOG_FAILURE("Ecc Error Check Test Failed with "
"%d mismatches\r\n", MismatchCounter);
break;
}
CT_NotifyNextPass();
}
return(CT_GetTestFailures());
}
/****************************************************************************/
/**
*
* This function runs a test on the NAND flash device using the basic driver
* functions in polled mode.
* The function does the following tasks:
* - Erase the flash.
* - Write data to the flash.
* - Read back the data from the flash.
* - Compare the data read against the data Written.
* - Corrupt data by writing random data to flash
* - Read back the data from the flash.
* - Compare the data read against the data Written before corruption.
*
* @param NandInstPtr - Instance to the nand driver.
* @param NandDeviceId is is the XPAR_<NAND_instance>_DEVICE_ID value
* from xparameters.h.
*
* @return
* - XST_SUCCESS if successful.
* - XST_FAILURE if failed.
*
* @note
* None
*
****************************************************************************/
s32 Ecc_Test(XNandPs8 * NandInstPtr, u16 NandDeviceId)
{
s32 Status = XST_FAILURE;
u32 Index;
u64 Offset;
u32 Length;
s32 i;
MismatchCounter = 0;
NandInstPtr->BCH_Error_Status = 0;
Offset = (u64)(TEST_PAGE_START * NandInstPtr->Geometry.BytesPerPage);
Length = NandInstPtr->Geometry.BytesPerPage;
/*
* Initialize the write buffer
*/
for (Index = 0; Index < Length;Index++) {
WriteBuffer[Index] = (u8)0;
}
/*
* Enable ECC
*/
XNandPs8_EnableEccMode(NandInstPtr);
/*
* Erase the flash
*/
Status = XNandPs8_Erase(NandInstPtr, (u64)Offset, (u64)Length);
if (Status != XST_SUCCESS) {
goto Out;
}
/*
* Write to flash
*/
Status = XNandPs8_Write(NandInstPtr, (u64)Offset, (u64)Length,
&WriteBuffer[0]);
if (Status != XST_SUCCESS) {
goto Out;
}
/*
* Read the flash after writing
*/
Status = XNandPs8_Read(NandInstPtr, (u64)Offset, (u64)Length,
&ReadBuffer[0]);
if (Status != XST_SUCCESS) {
goto Out;
}
/*
* Compare the results
*/
for (Index = 0U; Index < Length;Index++) {
if (ReadBuffer[Index] != WriteBuffer[Index]) {
MismatchCounter++;
Status = XST_FAILURE;
}
}
for (i = 0 ; i<24 ; i++){
/*
* Disable ECC
*/
XNandPs8_DisableEccMode(NandInstPtr);
/*
* Corrupting data in Write buffer
*/
WriteBuffer[i] = (u8)(i+1);
/*
* Write to flash
*/
Status = XNandPs8_Write(NandInstPtr, (u64)Offset, (u64)Length,
&WriteBuffer[0]);
if (Status != XST_SUCCESS) {
goto Out;
}
/*
* Correcting back data in Write buffer
*/
WriteBuffer[i] = (u8)0;
/*
* Enable ECC check
*/
XNandPs8_EnableEccMode(NandInstPtr);
/*
* Read the flash after writing
*/
Status = XNandPs8_Read(NandInstPtr, (u64)Offset, (u64)Length,
&ReadBuffer[0]);
if (Status != XST_SUCCESS) {
goto Out;
}
/*
* Compare the results
*/
for (Index = 0U; Index < Length;Index++) {
if (ReadBuffer[Index] != WriteBuffer[Index]) {
MismatchCounter++;
Status = XST_FAILURE;
}
}
}
xil_printf("Total BCH ECC errors = %d\r\n",NandInstPtr->BCH_Error_Status);
Out:
return Status;
}

193
XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/intg_erase_read.c Executable file
View file

@ -0,0 +1,193 @@
/******************************************************************************
*
* (c) Copyright 2010-14 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file intg_erase_read.c
*
* This file contains the design example for using NAND driver (XNandPs8).
* This example tests the erase and read feature of the controller.
* The flash is erased. The data is
* read back and compared with the 0xFF for correctness.
*
* @note None.
*
*
* <pre>
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ----- -------- -----------------------------------------------
* 1.0 sb 11/28/2014 First release
*
*
* </pre>
*
******************************************************************************/
/***************************** Include Files ********************************/
#include "intg.h"
/************************** Constant Definitions ****************************/
/**************************** Type Definitions ******************************/
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Variable Definitions ****************************/
/************************** Function Prototypes *****************************/
s32 Erase_Read_Test(XNandPs8 * NandInstPtr, u16 NandDeviceId);
/************************** Function Definitions ****************************/
/****************************************************************************/
/**
*
* Entry point to call the Erase Read test.
*
* @param NandInstPtr - Instance to the nand driver.
* @param TestLoops - Number of tests to execute.
*
* @return Number of test failures.
*
* @note None.
*
*****************************************************************************/
int Intg_EraseReadTest(XNandPs8 * NandInstPtr, int TestLoops)
{
s32 Status = XST_FAILURE;
CT_TestReset("Module FLASH Erase Read test");
while(TestLoops--) {
/* Get the configuration table entry for this CAN device */
Status = Erase_Read_Test(NandInstPtr, NAND_DEVICE_ID);
if (Status != XST_SUCCESS) {
CT_LOG_FAILURE("Nand Flash Erase ReadTest Failed"
" with %d mismatches\r\n", MismatchCounter);
break;
}
CT_NotifyNextPass();
}
return(CT_GetTestFailures());
}
/****************************************************************************/
/**
*
* This function runs a test on the NAND flash device using the basic driver
* functions in polled mode.
* The function does the following tasks:
* - Erase the flash.
* - Read back the data from the flash.
* - Compare the data read against 0xFF.
*
* @param NandInstPtr - Instance to the nand driver.
* @param NandDeviceId is is the XPAR_<NAND_instance>_DEVICE_ID value
* from xparameters.h.
*
* @return
* - XST_SUCCESS if successful.
* - XST_FAILURE if failed.
*
* @note
* None
*
****************************************************************************/
s32 Erase_Read_Test(XNandPs8 * NandInstPtr, u16 NandDeviceId)
{
s32 Status = XST_FAILURE;
s32 i = 0;
u32 Index;
u64 Offset;
u32 Length;
u32 BlockSize = NandInstPtr->Geometry.BlockSize;
MismatchCounter = 0;
Offset = (u64)TEST_BLOCK_START * NandInstPtr->Geometry.BlockSize;
Length = NandInstPtr->Geometry.BytesPerPage;
/*
* Erasing whole block
*/
Status = XNandPs8_Erase(NandInstPtr, (u64)Offset, (u64)BlockSize);
if (Status != XST_SUCCESS) {
goto Out;
}
for (i = 0; i < NandInstPtr->Geometry.PagesPerBlock; i++){
/*
* Disbale ECC
*/
XNandPs8_DisableEccMode(NandInstPtr);
/*
* Read the flash after writing
*/
Status = XNandPs8_Read(NandInstPtr, (u64)Offset, (u64)Length,
&ReadBuffer[0]);
if (Status != XST_SUCCESS) {
goto Out;
}
/*
* Enable ECC
*/
XNandPs8_EnableEccMode(NandInstPtr);
/*
* Compare the results
*/
for (Index = 0U; Index < Length;Index++) {
if (ReadBuffer[Index] != (u8)0xFF) {
MismatchCounter++;
Status = XST_FAILURE;
}
}
Offset = Offset + NandInstPtr->Geometry.BytesPerPage;
}
Out:
return Status;
}

194
XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/intg_flash_rw.c Executable file
View file

@ -0,0 +1,194 @@
/******************************************************************************
*
* (c) Copyright 2010-14 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file intg_flash_rw.c
*
* This file contains the design example for using NAND driver (XNandPs8).
* This example tests the erase, read and write feature of the controller.
* The flash is erased and written. The data is
* read back and compared with the data written for correctness.
*
* @note None.
*
*
* <pre>
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ----- -------- -----------------------------------------------
* 1.0 sb 11/28/2014 First release
*
*
* </pre>
*
******************************************************************************/
/***************************** Include Files ********************************/
#include "intg.h"
/************************** Constant Definitions ****************************/
/**************************** Type Definitions ******************************/
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Variable Definitions ****************************/
/************************** Function Prototypes *****************************/
s32 Flash_RW_Test(XNandPs8 * NandInstPtr, u16 NandDeviceId);
/************************** Function Definitions ****************************/
/****************************************************************************/
/**
*
* Entry point to call the Flash R/W test.
*
* @param NandInstPtr - Instance to the nand driver.
* @param TestLoops - Number of tests to execute.
*
* @return Number of test failures.
*
* @note None.
*
*****************************************************************************/
int Intg_FlashRWTest(XNandPs8 * NandInstPtr, int TestLoops)
{
s32 Status = XST_FAILURE;
CT_TestReset("Module FLASH Read Write test");
while(TestLoops--) {
/* Get the configuration table entry for this CAN device */
Status = Flash_RW_Test(NandInstPtr, NAND_DEVICE_ID);
if (Status != XST_SUCCESS) {
CT_LOG_FAILURE("Nand Flash Read Write Test Failed"
" with %d mismatches\r\n", MismatchCounter);
break;
}
CT_NotifyNextPass();
}
return(CT_GetTestFailures());
}
/****************************************************************************/
/**
*
* This function runs a test on the NAND flash device using the basic driver
* functions in polled mode.
* The function does the following tasks:
* - Initialize the driver.
* - Erase the flash.
* - Write data to the flash.
* - Read back the data from the flash.
* - Compare the data read against the data Written.
*
* @param NandInstPtr - Instance to the nand driver.
* @param NandDeviceId is is the XPAR_<NAND_instance>_DEVICE_ID value
* from xparameters.h.
*
* @return
* - XST_SUCCESS if successful.
* - XST_FAILURE if failed.
*
* @note
* None
*
****************************************************************************/
s32 Flash_RW_Test(XNandPs8 * NandInstPtr, u16 NandDeviceId)
{
s32 Status = XST_FAILURE;
u32 Index;
u64 Offset;
u32 Length;
MismatchCounter = 0;
Offset = (u64)(TEST_PAGE_START * NandInstPtr->Geometry.BytesPerPage);
Length = NandInstPtr->Geometry.BytesPerPage;
/*
* Initialize the write buffer
*/
for (Index = 0; Index < Length;Index++) {
WriteBuffer[Index] = (u8) (rand() % 256);
}
/*
* Erase the Block
*/
Status = XNandPs8_Erase(NandInstPtr, (u64)Offset, (u64)Length);
if (Status != XST_SUCCESS) {
goto Out;
}
/*
* Write to page offset
*/
Status = XNandPs8_Write(NandInstPtr, (u64)Offset, (u64)Length,
&WriteBuffer[0]);
if (Status != XST_SUCCESS) {
goto Out;
}
/*
* Read from the page after writing
*/
Status = XNandPs8_Read(NandInstPtr, (u64)Offset, (u64)Length,
&ReadBuffer[0]);
if (Status != XST_SUCCESS) {
goto Out;
}
/*
* Compare the results
*/
for (Index = 0U; Index < 10;Index++) {
if (ReadBuffer[Index] != WriteBuffer[Index]) {
MismatchCounter++;
Status = XST_FAILURE;
}
}
Out:
return Status;
}

208
XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/intg_partialpage_rw.c Executable file
View file

@ -0,0 +1,208 @@
/******************************************************************************
*
* (c) Copyright 2010-14 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file intg_partialpage_rw.c
*
* This file contains the design example for using NAND driver (XNandPs8).
* This example tests the erase, read and write feature of the controller
* to the page.The flash is erased and written. The data is
* read back and compared with the data written for correctness.
*
* @note None.
*
*
* <pre>
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ----- -------- -----------------------------------------------
* 1.0 sb 11/28/2014 First release
*
*
* </pre>
*
******************************************************************************/
/***************************** Include Files ********************************/
#include "intg.h"
/************************** Constant Definitions ****************************/
/**************************** Type Definitions ******************************/
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Variable Definitions ****************************/
/************************** Function Prototypes *****************************/
s32 PartialPage_RW_Test(XNandPs8 * NandInstPtr, u16 NandDeviceId);
/************************** Function Definitions ****************************/
/****************************************************************************/
/**
*
* Entry point to call the Partial Page R/W test.
*
* @param NandInstPtr - Instance to the nand driver.
* @param TestLoops - Number of tests to execute.
*
* @return Number of test failures.
*
* @note None.
*
*****************************************************************************/
int Intg_PartialRWTest(XNandPs8 * NandInstPtr, int TestLoops)
{
s32 Status = XST_FAILURE;
CT_TestReset("Module Partial Page Read Write test");
while(TestLoops--) {
/* Get the configuration table entry for this CAN device */
Status = PartialPage_RW_Test(NandInstPtr, NAND_DEVICE_ID);
if (Status != XST_SUCCESS) {
CT_LOG_FAILURE("Nand Partial Page Read Write Failed"
" with %d mismatches\r\n", MismatchCounter);
break;
}
CT_NotifyNextPass();
}
return(CT_GetTestFailures());
}
/****************************************************************************/
/**
*
* This function runs a test on the NAND flash device using the basic driver
* functions in polled mode.
* The function does the following tasks:
* - Choose random page size for read write Operations.
* - Erase the flash.
* - Write data to the flash.
* - Read back the data from the flash.
* - Compare the data read against the data Written.
*
* @param NandInstPtr - Instance to the nand driver.
* @param NandDeviceId is is the XPAR_<NAND_instance>_DEVICE_ID value
* from xparameters.h.
*
* @return
* - XST_SUCCESS if successful.
* - XST_FAILURE if failed.
*
* @note
* None
*
****************************************************************************/
s32 PartialPage_RW_Test(XNandPs8 * NandInstPtr, u16 NandDeviceId)
{
s32 Status = (s32)XST_FAILURE;
u32 Index;
u64 Offset;
u32 Length;
s32 i;
MismatchCounter = 0;
Offset = (u64)(TEST_PAGE_START * (u64)NandInstPtr->Geometry.BytesPerPage);
Length = NandInstPtr->Geometry.BytesPerPage;
/*
* Repeat the test for 20 iterations
*/
for(i = 0; i< 5; i++){
Length = rand()%NandInstPtr->Geometry.BytesPerPage;
if(Length == 0U){
Length = NandInstPtr->Geometry.BytesPerPage;
}
/*
* Erase the Block
*/
Status = XNandPs8_Erase(NandInstPtr, (u64)Offset, (u64)Length);
if (Status != (s32)XST_SUCCESS) {
goto Out;
}
/*
* Initialize the write buffer
*/
for (Index = 0U; Index < Length;Index++) {
WriteBuffer[Index] = ((u8)rand() % (u8)256);
}
/*
* Write to flash
*/
Status = XNandPs8_Write(NandInstPtr, (u64)Offset, (u64)Length,
&WriteBuffer[0]);
if (Status != (s32)XST_SUCCESS) {
goto Out;
}
/*
* Read the flash after writing
*/
Status = XNandPs8_Read(NandInstPtr, (u64)Offset, (u64)Length,
&ReadBuffer[0]);
if (Status != (s32)XST_SUCCESS) {
goto Out;
}
/*
* Compare the results
*/
for (Index = 0U; Index < Length;Index++) {
if (ReadBuffer[Index] != WriteBuffer[Index]) {
MismatchCounter++;
Status = (s32)XST_FAILURE;
}
}
}
Out:
return Status;
}

209
XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/intg_random_rw.c Executable file
View file

@ -0,0 +1,209 @@
/******************************************************************************
*
* (c) Copyright 2010-14 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file intg_random_rw.c
*
* This file contains the design example for using NAND driver (XNandPs8).
* This example tests the erase, read and write feature of the controller
* to a complete block. The block is randomly selected.
* The flash is erased and written. The data is read back and compared
* with the data written for correctness.
*
* @note None.
*
*
* <pre>
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ----- -------- -----------------------------------------------
* 1.0 sb 11/28/2014 First release
*
*
* </pre>
*
******************************************************************************/
/***************************** Include Files ********************************/
#include "intg.h"
/************************** Constant Definitions ****************************/
/**************************** Type Definitions ******************************/
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Variable Definitions ****************************/
/************************** Function Prototypes *****************************/
s32 Random_Block_RW_Test(XNandPs8 * NandInstPtr, u16 NandDeviceId);
/************************** Function Definitions ****************************/
/****************************************************************************/
/**
*
* Entry point to call the Random Block Read Write test.
*
* @param NandInstPtr - Instance to the nand driver.
* @param TestLoops - Number of tests to execute.
*
* @return Number of test failures.
*
* @note None.
*
*****************************************************************************/
int Intg_RandomRWTest(XNandPs8 * NandInstPtr, int TestLoops)
{
s32 Status = XST_FAILURE;
CT_TestReset("Module Random Block Read Write test");
while(TestLoops--) {
/* Get the configuration table entry for this CAN device */
Status = Random_Block_RW_Test(NandInstPtr, NAND_DEVICE_ID);
if (Status != XST_SUCCESS) {
CT_LOG_FAILURE("Nand Random Block Read Write Test Failed"
" with %d mismatches\r\n", MismatchCounter);
break;
}
CT_NotifyNextPass();
}
return(CT_GetTestFailures());
}
/****************************************************************************/
/**
*
* This function runs a test on the NAND flash device using the basic driver
* functions in polled mode.
* The function does the following tasks:
* - Initialize the driver.
* - Erase the flash.
* - Write data to the flash.
* - Read back the data from the flash.
* - Compare the data read against the data Written.
*
* @param NandInstPtr - Instance to the nand driver.
* @param NandDeviceId is is the XPAR_<NAND_instance>_DEVICE_ID value
* from xparameters.h.
*
* @return
* - XST_SUCCESS if successful.
* - XST_FAILURE if failed.
*
* @note
* None
*
****************************************************************************/
s32 Random_Block_RW_Test(XNandPs8 * NandInstPtr, u16 NandDeviceId)
{
s32 Status = XST_FAILURE;
u32 Index;
u64 Offset;
u32 Length;
s32 i = 0;
u32 BlockSize = NandInstPtr->Geometry.BlockSize;
Offset = (u64) ((rand()% 50) *
NandInstPtr->Geometry.BlockSize);
Length = NandInstPtr->Geometry.BytesPerPage;
/*
* Erase the Block
*/
Status = XNandPs8_Erase(NandInstPtr, (u64)Offset, (u64)BlockSize);
if (Status != XST_SUCCESS) {
goto Out;
}
/*
* Flash operation i.e. erase, write and read for all the pages
* of the block.
* This test will take some time to execute. Please be patient.
*/
for (i = 0; i < NandInstPtr->Geometry.PagesPerBlock; i++){
/*
* Initialize the write buffer
*/
for (Index = 0; Index < Length;Index++) {
WriteBuffer[Index] = (u8) (rand() % 256);
}
/*
* Write to flash
*/
Status = XNandPs8_Write(NandInstPtr, (u64)Offset, (u64)Length,
&WriteBuffer[0]);
if (Status != XST_SUCCESS) {
goto Out;
}
/*
* Read the flash after writing
*/
Status = XNandPs8_Read(NandInstPtr, (u64)Offset, (u64)Length,
&ReadBuffer[0]);
if (Status != XST_SUCCESS) {
goto Out;
}
/*
* Compare the results
*/
for (Index = 0U; Index < Length;Index++) {
if (ReadBuffer[Index] != WriteBuffer[Index]) {
MismatchCounter++;
Status = XST_FAILURE;
}
}
Offset = Offset + NandInstPtr->Geometry.BytesPerPage;
}
Out:
return Status;
}

215
XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/intg_sparebytes_rw.c Executable file
View file

@ -0,0 +1,215 @@
/******************************************************************************
*
* (c) Copyright 2010-14 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file intg_sparebytes_rw.c
*
* This file contains the design example for using NAND driver (XNandPs8).
* This example tests the erase, read and write feature of the controller
* in the spare bytes region.The flash is erased and written. The data is
* read back and compared with the data written for correctness.
*
* @note None.
*
*
* <pre>
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ----- -------- -----------------------------------------------
* 1.0 sb 11/28/2014 First release
*
* </pre>
*
******************************************************************************/
/***************************** Include Files ********************************/
#include "intg.h"
/************************** Constant Definitions ****************************/
/**************************** Type Definitions ******************************/
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Variable Definitions ****************************/
/************************** Function Prototypes *****************************/
s32 SpareBytes_RW_Test(XNandPs8 * NandInstPtr, u16 NandDeviceId);
/************************** Function Definitions ****************************/
/****************************************************************************/
/**
*
* Entry point to call the Spare Bytes test.
*
* @param NandInstPtr - Instance to the nand driver.
* @param TestLoops - Number of tests to execute.
*
* @return Number of test failures.
*
* @note None.
*
*****************************************************************************/
int Intg_SpareBytesRWTest(XNandPs8 * NandInstPtr, int TestLoops)
{
s32 Status = XST_FAILURE;
CT_TestReset("Module Spare Bytes Read Write test");
while(TestLoops--) {
/* Get the configuration table entry for this CAN device */
Status = SpareBytes_RW_Test(NandInstPtr, NAND_DEVICE_ID);
if (Status != XST_SUCCESS) {
CT_LOG_FAILURE("Nand Spare Bytes Read Write Test Failed"
" with %d mismatches\r\n", MismatchCounter);
break;
}
CT_NotifyNextPass();
}
return(CT_GetTestFailures());
}
/****************************************************************************/
/**
*
* This function runs a test on the NAND flash device using the basic driver
* functions in polled mode.
* The function does the following tasks:
* - Erase the flash.
* - Write data to the spare byte section of flash.
* - Read back the data from the spare byte section of flash.
* - Compare the data read against the data Written.
*
* @param NandInstPtr - Instance to the nand driver.
* @param NandDeviceId is is the XPAR_<NAND_instance>_DEVICE_ID value
* from xparameters.h.
*
* @return
* - XST_SUCCESS if successful.
* - XST_FAILURE if failed.
*
* @note
* None
*
****************************************************************************/
s32 SpareBytes_RW_Test(XNandPs8 * NandInstPtr, u16 NandDeviceId)
{
s32 Status = XST_FAILURE;
u32 Index;
u64 Offset;
u16 Length;
s32 i;
MismatchCounter = 0;
Offset = (u64)(TEST_PAGE_START * NandInstPtr->Geometry.BytesPerPage);
Length = NandInstPtr->Geometry.BytesPerPage;
/*
* Erase the flash
*/
Status = XNandPs8_Erase(NandInstPtr, (u64)Offset, (u64)Length);
if (Status != XST_SUCCESS) {
goto Out;
}
/*
* Repeat the test for 10 iterations
*/
for(i = 0; i< 10; i++){
Length = rand() % NandInstPtr->Geometry.SpareBytesPerPage;
if(Length == 0U){
Length = NandInstPtr->Geometry.SpareBytesPerPage;
}
/*
* Initialize the write buffer
*/
for (Index = 0; Index < Length;Index++) {
WriteBuffer[Index] = (u8) (rand() % 256);
}
/*
* Disable the ECC mode
*/
XNandPs8_DisableEccMode(NandInstPtr);
/*
* Write to flash Spare Bytes Section
*/
Status = XNandPs8_WriteSpareBytes(NandInstPtr, (u32)Offset,
&WriteBuffer[0]);
if (Status != XST_SUCCESS) {
goto Out;
}
/*
* Read from the flash Spare Bytes after writing
*/
Status = XNandPs8_ReadSpareBytes(NandInstPtr, (u32)Offset,
&ReadBuffer[0]);
if (Status != XST_SUCCESS) {
goto Out;
}
/*
* Enable the ECC mode
*/
XNandPs8_EnableEccMode(NandInstPtr);
/*
* Compare the results
*/
for (Index = 0U; Index < Length;Index++) {
if (ReadBuffer[Index] != WriteBuffer[Index]) {
MismatchCounter++;
Status = XST_FAILURE;
}
}
}
Status = XST_SUCCESS;
Out:
return Status;
}

96
XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/xil_testlib.h Executable file
View file

@ -0,0 +1,96 @@
/* $Id: xil_testlib.h,v 1.00 2009/2/19 */
/******************************************************************************
*
* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/***************************** Include Files *********************************/
#include <xil_printf.h>
#include "intg.h"
/**
*
* @file xil_testlib.h
*
* This file contains Xilinx software exit messages.These messages are set to be
* matched with the scan strings for board test such that board test would know
* the result of a standalone test program
*
******************************************************************************/
#ifndef XIL_TESTLIB_H /**< prevent circular inclusions */
#define XIL_TESTLIB_H /**< by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************** Macros (Inline Functions) Definitions *********************/
/**
* XIL_PASS puts out a message to signal board test that a program has pass
* the testing program without errors
*
* param None.
*
* @return None.
*
* @note None.
*/
#define XIL_PASS() xil_printf("\r\nREGRESSION TEST PASS.\r\n")
/*
* XIL_FAIL puts out a message to signal board test that a program has not pass
* the testing program
*
* @param number of errors.
*
* @return None.
*
* @note None.
*/
#define XIL_FAIL(numErrors) \
xil_printf("\r\nREGRESSION TEST FAIL WITH %d ERRORS.\r\n", numErrors)
#ifdef __cplusplus
}
#endif
#endif /**< End of protection macro */

83
XilinxProcessorIPLib/drivers/nandps8_v2_0/src/Makefile Executable file
View file

@ -0,0 +1,83 @@
#/******************************************************************************
#*
#* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
#*
#* This file contains confidential and proprietary information of Xilinx, Inc.
#* and is protected under U.S. and international copyright and other
#* intellectual property laws.
#*
#* DISCLAIMER
#* This disclaimer is not a license and does not grant any rights to the
#* materials distributed herewith. Except as otherwise provided in a valid
#* license issued to you by Xilinx, and to the maximum extent permitted by
#* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
#* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
#* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
#* MERCHANTABILITY, NON- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
#* and
#* (2) Xilinx shall not be liable (whether in contract or tort, including
#* negligence, or under any other theory of liability) for any loss or damage
#* of any kind or nature related to, arising under or in connection with these
#* materials, including for any direct, or any indirect, special, incidental,
#* or consequential loss or damage (including loss of data, profits,
#* goodwill, or any type of loss or damage suffered as a result of any
#* action brought by a third party) even if such damage or loss was
#* reasonably foreseeable or Xilinx had been advised of the possibility
#* of the same.
#*
#* CRITICAL APPLICATIONS
#* Xilinx products are not designed or intended to be fail- safe, or for use
#* in any application requiring fail-safe performance, such as life-support
#* or safety devices or systems, Class III medical devices, nuclear
#* facilities, applications related to the deployment of airbags, or any
#* other applications that could lead to death, personal injury, or severe
#* property or environmental damage (individually and collectively,
#* "Critical Applications"). Customer assumes the sole risk and liability
#* of any use of Xilinx products in Critical Applications, subject only to
#* applicable laws and regulations governing limitations on product liability.
#*
#* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART
#* OF THIS FILE AT ALL TIMES.
#*
#******************************************************************************/
COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
CC_FLAGS = $(COMPILER_FLAGS)
ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}
OUTS = *.o
LIBSOURCES:=*.c
INCLUDEFILES:=*.h
OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
libs: banner xuartps_libs clean
%.o: %.c
${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
banner:
echo "Compiling nandps8"
xuartps_libs: ${OBJECTS}
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
.PHONY: include
include: xuartps_includes
xuartps_includes:
${CP} ${INCLUDEFILES} ${INCLUDEDIR}
clean:
rm -rf ${OBJECTS}

4144
XilinxProcessorIPLib/drivers/nandps8_v2_0/src/xnandps8.c Executable file
View file

File diff suppressed because it is too large Load diff

568
XilinxProcessorIPLib/drivers/nandps8_v2_0/src/xnandps8.h Executable file
View file

@ -0,0 +1,568 @@
/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
* and
* (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits,
* goodwill, or any type of loss or damage suffered as a result of any
* action brought by a third party) even if such damage or loss was
* reasonably foreseeable or Xilinx had been advised of the possibility
* of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail- safe, or for use
* in any application requiring fail-safe performance, such as life-support
* or safety devices or systems, Class III medical devices, nuclear
* facilities, applications related to the deployment of airbags, or any
* other applications that could lead to death, personal injury, or severe
* property or environmental damage (individually and collectively,
* "Critical Applications"). Customer assumes the sole risk and liability
* of any use of Xilinx products in Critical Applications, subject only to
* applicable laws and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART
* OF THIS FILE AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xnandps8.h
*
* This file implements a driver to support Arasan NAND controller
* present in Zynq Ultrascale Mp.
*
* <b>Driver Initialization</b>
*
* The function call XNandPs8_CfgInitialize() should be called by the application
* before any other function in the driver. The initialization function takes
* device specific data (like device id, instance id, and base address) and
* initializes the XNandPs8 instance with the device specific data.
*
* <b>Device Geometry</b>
*
* NAND flash device is memory device and it is segmented into areas called
* Logical Unit(s) (LUN) and further in to blocks and pages. A NAND flash device
* can have multiple LUN. LUN is sequential raw of multiple blocks of the same
* size. A block is the smallest erasable unit of data within the Flash array of
* a LUN. The size of each block is based on a power of 2. There is no
* restriction on the number of blocks within the LUN. A block contains a number
* of pages. A page is the smallest addressable unit for read and program
* operations. The arrangement of LUN, blocks, and pages is referred to by this
* module as the part's geometry.
*
* The cells within the part can be programmed from a logic 1 to a logic 0
* and not the other way around. To change a cell back to a logic 1, the
* entire block containing that cell must be erased. When a block is erased
* all bytes contain the value 0xFF. The number of times a block can be
* erased is finite. Eventually the block will wear out and will no longer
* be capable of erasure. As of this writing, the typical flash block can
* be erased 100,000 or more times.
*
* The jobs done by this driver typically are:
* - 8-bit operational mode
* - Read, Write, and Erase operation
*
* <b>Write Operation</b>
*
* The write call can be used to write a minimum of one byte and a maximum
* entire flash. If the address offset specified to write is out of flash or if
* the number of bytes specified from the offset exceed flash boundaries
* an error is reported back to the user. The write is blocking in nature in that
* the control is returned back to user only after the write operation is
* completed successfully or an error is reported.
*
* <b>Read Operation</b>
*
* The read call can be used to read a minimum of one byte and maximum of
* entire flash. If the address offset specified to read is out of flash or if
* the number of bytes specified from the offset exceed flash boundaries
* an error is reported back to the user. The read is blocking in nature in that
* the control is returned back to user only after the read operation is
* completed successfully or an error is reported.
*
* <b>Erase Operation</b>
*
* The erase operations are provided to erase a Block in the Flash memory. The
* erase call is blocking in nature in that the control is returned back to user
* only after the erase operation is completed successfully or an error is
* reported.
*
* @note
*
* This driver is intended to be RTOS and processor independent. It works with
* physical addresses only. Any needs for dynamic memory management, threads,
* mutual exclusion, virtual memory, cache control, or HW write protection
* management must be satisfied by the layer above this driver.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- ---------- -----------------------------------------------
* 1.0 nm 05/06/2014 First release
* 2.0 sb 11/04/2014 Removed Null checks for Buffer passed
* as parameter to Read API's
* - XNandPs8_Read()
* - XNandPs8_ReadPage
* Modified
* - XNandPs8_SetFeature()
* - XNandPs8_GetFeature()
* and made them public.
* Removed Failure Return for BCF Error check in
* XNandPs8_ReadPage() and added BCH_Error counter
* in the instance pointer structure.
* Added XNandPs8_Prepare_Cmd API
* Replaced
* - XNandPs8_IntrStsEnable
* - XNandPs8_IntrStsClear
* - XNandPs8_IntrClear
* - XNandPs8_SetProgramReg
* with XNandPs8_WriteReg call
* Modified xnandps8.c file API's with above changes.
* Corrected the program command for Set Feature API.
* Modified
* - XNandPs8_OnfiReadStatus
* - XNandPs8_GetFeature
* - XNandPs8_SetFeature
* to add support for DDR mode.
* Changed Convention for SLC/MLC
* SLC --> HAMMING
* MLC --> BCH
* SlcMlc --> IsBCH
* Added support for writing BBT signature and version
* in page section by enabling XNANDPS8_BBT_NO_OOB.
* Removed extra DMA mode initialization from
* the XNandPs8_CfgInitialize API.
* Modified
* - XNandPs8_SetEccAddrSize
* ECC address now is calculated based upon the
* size of spare area
* </pre>
*
******************************************************************************/
#ifndef XNANDPS8_H /* prevent circular inclusions */
#define XNANDPS8_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include <string.h>
#include "xstatus.h"
#include "xil_assert.h"
#include "xnandps8_hw.h"
#include "xnandps8_onfi.h"
#include "xil_cache.h"
/************************** Constant Definitions *****************************/
#define XNANDPS8_DEBUG
#define RTL_3_1_FIX
#define RTL_3_1_DRIVER_WORKAROUND
#define XNANDPS8_MAX_TARGETS 1U /**< ce_n0, ce_n1 */
#define XNANDPS8_MAX_PKT_SIZE 0x7FFU /**< Max packet size */
#define XNANDPS8_MAX_PKT_COUNT 0xFFFU /**< Max packet count */
#define XNANDPS8_PAGE_SIZE_512 512U /**< 512 bytes page */
#define XNANDPS8_PAGE_SIZE_2K 2048U /**< 2K bytes page */
#define XNANDPS8_PAGE_SIZE_4K 4096U /**< 4K bytes page */
#define XNANDPS8_PAGE_SIZE_8K 8192U /**< 8K bytes page */
#define XNANDPS8_PAGE_SIZE_16K 16384U /**< 16K bytes page */
#define XNANDPS8_PAGE_SIZE_1K_16BIT 1024U /**< 16-bit 2K bytes page */
#define XNANDPS8_MAX_PAGE_SIZE 16384U /**< Max page size supported */
#define XNANDPS8_BUS_WIDTH_8 0U /**< 8-bit bus width */
#define XNANDPS8_BUS_WIDTH_16 1U /**< 16-bit bus width */
#define XNANDPS8_HAMMING 0x1U /**< Hamming Flash */
#define XNANDPS8_BCH 0x2U /**< BCH Flash */
#define XNANDPS8_MAX_BLOCKS 32768U /**< Max number of Blocks */
#define XNANDPS8_MAX_SPARE_SIZE 0x800U /**< Max spare bytes of a NAND
flash page of 16K */
#define XNANDPS8_INTR_POLL_TIMEOUT 10000U
#define SDR_CLK ((u16)100U * (u16)1000U * (u16)1000U)
#define NVDDR_CLK_0 ((u16)20U * (u16)1000U * (u16)1000U)
#define NVDDR_CLK_1 ((u16)33U * (u16)1000U * (u16)1000U)
#define NVDDR_CLK_2 ((u16)50U * (u16)1000U * (u16)1000U)
#define NVDDR_CLK_3 ((u16)66U * (u16)1000U * (u16)1000U)
#define NVDDR_CLK_4 ((u16)83U * (u16)1000U * (u16)1000U)
#define NVDDR_CLK_5 ((u16)100U * (u16)1000U * (u16)1000U)
//#define XNANDPS8_BBT_NO_OOB
/**
* The XNandPs8_Config structure contains configuration information for NAND
* controller.
*/
typedef struct {
u16 DeviceId; /**< Instance ID of NAND flash controller */
u32 BaseAddress; /**< Base address of NAND flash controller */
} XNandPs8_Config;
/**
* The XNandPs8_DataInterface enum contains flash operating mode.
*/
typedef enum {
SDR = 0U, /**< Single Data Rate */
NVDDR /**< Double Data Rate */
} XNandPs8_DataInterface;
/**
* XNandPs8_TimingMode enum contains timing modes.
*/
typedef enum {
SDR0 = 0U,
SDR1,
SDR2,
SDR3,
SDR4,
SDR5,
NVDDR0,
NVDDR1,
NVDDR2,
NVDDR3,
NVDDR4,
NVDDR5
} XNandPs8_TimingMode;
/**
* The XNandPs8_SWMode enum contains the driver operating mode.
*/
typedef enum {
POLLING = 0, /**< Polling */
INTERRUPT /**< Interrupt */
} XNandPs8_SWMode;
/**
* The XNandPs8_DmaMode enum contains the controller MDMA mode.
*/
typedef enum {
PIO = 0, /**< PIO Mode */
SDMA, /**< SDMA Mode */
MDMA /**< MDMA Mode */
} XNandPs8_DmaMode;
/**
* The XNandPs8_EccMode enum contains ECC functionality.
*/
typedef enum {
NONE = 0,
HWECC,
EZNAND,
ONDIE
} XNandPs8_EccMode;
typedef struct {
XNandPs8_DataInterface CurDataIntf;
XNandPs8_DataInterface NewDataIntf;
XNandPs8_TimingMode NewTimingMode;
u32 ClockFreq;
u32 FeatureVal;
} XNandPs8_TimingModeDesc;
/**
* Bad block table descriptor
*/
typedef struct {
u32 PageOffset[XNANDPS8_MAX_TARGETS];
/**< Page offset where BBT resides */
u32 SigOffset; /**< Signature offset in Spare area */
u32 VerOffset; /**< Offset of BBT version */
u32 SigLength; /**< Length of the signature */
u32 MaxBlocks; /**< Max blocks to search for BBT */
char Signature[4]; /**< BBT signature */
u8 Version[XNANDPS8_MAX_TARGETS];
/**< BBT version */
u32 Valid; /**< BBT descriptor is valid or not */
} XNandPs8_BbtDesc;
/**
* Bad block pattern
*/
typedef struct {
u32 Options; /**< Options to search the bad block pattern */
u32 Offset; /**< Offset to search for specified pattern */
u32 Length; /**< Number of bytes to check the pattern */
u8 Pattern[2]; /**< Pattern format to search for */
} XNandPs8_BadBlockPattern;
/**
* The XNandPs8_Geometry structure contains the ONFI geometry information.
*/
typedef struct {
/*
* Parameter page information
*/
u32 BytesPerPage; /**< Number of bytes per page */
u16 SpareBytesPerPage; /**< Number of spare bytes per page */
u32 PagesPerBlock; /**< Number of pages per block */
u32 BlocksPerLun; /**< Number of blocks per LUN */
u8 NumLuns; /**< Number of LUN's */
u8 RowAddrCycles; /**< Row address cycles */
u8 ColAddrCycles; /**< Column address cycles */
u8 NumBitsPerCell; /**< Number of bits per cell (Hamming/BCH) */
u8 NumBitsECC; /**< Number of bits ECC correctability */
u32 EccCodeWordSize; /**< ECC codeword size */
/*
* Driver specific information
*/
u32 BlockSize; /**< Block size */
u32 NumTargetPages; /**< Total number of pages in a Target */
u32 NumTargetBlocks; /**< Total number of blocks in a Target */
u64 TargetSize; /**< Target size in bytes */
u8 NumTargets; /**< Number of targets present */
u32 NumPages; /**< Total number of pages */
u32 NumBlocks; /**< Total number of blocks */
u64 DeviceSize; /**< Total flash size in bytes */
} XNandPs8_Geometry;
/**
* The XNandPs8_Features structure contains the ONFI features information.
*/
typedef struct {
u32 BusWidth;
u32 NvDdr;
u32 EzNand;
u32 OnDie;
u32 ExtPrmPage;
} XNandPs8_Features;
/**
* The XNandPs8_EccMatrix structure contains ECC features information.
*/
typedef struct {
u16 PageSize;
u16 CodeWordSize;
u8 NumEccBits;
u8 IsBCH;
u16 EccAddr;
u16 EccSize;
} XNandPs8_EccMatrix;
/**
* The XNandPs8_EccCfg structure contains ECC configuration.
*/
typedef struct {
u16 EccAddr;
u16 EccSize;
u16 CodeWordSize;
u8 NumEccBits;
u8 IsBCH;
} XNandPs8_EccCfg;
/**
* The XNandPs8 structure contains the driver instance data. The user is
* required to allocate a variable of this type for the NAND controller.
* A pointer to a variable of this type is then passed to the driver API
* functions.
*/
typedef struct {
u32 IsReady; /**< Device is initialized and ready */
XNandPs8_Config Config;
u8 BCH_Error_Status;
XNandPs8_DataInterface DataInterface;
XNandPs8_TimingMode TimingMode;
XNandPs8_SWMode Mode; /**< Driver operating mode */
XNandPs8_DmaMode DmaMode; /**< MDMA mode enabled/disabled */
XNandPs8_EccMode EccMode; /**< ECC Mode */
XNandPs8_EccCfg EccCfg; /**< ECC configuration */
XNandPs8_Geometry Geometry; /**< Flash geometry */
XNandPs8_Features Features; /**< ONFI features */
u8 PartialDataBuf[XNANDPS8_MAX_PAGE_SIZE] __attribute__ ((aligned(64)));
/**< Partial read/write buffer */
/* Bad block table definitions */
XNandPs8_BbtDesc BbtDesc; /**< Bad block table descriptor */
XNandPs8_BbtDesc BbtMirrorDesc; /**< Mirror BBT descriptor */
XNandPs8_BadBlockPattern BbPattern; /**< Bad block pattern to
search */
u8 Bbt[XNANDPS8_MAX_BLOCKS >> 2]; /**< Bad block table array */
} XNandPs8;
/******************* Macro Definitions (Inline Functions) *******************/
/*****************************************************************************/
/**
* This macro sets the bitmask in the register.
*
* @param InstancePtr is a pointer to the XNandPs8 instance of the
* controller.
* @param RegOffset is the register offset.
* @param BitMask is the bitmask.
*
* @note C-style signature:
* void XNandPs8_SetBits(XNandPs8 *InstancePtr, u32 RegOffset,
* u32 BitMask)
*
*****************************************************************************/
#define XNandPs8_SetBits(InstancePtr, RegOffset, BitMask) \
XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress, \
(RegOffset), \
((u32)(XNandPs8_ReadReg((InstancePtr)->Config.BaseAddress, \
(RegOffset)) | (BitMask))))
/*****************************************************************************/
/**
* This macro clears the bitmask in the register.
*
* @param InstancePtr is a pointer to the XNandPs8 instance of the
* controller.
* @param RegOffset is the register offset.
* @param BitMask is the bitmask.
*
* @note C-style signature:
* void XNandPs8_ClrBits(XNandPs8 *InstancePtr, u32 RegOffset,
* u32 BitMask)
*
*****************************************************************************/
#define XNandPs8_ClrBits(InstancePtr, RegOffset, BitMask) \
XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress, \
(RegOffset), \
((u32)(XNandPs8_ReadReg((InstancePtr)->Config.BaseAddress, \
(RegOffset)) & ~(BitMask))))
/*****************************************************************************/
/**
* This macro clears and updates the bitmask in the register.
*
* @param InstancePtr is a pointer to the XNandPs8 instance of the
* controller.
* @param RegOffset is the register offset.
* @param Mask is the bitmask.
* @param Value is the register value to write.
*
* @note C-style signature:
* void XNandPs8_ReadModifyWrite(XNandPs8 *InstancePtr,
* u32 RegOffset, u32 Mask, u32 Val)
*
*****************************************************************************/
#define XNandPs8_ReadModifyWrite(InstancePtr, RegOffset, Mask, Value) \
XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress, \
(RegOffset), \
((u32)((u32)(XNandPs8_ReadReg((InstancePtr)->Config.BaseAddress,\
(u32)(RegOffset)) & (u32)(~(Mask))) | (u32)(Value))))
/*****************************************************************************/
/**
* This macro enables bitmask in Interrupt Signal Enable register.
*
* @param InstancePtr is a pointer to the XNandPs8 instance of the
* controller.
* @param Mask is the bitmask.
*
* @note C-style signature:
* void XNandPs8_IntrSigEnable(XNandPs8 *InstancePtr, u32 Mask)
*
*****************************************************************************/
#define XNandPs8_IntrSigEnable(InstancePtr, Mask) \
XNandPs8_SetBits((InstancePtr), \
XNANDPS8_INTR_SIG_EN_OFFSET, \
(Mask))
/*****************************************************************************/
/**
* This macro clears bitmask in Interrupt Signal Enable register.
*
* @param InstancePtr is a pointer to the XNandPs8 instance of the
* controller.
* @param Mask is the bitmask.
*
* @note C-style signature:
* void XNandPs8_IntrSigClear(XNandPs8 *InstancePtr, u32 Mask)
*
*****************************************************************************/
#define XNandPs8_IntrSigClear(InstancePtr, Mask) \
XNandPs8_ClrBits((InstancePtr), \
XNANDPS8_INTR_SIG_EN_OFFSET, \
(Mask))
/*****************************************************************************/
/**
* This macro enables bitmask in Interrupt Status Enable register.
*
* @param InstancePtr is a pointer to the XNandPs8 instance of the
* controller.
* @param Mask is the bitmask.
*
* @note C-style signature:
* void XNandPs8_IntrStsEnable(XNandPs8 *InstancePtr, u32 Mask)
*
*****************************************************************************/
#define XNandPs8_IntrStsEnable(InstancePtr, Mask) \
XNandPs8_SetBits((InstancePtr), \
XNANDPS8_INTR_STS_EN_OFFSET, \
(Mask))
/************************** Function Prototypes *****************************/
s32 XNandPs8_CfgInitialize(XNandPs8 *InstancePtr, XNandPs8_Config *ConfigPtr,
u32 EffectiveAddr);
s32 XNandPs8_Erase(XNandPs8 *InstancePtr, u64 Offset, u64 Length);
s32 XNandPs8_Write(XNandPs8 *InstancePtr, u64 Offset, u64 Length,
u8 *SrcBuf);
s32 XNandPs8_Read(XNandPs8 *InstancePtr, u64 Offset, u64 Length,
u8 *DestBuf);
s32 XNandPs8_EraseBlock(XNandPs8 *InstancePtr, u32 Target, u32 Block);
s32 XNandPs8_WriteSpareBytes(XNandPs8 *InstancePtr, u32 Page, u8 *Buf);
s32 XNandPs8_ReadSpareBytes(XNandPs8 *InstancePtr, u32 Page, u8 *Buf);
s32 XNandPs8_ChangeTimingMode(XNandPs8 *InstancePtr,
XNandPs8_DataInterface NewIntf,
XNandPs8_TimingMode NewMode);
s32 XNandPs8_GetFeature(XNandPs8 *InstancePtr, u32 Target, u8 Feature,
u8 *Buf);
s32 XNandPs8_SetFeature(XNandPs8 *InstancePtr, u32 Target, u8 Feature,
u8 *Buf);
void XNandPs8_EnableDmaMode(XNandPs8 *InstancePtr);
void XNandPs8_DisableDmaMode(XNandPs8 *InstancePtr);
void XNandPs8_EnableEccMode(XNandPs8 *InstancePtr);
void XNandPs8_DisableEccMode(XNandPs8 *InstancePtr);
void XNandPs8_Prepare_Cmd(XNandPs8 *InstancePtr, u8 Cmd1, u8 Cmd2, u8 EccState,
u8 DmaMode, u8 AddrCycles);
/*
* XNandPs8_LookupConfig in xnandps8_sinit.c
*/
XNandPs8_Config *XNandPs8_LookupConfig(u16 DeviceID);
#ifdef __cplusplus
}
#endif
#endif /* XNANDPS8_H end of protection macro */

1051
XilinxProcessorIPLib/drivers/nandps8_v2_0/src/xnandps8_bbm.c Executable file
View file

File diff suppressed because it is too large Load diff

215
XilinxProcessorIPLib/drivers/nandps8_v2_0/src/xnandps8_bbm.h Executable file
View file

@ -0,0 +1,215 @@
/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
* and
* (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits,
* goodwill, or any type of loss or damage suffered as a result of any
* action brought by a third party) even if such damage or loss was
* reasonably foreseeable or Xilinx had been advised of the possibility
* of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail- safe, or for use
* in any application requiring fail-safe performance, such as life-support
* or safety devices or systems, Class III medical devices, nuclear
* facilities, applications related to the deployment of airbags, or any
* other applications that could lead to death, personal injury, or severe
* property or environmental damage (individually and collectively,
* "Critical Applications"). Customer assumes the sole risk and liability
* of any use of Xilinx products in Critical Applications, subject only to
* applicable laws and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART
* OF THIS FILE AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xnandps8_bbm.h
*
* This file implements the Bad Block Management(BBM) functionality. This is
* similar to the Bad Block Management which is a part of the MTD subsystem in
* Linux. The factory marked bad blocks are scanned initially and a Bad Block
* Table(BBT) is created in the memory. This table is also written to the flash
* so that upon reboot, the BBT is read back from the flash and loaded into the
* memory instead of scanning every time. The Bad Block Table(BBT) is written
* into one of the the last four blocks in the flash memory. The last four
* blocks are marked as Reserved so that user can't erase/program those blocks.
*
* There are two bad block tables, a primary table and a mirror table. The
* tables are versioned and incrementing version number is used to detect and
* recover from interrupted updates. Each table is stored in a separate block,
* beginning in the first page of that block. Only two blocks would be necessary
* in the absence of bad blocks within the last four; the range of four provides
* a little slack in case one or two of those blocks is bad. These blocks are
* marked as reserved and cannot be programmed by the user. A NAND Flash device
* with 3 or more factory bad blocks in the last 4 cannot be used. The bad block
* table signature is written into the spare data area of the pages containing
* bad block table so that upon rebooting the bad block table signature is
* searched and the bad block table is loaded into RAM. The signature is "Bbt0"
* for primary Bad Block Table and "1tbB" for Mirror Bad Block Table. The
* version offset follows the signature offset in the spare data area. The
* version number increments on every update to the bad block table and the
* version wraps at 0xff.
*
* Each block in the Bad Block Table(BBT) is represented by 2 bits.
* The two bits are encoded as follows in RAM BBT.
* 0'b00 -> Good Block
* 0'b01 -> Block is bad due to wear
* 0'b10 -> Reserved block
* 0'b11 -> Factory marked bad block
*
* While writing to the flash the two bits are encoded as follows.
* 0'b00 -> Factory marked bad block
* 0'b01 -> Reserved block
* 0'b10 -> Block is bad due to wear
* 0'b11 -> Good Block
*
* The user can check for the validity of the block using the API
* XNandPs8_IsBlockBad and take the action based on the return value. Also user
* can update the bad block table using XNandPs8_MarkBlockBad API.
*
* @note None
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- ---------- -----------------------------------------------
* 1.0 nm 05/06/2014 First release
* 2.0 sb 11/04/2014 Added support for writing BBT signature and version
* in page section by enabling XNANDPS8_BBT_NO_OOB.
* </pre>
*
******************************************************************************/
#ifndef XNANDPS8_BBM_H /* prevent circular inclusions */
#define XNANDPS8_BBM_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xnandps8.h"
/************************** Constant Definitions *****************************/
/*
* Block definitions for RAM based Bad Block Table (BBT)
*/
#define XNANDPS8_BLOCK_GOOD 0x0U /**< Block is good */
#define XNANDPS8_BLOCK_BAD 0x1U /**< Block is bad */
#define XNANDPS8_BLOCK_RESERVED 0x2U /**< Reserved block */
#define XNANDPS8_BLOCK_FACTORY_BAD 0x3U /**< Factory marked bad
block */
/*
* Block definitions for FLASH based Bad Block Table (BBT)
*/
#define XNANDPS8_FLASH_BLOCK_GOOD 0x3U /**< Block is good */
#define XNANDPS8_FLASH_BLOCK_BAD 0x2U /**< Block is bad */
#define XNANDPS8_FLASH_BLOCK_RESERVED 0x1U /**< Reserved block */
#define XNANDPS8_FLASH_BLOCK_FACTORY_BAD 0x0U /**< Factory marked bad
block */
#define XNANDPS8_BBT_SCAN_2ND_PAGE 0x00000001U /**< Scan the
second page
for bad block
information
*/
#define XNANDPS8_BBT_DESC_PAGE_OFFSET 0U /**< Page offset of Bad
Block Table Desc */
#define XNANDPS8_BBT_DESC_SIG_OFFSET 2U /**< Bad Block Table
signature offset */
#define XNANDPS8_BBT_DESC_VER_OFFSET 6U /**< Bad block Table
version offset */
#define XNANDPS8_BBT_DESC_SIG_LEN 4U /**< Bad block Table
signature length */
#define XNANDPS8_BBT_DESC_MAX_BLOCKS 64U /**< Bad block Table
max blocks */
#define XNANDPS8_BBT_BLOCK_SHIFT 2U /**< Block shift value
for a block in BBT */
#define XNANDPS8_BBT_ENTRY_NUM_BLOCKS 4U /**< Num of blocks in
one BBT entry */
#define XNANDPS8_BB_PATTERN_OFFSET_SMALL_PAGE 5U /**< Bad block pattern
offset in a page */
#define XNANDPS8_BB_PATTERN_LENGTH_SMALL_PAGE 1U /**< Bad block pattern
length */
#define XNANDPS8_BB_PATTERN_OFFSET_LARGE_PAGE 0U /**< Bad block pattern
offset in a large
page */
#define XNANDPS8_BB_PATTERN_LENGTH_LARGE_PAGE 2U /**< Bad block pattern
length */
#define XNANDPS8_BB_PATTERN 0xFFU /**< Bad block pattern
to search in a page
*/
#define XNANDPS8_BLOCK_TYPE_MASK 0x03U /**< Block type mask */
#define XNANDPS8_BLOCK_SHIFT_MASK 0x06U /**< Block shift mask
for a Bad Block Table
entry byte */
#define XNANDPS8_ONDIE_SIG_OFFSET 0x4U
#define XNANDPS8_ONDIE_VER_OFFSET 0x14U
#define XNANDPS8_BBT_VERSION_LENGTH 1U
#define XNANDPS8_BBT_SIG_LENGTH 4U
#define XNANDPS8_BBT_BUF_LENGTH ((XNANDPS8_MAX_BLOCKS >> \
XNANDPS8_BBT_BLOCK_SHIFT) + \
(XNANDPS8_BBT_DESC_SIG_OFFSET + \
XNANDPS8_BBT_SIG_LENGTH + \
XNANDPS8_BBT_VERSION_LENGTH))
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/****************************************************************************/
/**
*
* This macro returns the Block shift value corresponding to a Block.
*
* @param Block is the block number.
*
* @return Block shift value
*
* @note None.
*
*****************************************************************************/
#define XNandPs8_BbtBlockShift(Block) \
((u8)(((Block) * 2U) & XNANDPS8_BLOCK_SHIFT_MASK))
/************************** Variable Definitions *****************************/
/************************** Function Prototypes ******************************/
void XNandPs8_InitBbtDesc(XNandPs8 *InstancePtr);
s32 XNandPs8_ScanBbt(XNandPs8 *InstancePtr);
s32 XNandPs8_IsBlockBad(XNandPs8 *InstancePtr, u32 Block);
s32 XNandPs8_MarkBlockBad(XNandPs8 *InstancePtr, u32 Block);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

82
XilinxProcessorIPLib/drivers/nandps8_v2_0/src/xnandps8_g.c Executable file
View file

@ -0,0 +1,82 @@
/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
* and
* (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits,
* goodwill, or any type of loss or damage suffered as a result of any
* action brought by a third party) even if such damage or loss was
* reasonably foreseeable or Xilinx had been advised of the possibility
* of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail- safe, or for use
* in any application requiring fail-safe performance, such as life-support
* or safety devices or systems, Class III medical devices, nuclear
* facilities, applications related to the deployment of airbags, or any
* other applications that could lead to death, personal injury, or severe
* property or environmental damage (individually and collectively,
* "Critical Applications"). Customer assumes the sole risk and liability
* of any use of Xilinx products in Critical Applications, subject only to
* applicable laws and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART
* OF THIS FILE AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xnandps8_g.c
*
* This file contains a configuration table where each entry is a configuration
* structure for an XNandPs8 device in the system.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- ---------- -----------------------------------------------
* 1.0 nm 05/06/2014 First release
* 1.0 nm 06/02/2014 Changed the copyright to new copyright
* </pre>
*
******************************************************************************/
/***************************** Include Files ********************************/
#include "xparameters.h"
#include "xnandps8.h"
/************************** Constant Definitions ****************************/
/**************************** Type Definitions ******************************/
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Variable Definitions ****************************/
/**
* Each XNandPs8 device in the system has an entry in this table.
*/
XNandPs8_Config XNandPs8_ConfigTable[] = {
{
0U,
XPAR_XNANDPS8_0_BASEADDR
}
};

516
XilinxProcessorIPLib/drivers/nandps8_v2_0/src/xnandps8_hw.h Executable file
View file

@ -0,0 +1,516 @@
/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
* and
* (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits,
* goodwill, or any type of loss or damage suffered as a result of any
* action brought by a third party) even if such damage or loss was
* reasonably foreseeable or Xilinx had been advised of the possibility
* of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail- safe, or for use
* in any application requiring fail-safe performance, such as life-support
* or safety devices or systems, Class III medical devices, nuclear
* facilities, applications related to the deployment of airbags, or any
* other applications that could lead to death, personal injury, or severe
* property or environmental damage (individually and collectively,
* "Critical Applications"). Customer assumes the sole risk and liability
* of any use of Xilinx products in Critical Applications, subject only to
* applicable laws and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART
* OF THIS FILE AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xnandps8_hw.h
*
* This file contains identifiers and low-level macros/functions for the Arasan
* NAND flash controller driver.
*
* See xnandps8.h for more information.
*
* @note None
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- ---------- -----------------------------------------------
* 1.0 nm 05/06/2014 First Release
* 2.0 sb 11/04/2014 Changed XNANDPS8_ECC_SLC_MLC_MASK to
* XNANDPS8_ECC_HAMMING_BCH_MASK.
* </pre>
*
******************************************************************************/
#ifndef XNANDPS8_HW_H /* prevent circular inclusions */
#define XNANDPS8_HW_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_io.h"
/************************** Constant Definitions *****************************/
/************************** Register Offset Definitions **********************/
#define XNANDPS8_PKT_OFFSET 0x00U /**< Packet Register */
#define XNANDPS8_MEM_ADDR1_OFFSET 0x04U /**< Memory Address
Register 1 */
#define XNANDPS8_MEM_ADDR2_OFFSET 0x08U /**< Memory Address
Register 2 */
#define XNANDPS8_CMD_OFFSET 0x0CU /**< Command Register */
#define XNANDPS8_PROG_OFFSET 0x10U /**< Program Register */
#define XNANDPS8_INTR_STS_EN_OFFSET 0x14U /**< Interrupt Status
Enable Register */
#define XNANDPS8_INTR_SIG_EN_OFFSET 0x18U /**< Interrupt Signal
Enable Register */
#define XNANDPS8_INTR_STS_OFFSET 0x1CU /**< Interrupt Status
Register */
#define XNANDPS8_READY_BUSY_OFFSET 0x20U /**< Ready/Busy status
Register */
#define XNANDPS8_FLASH_STS_OFFSET 0x28U /**< Flash Status Register */
#define XNANDPS8_TIMING_OFFSET 0x2CU /**< Timing Register */
#define XNANDPS8_BUF_DATA_PORT_OFFSET 0x30U /**< Buffer Data Port
Register */
#define XNANDPS8_ECC_OFFSET 0x34U /**< ECC Register */
#define XNANDPS8_ECC_ERR_CNT_OFFSET 0x38U /**< ECC Error Count
Register */
#define XNANDPS8_ECC_SPR_CMD_OFFSET 0x3CU /**< ECC Spare Command
Register */
#define XNANDPS8_ECC_CNT_1BIT_OFFSET 0x40U /**< Error Count 1bit
Register */
#define XNANDPS8_ECC_CNT_2BIT_OFFSET 0x44U /**< Error Count 2bit
Register */
#define XNANDPS8_ECC_CNT_3BIT_OFFSET 0x48U /**< Error Count 3bit
Register */
#define XNANDPS8_ECC_CNT_4BIT_OFFSET 0x4CU /**< Error Count 4bit
Register */
#define XNANDPS8_CPU_REL_OFFSET 0x58U /**< CPU Release Register */
#define XNANDPS8_ECC_CNT_5BIT_OFFSET 0x5CU /**< Error Count 5bit
Register */
#define XNANDPS8_ECC_CNT_6BIT_OFFSET 0x60U /**< Error Count 6bit
Register */
#define XNANDPS8_ECC_CNT_7BIT_OFFSET 0x64U /**< Error Count 7bit
Register */
#define XNANDPS8_ECC_CNT_8BIT_OFFSET 0x68U /**< Error Count 8bit
Register */
#define XNANDPS8_DATA_INTF_OFFSET 0x6CU /**< Data Interface Register */
#define XNANDPS8_DMA_SYS_ADDR0_OFFSET 0x50U /**< DMA System Address 0
Register */
#define XNANDPS8_DMA_SYS_ADDR1_OFFSET 0x24U /**< DMA System Address 1
Register */
#define XNANDPS8_DMA_BUF_BND_OFFSET 0x54U /**< DMA Buffer Boundary
Register */
#define XNANDPS8_SLV_DMA_CONF_OFFSET 0x80U /**< Slave DMA Configuration
Register */
/** @name Packet Register bit definitions and masks
* @{
*/
#define XNANDPS8_PKT_PKT_SIZE_MASK 0x000007FFU /**< Packet Size */
#define XNANDPS8_PKT_PKT_CNT_MASK 0x00FFF000U /**< Packet Count*/
#define XNANDPS8_PKT_PKT_CNT_SHIFT 12U /**< Packet Count Shift */
/* @} */
/** @name Memory Address Register 1 bit definitions and masks
* @{
*/
#define XNANDPS8_MEM_ADDR1_COL_ADDR_MASK 0x0000FFFFU /**< Column Address
Mask */
#define XNANDPS8_MEM_ADDR1_PG_ADDR_MASK 0xFFFF0000U /**< Page, Block
Address Mask */
#define XNANDPS8_MEM_ADDR1_PG_ADDR_SHIFT 16U /**< Page Shift */
/* @} */
/** @name Memory Address Register 2 bit definitions and masks
* @{
*/
#define XNANDPS8_MEM_ADDR2_MEM_ADDR_MASK 0x000000FFU /**< Memory Address
*/
#define XNANDPS8_MEM_ADDR2_BUS_WIDTH_MASK 0x01000000U /**< Bus Width */
#define XNANDPS8_MEM_ADDR2_NFC_BCH_MODE_MASK 0x0E000000U /**< BCH Mode
Value */
#define XNANDPS8_MEM_ADDR2_MODE_MASK 0x30000000U /**< Flash
Connection Mode */
#define XNANDPS8_MEM_ADDR2_CHIP_SEL_MASK 0xC0000000U /**< Chip Select */
#define XNANDPS8_MEM_ADDR2_CHIP_SEL_SHIFT 30U /**< Chip select
shift */
#define XNANDPS8_MEM_ADDR2_BUS_WIDTH_SHIFT 24U /**< Bus width shift */
#define XNANDPS8_MEM_ADDR2_NFC_BCH_MODE_SHIFT 25U
/* @} */
/** @name Command Register bit definitions and masks
* @{
*/
#define XNANDPS8_CMD_CMD1_MASK 0x000000FFU /**< 1st Cycle
Command */
#define XNANDPS8_CMD_CMD2_MASK 0x0000FF00U /**< 2nd Cycle
Command */
#define XNANDPS8_CMD_PG_SIZE_MASK 0x03800000U /**< Page Size */
#define XNANDPS8_CMD_DMA_EN_MASK 0x0C000000U /**< DMA Enable
Mode */
#define XNANDPS8_CMD_ADDR_CYCLES_MASK 0x70000000U /**< Number of
Address Cycles */
#define XNANDPS8_CMD_ECC_ON_MASK 0x80000000U /**< ECC ON/OFF */
#define XNANDPS8_CMD_CMD2_SHIFT 8U /**< 2nd Cycle Command
Shift */
#define XNANDPS8_CMD_PG_SIZE_SHIFT 23U /**< Page Size Shift */
#define XNANDPS8_CMD_DMA_EN_SHIFT 26U /**< DMA Enable Shift */
#define XNANDPS8_CMD_ADDR_CYCLES_SHIFT 28U /**< Number of Address
Cycles Shift */
#define XNANDPS8_CMD_ECC_ON_SHIFT 31U /**< ECC ON/OFF */
/* @} */
/** @name Program Register bit definitions and masks
* @{
*/
#define XNANDPS8_PROG_RD_MASK 0x00000001U /**< Read */
#define XNANDPS8_PROG_MUL_DIE_MASK 0x00000002U /**< Multi Die */
#define XNANDPS8_PROG_BLK_ERASE_MASK 0x00000004U /**< Block Erase */
#define XNANDPS8_PROG_RD_STS_MASK 0x00000008U /**< Read Status */
#define XNANDPS8_PROG_PG_PROG_MASK 0x00000010U /**< Page Program */
#define XNANDPS8_PROG_MUL_DIE_RD_MASK 0x00000020U /**< Multi Die Rd */
#define XNANDPS8_PROG_RD_ID_MASK 0x00000040U /**< Read ID */
#define XNANDPS8_PROG_RD_PRM_PG_MASK 0x00000080U /**< Read Param
Page */
#define XNANDPS8_PROG_RST_MASK 0x00000100U /**< Reset */
#define XNANDPS8_PROG_GET_FEATURES_MASK 0x00000200U /**< Get Features */
#define XNANDPS8_PROG_SET_FEATURES_MASK 0x00000400U /**< Set Features */
#define XNANDPS8_PROG_RD_UNQ_ID_MASK 0x00000800U /**< Read Unique
ID */
#define XNANDPS8_PROG_RD_STS_ENH_MASK 0x00001000U /**< Read Status
Enhanced */
#define XNANDPS8_PROG_RD_INTRLVD_MASK 0x00002000U /**< Read
Interleaved */
#define XNANDPS8_PROG_CHNG_RD_COL_ENH_MASK 0x00004000U /**< Change Read
Column
Enhanced */
#define XNANDPS8_PROG_COPY_BACK_INTRLVD_MASK 0x00008000U /**< Copy Back
Interleaved */
#define XNANDPS8_PROG_RD_CACHE_START_MASK 0x00010000U /**< Read Cache
Start */
#define XNANDPS8_PROG_RD_CACHE_SEQ_MASK 0x00020000U /**< Read Cache
Sequential */
#define XNANDPS8_PROG_RD_CACHE_RAND_MASK 0x00040000U /**< Read Cache
Random */
#define XNANDPS8_PROG_RD_CACHE_END_MASK 0x00080000U /**< Read Cache
End */
#define XNANDPS8_PROG_SMALL_DATA_MOVE_MASK 0x00100000U /**< Small Data
Move */
#define XNANDPS8_PROG_CHNG_ROW_ADDR_MASK 0x00200000U /**< Change Row
Address */
#define XNANDPS8_PROG_CHNG_ROW_ADDR_END_MASK 0x00400000U /**< Change Row
Address End */
#define XNANDPS8_PROG_RST_LUN_MASK 0x00800000U /**< Reset LUN */
#define XNANDPS8_PROG_PGM_PG_CLR_MASK 0x01000000U /**< Enhanced
Program Page
Register Clear */
#define XNANDPS8_PROG_VOL_SEL_MASK 0x02000000U /**< Volume Select */
#define XNANDPS8_PROG_ODT_CONF_MASK 0x04000000U /**< ODT Configure */
/* @} */
/** @name Interrupt Status Enable Register bit definitions and masks
* @{
*/
#define XNANDPS8_INTR_STS_EN_BUFF_WR_RDY_STS_EN_MASK 0x00000001U /**< Buffer
Write Ready
Status
Enable */
#define XNANDPS8_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK 0x00000002U /**< Buffer
Read Ready
Status
Enable */
#define XNANDPS8_INTR_STS_EN_TRANS_COMP_STS_EN_MASK 0x00000004U /**< Transfer
Complete
Status
Enable */
#define XNANDPS8_INTR_STS_EN_MUL_BIT_ERR_STS_EN_MASK 0x00000008U /**< Multi
Bit Error
Status
Enable */
#define XNANDPS8_INTR_STS_EN_ERR_INTR_STS_EN_MASK 0x00000010U /**< Single
Bit Error
Status
Enable,
BCH Detect
Error
Status
Enable */
#define XNANDPS8_INTR_STS_EN_DMA_INT_STS_EN_MASK 0x00000040U /**< DMA
Status
Enable */
#define XNANDPS8_INTR_STS_EN_ERR_AHB_STS_EN_MASK 0x00000080U /**< Error
AHB Status
Enable */
/* @} */
/** @name Interrupt Signal Enable Register bit definitions and masks
* @{
*/
#define XNANDPS8_INTR_SIG_EN_BUFF_WR_RDY_STS_EN_MASK 0x00000001U /**< Buffer
Write Ready
Signal
Enable */
#define XNANDPS8_INTR_SIG_EN_BUFF_RD_RDY_STS_EN_MASK 0x00000002U /**< Buffer
Read Ready
Signal
Enable */
#define XNANDPS8_INTR_SIG_EN_TRANS_COMP_STS_EN_MASK 0x00000004U /**< Transfer
Complete
Signal
Enable */
#define XNANDPS8_INTR_SIG_EN_MUL_BIT_ERR_STS_EN_MASK 0x00000008U /**< Multi
Bit Error
Signal
Enable */
#define XNANDPS8_INTR_SIG_EN_ERR_INTR_STS_EN_MASK 0x00000010U /**< Single
Bit Error
Signal
Enable,
BCH Detect
Error
Signal
Enable */
#define XNANDPS8_INTR_SIG_EN_DMA_INT_STS_EN_MASK 0x00000040U /**< DMA
Signal
Enable */
#define XNANDPS8_INTR_SIG_EN_ERR_AHB_STS_EN_MASK 0x00000080U /**< Error
AHB Signal
Enable */
/* @} */
/** @name Interrupt Status Register bit definitions and masks
* @{
*/
#define XNANDPS8_INTR_STS_BUFF_WR_RDY_STS_EN_MASK 0x00000001U /**< Buffer
Write
Ready */
#define XNANDPS8_INTR_STS_BUFF_RD_RDY_STS_EN_MASK 0x00000002U /**< Buffer
Read
Ready */
#define XNANDPS8_INTR_STS_TRANS_COMP_STS_EN_MASK 0x00000004U /**< Transfer
Complete */
#define XNANDPS8_INTR_STS_MUL_BIT_ERR_STS_EN_MASK 0x00000008U /**< Multi
Bit Error */
#define XNANDPS8_INTR_STS_ERR_INTR_STS_EN_MASK 0x00000010U /**< Single
Bit Error,
BCH Detect
Error */
#define XNANDPS8_INTR_STS_DMA_INT_STS_EN_MASK 0x00000040U /**< DMA
Interrupt
*/
#define XNANDPS8_INTR_STS_ERR_AHB_STS_EN_MASK 0x00000080U /**< Error
AHB */
/* @} */
/** @name Interrupt bit definitions and masks
* @{
*/
#define XNANDPS8_INTR_BUFF_WR_RDY_STS_EN_MASK 0x00000001U /**< Buffer Write
Ready Status
Enable */
#define XNANDPS8_INTR_BUFF_RD_RDY_STS_EN_MASK 0x00000002U /**< Buffer Read
Ready Status
Enable */
#define XNANDPS8_INTR_TRANS_COMP_STS_EN_MASK 0x00000004U /**< Transfer
Complete Status
Enable */
#define XNANDPS8_INTR_MUL_BIT_ERR_STS_EN_MASK 0x00000008U /**< Multi Bit Error
Status Enable */
#define XNANDPS8_INTR_ERR_INTR_STS_EN_MASK 0x00000010U /**< Single Bit Error
Status Enable,
BCH Detect Error
Status Enable */
#define XNANDPS8_INTR_DMA_INT_STS_EN_MASK 0x00000040U /**< DMA Status
Enable */
#define XNANDPS8_INTR_ERR_AHB_STS_EN_MASK 0x00000080U /**< Error AHB Status
Enable */
/* @} */
/** @name ID2 Register bit definitions and masks
* @{
*/
#define XNANDPS8_ID2_DEVICE_ID2_MASK 0x000000FFU /**< MSB Device ID */
/* @} */
/** @name Flash Status Register bit definitions and masks
* @{
*/
#define XNANDPS8_FLASH_STS_FLASH_STS_MASK 0x0000FFFFU /**< Flash Status
Value */
/* @} */
/** @name Timing Register bit definitions and masks
* @{
*/
#define XNANDPS8_TIMING_TCCS_TIME_MASK 0x00000003U /**< Change column
setup time */
#define XNANDPS8_TIMING_SLOW_FAST_TCAD_MASK 0x00000004U /**< Slow/Fast device
*/
#define XNANDPS8_TIMING_DQS_BUFF_SEL_MASK 0x00000078U /**< Write/Read data
transaction value
*/
#define XNANDPS8_TIMING_TADL_TIME_MASK 0x00007F80U /**< Address latch
enable to Data
loading time */
/* @} */
/** @name ECC Register bit definitions and masks
* @{
*/
#define XNANDPS8_ECC_ADDR_MASK 0x0000FFFFU /**< ECC address */
#define XNANDPS8_ECC_SIZE_MASK 0x01FF0000U /**< ECC size */
#define XNANDPS8_ECC_HAMMING_BCH_MASK 0x02000000U /**< Hamming/BCH
support */
/* @} */
/** @name ECC Error Count Register bit definitions and masks
* @{
*/
#define XNANDPS8_ECC_ERR_CNT_PKT_BND_ERR_CNT_MASK 0x000000FFU /**< Packet
bound error
count */
#define XNANDPS8_ECC_ERR_CNT_PG_BND_ERR_CNT_MASK 0x0000FF00U /**< Page
bound error
count */
/* @} */
/** @name ECC Spare Command Register bit definitions and masks
* @{
*/
#define XNANDPS8_ECC_SPR_CMD_SPR_CMD_MASK 0x000000FFU /**< ECC
spare
command */
#define XNANDPS8_ECC_SPR_CMD_ECC_ADDR_CYCLES_MASK 0x70000000U /**< Number
of ECC/
spare
address
cycles */
/* @} */
/** @name Data Interface Register bit definitions and masks
* @{
*/
#define XNANDPS8_DATA_INTF_SDR_MASK 0x00000007U /**< SDR mode */
#define XNANDPS8_DATA_INTF_NVDDR_MASK 0x00000038U /**< NVDDR mode */
#define XNANDPS8_DATA_INTF_NVDDR2_MASK 0x000001C0U /**< NVDDR2 mode */
#define XNANDPS8_DATA_INTF_DATA_INTF_MASK 0x00000600U /**< Data
Interface */
#define XNANDPS8_DATA_INTF_NVDDR_SHIFT 3U /**< NVDDR mode shift */
#define XNANDPS8_DATA_INTF_DATA_INTF_SHIFT 9U /**< Data Interface Shift */
/* @} */
/** @name DMA Buffer Boundary Register bit definitions and masks
* @{
*/
#define XNANDPS8_DMA_BUF_BND_BND_MASK 0x00000007U /**< DMA buffer
boundary */
#define XNANDPS8_DMA_BUF_BND_4K 0x0U
#define XNANDPS8_DMA_BUF_BND_8K 0x1U
#define XNANDPS8_DMA_BUF_BND_16K 0x2U
#define XNANDPS8_DMA_BUF_BND_32K 0x3U
#define XNANDPS8_DMA_BUF_BND_64K 0x4U
#define XNANDPS8_DMA_BUF_BND_128K 0x5U
#define XNANDPS8_DMA_BUF_BND_256K 0x6U
#define XNANDPS8_DMA_BUF_BND_512K 0x7U
/* @} */
/** @name Slave DMA Configuration Register bit definitions and masks
* @{
*/
#define XNANDPS8_SLV_DMA_CONF_SDMA_TX_RX_MASK 0x00000001U /**< Slave
DMA
Transfer
Direction
*/
#define XNANDPS8_SLV_DMA_CONF_DMA_TRANS_CNT_MASK 0x001FFFFEU /**< Slave
DMA
Transfer
Count */
#define XNANDPS8_SLV_DMA_CONF_DMA_BURST_SIZE_MASK 0x00E00000U /**< Slave
DMA
Burst
Size */
#define XNANDPS8_SLV_DMA_CONF_DMA_TMOUT_CNT_VAL_MASK 0x0F000000U /**< DMA
Timeout
Counter
Value */
#define XNANDPS8_SLV_DMA_CONF_SDMA_EN_MASK 0x10000000U /**< Slave
DMA
Enable */
/* @} */
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/****************************************************************************/
/**
*
* This macro reads the given register.
*
* @param BaseAddress is the base address of controller registers.
* @param RegOffset is the register offset to be read.
*
* @return The 32-bit value of the register.
*
* @note C-style signature:
* u32 XNandPs8_ReadReg(u32 BaseAddress, u32 RegOffset)
*
*****************************************************************************/
#define XNandPs8_ReadReg(BaseAddress, RegOffset) \
Xil_In32((BaseAddress) + (RegOffset))
/****************************************************************************/
/**
*
* This macro writes the given register.
*
* @param BaseAddress is the the base address of controller registers.
* @param RegOffset is the register offset to be written.
* @param Data is the the 32-bit value to write to the register.
*
* @return None.
*
* @note C-style signature:
* void XNandPs8_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
*
******************************************************************************/
#define XNandPs8_WriteReg(BaseAddress, RegOffset, Data) \
Xil_Out32(((BaseAddress) + (RegOffset)), (Data))
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
#ifdef __cplusplus
}
#endif
#endif /* XNANDPS8_HW_H end of protection macro */

124
XilinxProcessorIPLib/drivers/nandps8_v2_0/src/xnandps8_onfi.c Executable file
View file

@ -0,0 +1,124 @@
/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
* and
* (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits,
* goodwill, or any type of loss or damage suffered as a result of any
* action brought by a third party) even if such damage or loss was
* reasonably foreseeable or Xilinx had been advised of the possibility
* of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail- safe, or for use
* in any application requiring fail-safe performance, such as life-support
* or safety devices or systems, Class III medical devices, nuclear
* facilities, applications related to the deployment of airbags, or any
* other applications that could lead to death, personal injury, or severe
* property or environmental damage (individually and collectively,
* "Critical Applications"). Customer assumes the sole risk and liability
* of any use of Xilinx products in Critical Applications, subject only to
* applicable laws and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART
* OF THIS FILE AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xnandps8_onfi.c
*
* This file contains the implementation of ONFI specific functions.
*
* @note None
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- ---------- -----------------------------------------------
* 1.0 nm 05/06/2014 First release
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xnandps8_onfi.h"
#include "xnandps8.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/*****************************************************************************/
/**
*
* This function calculates ONFI paramater page CRC.
*
* @param Parambuf is a pointer to the ONFI paramater page buffer.
* @param StartOff is the starting offset in buffer to calculate CRC.
* @param Length is the number of bytes for which CRC is calculated.
*
* @return
* CRC value.
* @note
* None.
*
******************************************************************************/
u32 XNandPs8_OnfiParamPageCrc(u8 *ParamBuf, u32 StartOff, u32 Length)
{
const u32 CrcInit = 0x4F4EU;
const u32 Order = 16U;
const u32 Polynom = 0x8005U;
u32 i, j, c, Bit;
u32 Crc = CrcInit;
u32 DataIn;
u32 DataByteCount = 0U;
u32 CrcMask, CrcHighBit;
CrcMask = ((u32)(((u32)1 << (Order - (u32)1)) -(u32)1) << (u32)1) | (u32)1;
CrcHighBit = (u32)((u32)1 << (Order - (u32)1));
/*
* CRC covers the data bytes between byte 0 and byte 253
* (ONFI 1.0, section 5.4.1.36)
*/
for(i = StartOff; i < Length; i++) {
DataIn = ParamBuf[i];
c = (u32)DataIn;
DataByteCount++;
for(j = 0x80U; j; j >>= 1U) {
Bit = Crc & CrcHighBit;
Crc <<= 1U;
if ((c & j) != 0U) {
Bit ^= CrcHighBit;
}
if (Bit != 0U) {
Crc ^= Polynom;
}
}
Crc &= CrcMask;
}
return Crc;
}

352
XilinxProcessorIPLib/drivers/nandps8_v2_0/src/xnandps8_onfi.h Executable file
View file

@ -0,0 +1,352 @@
/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
* and
* (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits,
* goodwill, or any type of loss or damage suffered as a result of any
* action brought by a third party) even if such damage or loss was
* reasonably foreseeable or Xilinx had been advised of the possibility
* of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail- safe, or for use
* in any application requiring fail-safe performance, such as life-support
* or safety devices or systems, Class III medical devices, nuclear
* facilities, applications related to the deployment of airbags, or any
* other applications that could lead to death, personal injury, or severe
* property or environmental damage (individually and collectively,
* "Critical Applications"). Customer assumes the sole risk and liability
* of any use of Xilinx products in Critical Applications, subject only to
* applicable laws and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART
* OF THIS FILE AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xnandps8_onfi.h
*
* This file defines all the ONFI 3.1 specific commands and values.
*
* @note None
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- ---------- -----------------------------------------------
* 1.0 nm 05/06/2014 First release
* </pre>
*
******************************************************************************/
#ifndef XNANDPS8_ONFI_H /* prevent circular inclusions */
#define XNANDPS8_ONFI_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
/************************** Constant Definitions *****************************/
/*
* Standard ONFI 3.1 Commands
*/
/*
* ONFI 3.1 Mandatory Commands
*/
#define ONFI_CMD_RD1 0x00U /**< Read (1st cycle) */
#define ONFI_CMD_RD2 0x30U /**< Read (2nd cycle) */
#define ONFI_CMD_CHNG_RD_COL1 0x05U /**< Change Read Column
(1st cycle) */
#define ONFI_CMD_CHNG_RD_COL2 0xE0U /**< Change Read Column
(2nd cycle) */
#define ONFI_CMD_BLK_ERASE1 0x60U /**< Block Erase (1st cycle) */
#define ONFI_CMD_BLK_ERASE2 0xD0U /**< Block Erase (2nd cycle) */
#define ONFI_CMD_RD_STS 0x70U /**< Read Status */
#define ONFI_CMD_PG_PROG1 0x80U /**< Page Program(1st cycle) */
#define ONFI_CMD_PG_PROG2 0x10U /**< Page Program(2nd cycle) */
#define ONFI_CMD_CHNG_WR_COL 0x85U /**< Change Write Column */
#define ONFI_CMD_RD_ID 0x90U /**< Read ID */
#define ONFI_CMD_RD_PRM_PG 0xECU /**< Read Parameter Page */
#define ONFI_CMD_RST 0xFFU /**< Reset */
/*
* ONFI 3.1 Optional Commands
*/
#define ONFI_CMD_MUL_RD1 0x00U /**< Multiplane Read
(1st cycle) */
#define ONFI_CMD_MUL_RD2 0x32U /**< Multiplane Read
(2nd cycle) */
#define ONFI_CMD_CPBK_RD1 0x00U /**< Copyback Read
(1st cycle) */
#define ONFI_CMD_CPBK_RD2 0x35U /**< Copyback Read
(2nd cycle) */
#define ONFI_CMD_CHNG_RD_COL_ENHCD1 0x06U /**< Change Read Column
Enhanced (1st cycle) */
#define ONFI_CMD_CHNG_RD_COL_ENHCD2 0xE0U /**< Change Read Column
Enhanced (2nd cycle) */
#define ONFI_CMD_RD_CACHE_RND1 0x00U /**< Read Cache Random
(1st cycle) */
#define ONFI_CMD_RD_CACHE_RND2 0x31U /**< Read Cache Random
(2nd cycle) */
#define ONFI_CMD_RD_CACHE_SEQ 0x31U /**< Read Cache Sequential */
#define ONFI_CMD_RD_CACHE_END 0x3FU /**< Read Cache End */
#define ONFI_CMD_MUL_BLK_ERASE1 0x60U /**< Multiplane Block Erase
(1st cycle) */
#define ONFI_CMD_MUL_BLK_ERASE2 0xD1U /**< Multiplane Block Erase
(2nd cycle) */
#define ONFI_CMD_RD_STS_ENHCD 0x78U /**< Read Status Enhanced */
#define ONFI_CMD_BLK_ERASE_INTRLVD2 0xD1U /**< Block Erase Interleaved
(2nd cycle) */
#define ONFI_CMD_MUL_PG_PROG1 0x80U /**< Multiplane Page Program
(1st cycle) */
#define ONFI_CMD_MUL_PG_PROG2 0x11U /**< Multiplane Page Program
(2nd cycle) */
#define ONFI_CMD_PG_CACHE_PROG1 0x80U /**< Page Cache Program
(1st cycle) */
#define ONFI_CMD_PG_CACHE_PROG2 0x15U /**< Page Cache Program
(2nd cycle) */
#define ONFI_CMD_CPBK_PROG1 0x85U /**< Copyback Program
(1st cycle) */
#define ONFI_CMD_CPBK_PROG2 0x10U /**< Copyback Program
(2nd cycle) */
#define ONFI_CMD_MUL_CPBK_PROG1 0x85U /**< Multiplane Copyback
Program (1st cycle) */
#define ONFI_CMD_MUL_CPBK_PROG2 0x10U /**< Multiplane Copyback
Program (2nd cycle) */
#define ONFI_CMD_SMALL_DATA_MV1 0x85U /**< Small Data Move
(1st cycle) */
#define ONFI_CMD_SMALL_DATA_MV2 0x10U /**< Small Data Move
(2nd cycle) */
#define ONFI_CMD_CHNG_ROW_ADDR 0x85U /**< Change Row Address */
#define ONFI_CMD_VOL_SEL 0xE1U /**< Volume Select */
#define ONFI_CMD_ODT_CONF 0xE2U /**< ODT Configure */
#define ONFI_CMD_RD_UNIQID 0xEDU /**< Read Unique ID */
#define ONFI_CMD_GET_FEATURES 0xEEU /**< Get Features */
#define ONFI_CMD_SET_FEATURES 0xEFU /**< Set Features */
#define ONFI_CMD_LUN_GET_FEATURES 0xD4U /**< LUN Get Features */
#define ONFI_CMD_LUN_SET_FEATURES 0xD5U /**< LUN Set Features */
#define ONFI_CMD_RST_LUN 0xFAU /**< Reset LUN */
#define ONFI_CMD_SYN_RST 0xFCU /**< Synchronous Reset */
/*
* ONFI Status Register bit offsets
*/
#define ONFI_STS_FAIL 0x01U /**< FAIL */
#define ONFI_STS_FAILC 0x02U /**< FAILC */
#define ONFI_STS_CSP 0x08U /**< CSP */
#define ONFI_STS_VSP 0x10U /**< VSP */
#define ONFI_STS_ARDY 0x20U /**< ARDY */
#define ONFI_STS_RDY 0x40U /**< RDY */
#define ONFI_STS_WP 0x80U /**< WP_n */
/*
* ONFI constants
*/
#define ONFI_CRC_LEN 254U /**< ONFI CRC Buf Length */
#define ONFI_PRM_PG_LEN 256U /**< Parameter Page Length */
#define ONFI_MND_PRM_PGS 3U /**< Number of mandatory
parameter pages */
#define ONFI_SIG_LEN 4U /**< Signature Length */
#define ONFI_CMD_INVALID 0x00U /**< Invalid Command */
#define ONFI_READ_ID_LEN 4U /**< ONFI ID length */
#define ONFI_READ_ID_ADDR 0x20U /**< ONFI Read ID Address */
#define ONFI_READ_ID_ADDR_CYCLES 1U /**< ONFI Read ID Address
cycles */
#define ONFI_PRM_PG_ADDR_CYCLES 1U /**< ONFI Read Parameter page
address cycles */
/**
* This enum defines the ONFI 3.1 commands.
*/
enum OnfiCommandList {
READ=0, /**< Read */
MULTIPLANE_READ, /**< Multiplane Read */
COPYBACK_READ, /**< Copyback Read */
CHANGE_READ_COLUMN, /**< Change Read Column */
CHANGE_READ_COLUMN_ENHANCED, /**< Change Read Column Enhanced */
READ_CACHE_RANDOM, /**< Read Cache Random */
READ_CACHE_SEQUENTIAL, /**< Read Cache Sequential */
READ_CACHE_END, /**< Read Cache End */
BLOCK_ERASE, /**< Block Erase */
MULTIPLANE_BLOCK_ERASE, /**< Multiplane Block Erase */
READ_STATUS, /**< Read Status */
READ_STATUS_ENHANCED, /**< Read Status Enhanced */
PAGE_PROGRAM, /**< Page Program */
MULTIPLANE_PAGE_PROGRAM, /**< Multiplane Page Program */
PAGE_CACHE_PROGRAM, /**< Page Cache Program */
COPYBACK_PROGRAM, /**< Copyback Program */
MULTIPLANE_COPYBACK_PROGRAM, /**< Multiplance Copyback Program */
SMALL_DATA_MOVE, /**< Small Data Move */
CHANGE_WRITE_COLUMN, /**< Change Write Column */
CHANGE_ROW_ADDR, /**< Change Row Address */
READ_ID, /**< Read ID */
VOLUME_SELECT, /**< Volume Select */
ODT_CONFIGURE, /**< ODT Configure */
READ_PARAM_PAGE, /**< Read Parameter Page */
READ_UNIQUE_ID, /**< Read Unique ID */
GET_FEATURES, /**< Get Features */
SET_FEATURES, /**< Set Features */
LUN_GET_FEATURES, /**< LUN Get Features */
LUN_SET_FEATURES, /**< LUN Set Features */
RESET_LUN, /**< Reset LUN */
SYN_RESET, /**< Synchronous Reset */
RESET, /**< Reset */
MAX_CMDS /**< Dummy Command */
};
/**************************** Type Definitions *******************************/
/*
* Parameter page structure of ONFI 3.1 specification.
*/
typedef struct {
/*
* Revision information and features block
*/
u8 Signature[4]; /**< Parameter page signature */
u16 Revision; /**< Revision Number */
u16 Features; /**< Features supported */
u16 OptionalCmds; /**< Optional commands supported */
u8 JedecJtgPrmAdvCmd; /**< ONFI JEDEC JTG primary advanced
command support */
u8 Reserved0; /**< Reserved (11) */
u16 ExtParamPageLen; /**< Extended Parameter Page Length */
u8 NumOfParamPages; /**< Number of Parameter Pages */
u8 Reserved1[17]; /**< Reserved (15-31) */
/*
* Manufacturer information block
*/
u8 DeviceManufacturer[12]; /**< Device manufacturer */
u8 DeviceModel[20]; /**< Device model */
u8 JedecManufacturerId; /**< JEDEC Manufacturer ID */
u8 DateCode[2]; /**< Date code */
u8 Reserved2[13]; /**< Reserved (67-79) */
/*
* Memory organization block
*/
u32 BytesPerPage; /**< Number of data bytes per page */
u16 SpareBytesPerPage; /**< Number of spare bytes per page */
u32 BytesPerPartialPage; /**< Number of data bytes per
partial page */
u16 SpareBytesPerPartialPage; /**< Number of spare bytes per
partial page */
u32 PagesPerBlock; /**< Number of pages per block */
u32 BlocksPerLun; /**< Number of blocks per LUN */
u8 NumLuns; /**< Number of LUN's */
u8 AddrCycles; /**< Number of address cycles */
u8 BitsPerCell; /**< Number of bits per cell */
u16 MaxBadBlocksPerLun; /**< Bad blocks maximum per LUN */
u16 BlockEndurance; /**< Block endurance */
u8 GuaranteedValidBlock; /**< Guaranteed valid blocks at
beginning of target */
u16 BlockEnduranceGVB; /**< Block endurance for guaranteed
valid block */
u8 ProgramsPerPage; /**< Number of programs per page */
u8 PartialProgAttr; /**< Partial programming attributes */
u8 EccBits; /**< Number of bits ECC
correctability */
u8 PlaneAddrBits; /**< Number of plane address bits */
u8 PlaneOperationAttr; /**< Multi-plane operation
attributes */
u8 EzNandSupport; /**< EZ NAND support */
u8 Reserved3[12]; /**< Reserved (116 - 127) */
/*
* Electrical parameters block
*/
u8 IOPinCapacitance; /**< I/O pin capacitance, maximum */
u16 SDRTimingMode; /**< SDR Timing mode support */
u16 SDRPagecacheTimingMode; /**< SDR Program cache timing mode */
u16 TProg; /**< Maximum page program time */
u16 TBers; /**< Maximum block erase time */
u16 TR; /**< Maximum page read time */
u16 TCcs; /**< Maximum change column setup
time */
u8 NVDDRTimingMode; /**< NVDDR timing mode support */
u8 NVDDR2TimingMode; /**< NVDDR2 timing mode support */
u8 SynFeatures; /**< NVDDR/NVDDR2 features */
u16 ClkInputPinCap; /**< CLK input pin capacitance */
u16 IOPinCap; /**< I/O pin capacitance */
u16 InputPinCap; /**< Input pin capacitance typical */
u8 InputPinCapMax; /**< Input pin capacitance maximum */
u8 DrvStrength; /**< Driver strength support */
u16 TMr; /**< Maximum multi-plane read time */
u16 TAdl; /**< Program page register clear
enhancement value */
u16 TEr; /**< Typical page read time for
EZ NAND */
u8 NVDDR2Features; /**< NVDDR2 Features */
u8 NVDDR2WarmupCycles; /**< NVDDR2 Warmup Cycles */
u8 Reserved4[4]; /**< Reserved (160 - 163) */
/*
* Vendor block
*/
u16 VendorRevisionNum; /**< Vendor specific revision number */
u8 VendorSpecific[88]; /**< Vendor specific */
u16 Crc; /**< Integrity CRC */
}__attribute__((packed))OnfiParamPage;
/*
* ONFI extended parameter page structure.
*/
typedef struct {
u16 Crc;
u8 Sig[4];
u8 Reserved1[10];
u8 Section0Type;
u8 Section0Len;
u8 Section1Type;
u8 Section1Len;
u8 ResSection[12];
u8 SectionData[256];
}__attribute__((packed))OnfiExtPrmPage;
/*
* Driver extended parameter page information.
*/
typedef struct {
u8 NumBitsEcc;
u8 CodeWordSize;
u16 MaxBadBlocks;
u16 BlockEndurance;
u16 Reserved;
}__attribute__((packed))OnfiExtEccBlock;
typedef struct {
u8 Command1; /**< Command Cycle 1 */
u8 Command2; /**< Command Cycle 2 */
} OnfiCmdFormat;
extern const OnfiCmdFormat OnfiCmd[MAX_CMDS];
/************************** Function Prototypes ******************************/
u32 XNandPs8_OnfiParamPageCrc(u8 *ParamBuf, u32 StartOff, u32 Length);
#ifdef __cplusplus
}
#endif
#endif /* XNANDPS8_ONFI_H end of protection macro */

106
XilinxProcessorIPLib/drivers/nandps8_v2_0/src/xnandps8_sinit.c Executable file
View file

@ -0,0 +1,106 @@
/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
* and
* (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits,
* goodwill, or any type of loss or damage suffered as a result of any
* action brought by a third party) even if such damage or loss was
* reasonably foreseeable or Xilinx had been advised of the possibility
* of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail- safe, or for use
* in any application requiring fail-safe performance, such as life-support
* or safety devices or systems, Class III medical devices, nuclear
* facilities, applications related to the deployment of airbags, or any
* other applications that could lead to death, personal injury, or severe
* property or environmental damage (individually and collectively,
* "Critical Applications"). Customer assumes the sole risk and liability
* of any use of Xilinx products in Critical Applications, subject only to
* applicable laws and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART
* OF THIS FILE AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xnandps8_sinit.c
*
* The implementation of the XNandPs8 driver's static initialzation
* functionality.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- ---------- -----------------------------------------------
* 1.0 nm 05/06/2014 First release
* </pre>
*
******************************************************************************/
/***************************** Include Files ********************************/
#include "xstatus.h"
#include "xparameters.h"
#include "xnandps8.h"
/************************** Constant Definitions ****************************/
#define XPAR_XNANDPS8_NUM_INSTANCES 1U
/**************************** Type Definitions ******************************/
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Variable Definitions ****************************/
extern XNandPs8_Config XNandPs8_ConfigTable[];
/************************** Function Prototypes *****************************/
/****************************************************************************/
/**
*
* Looks up the controller configuration based on the unique controller ID. A
* table contains the configuration info for each controller in the system.
*
* @param DeviceID is the ID of the controller to look up the
* configuration for.
*
* @return
* A pointer to the configuration found or NULL if the specified
* controller ID was not found.
*
******************************************************************************/
XNandPs8_Config *XNandPs8_LookupConfig(u16 DeviceID)
{
XNandPs8_Config *CfgPtr = NULL;
u32 Index;
for (Index = 0U; Index < XPAR_XNANDPS8_NUM_INSTANCES; Index++) {
if (XNandPs8_ConfigTable[Index].DeviceId == DeviceID) {
CfgPtr = &XNandPs8_ConfigTable[Index];
break;
}
}
return (XNandPs8_Config *)CfgPtr;
}