stv0g/embeddedsw
1
0
Fork 0
Code Issues Pull requests Releases Wiki Activity

emacps: Add support for jumbo frames

Browse source 
Add an option to enable jumbo frames for zynqmp.
Add frame size and receive buffer length masks to instance so that they can
be updated dynamically with jumbo enable/disable.
Provide new API XEmacPs_GetRxFrameSize instead of XEmacPs_BdGetLength to
find frame size in case of jumbo frames or otherwise.

Signed-off-by: Harini Katakam <harinik@xilinx.com>
This commit is contained in:
Harini Katakam 2015-03-14 12:26:55 +05:30 • committed by Nava kishore Manne
parent bf50cadd34
commit 9b8d665400
5 changed files with 93 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

9
XilinxProcessorIPLib/drivers/emacps/src/xemacps.c
View file

@ -47,6 +47,7 @@
* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification and
* 64-bit changes.
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.0 hk 02/20/15 Added support for jumbo frames.
*
* </pre>
******************************************************************************/
@ -306,6 +307,14 @@ void XEmacPs_Reset(XEmacPs *InstancePtr)
InstancePtr->Version = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, 0xFC);
InstancePtr->Version = (InstancePtr->Version >> 16) & 0xFFF;
InstancePtr->MaxMtuSize = XEMACPS_MTU;
InstancePtr->MaxFrameSize = XEMACPS_MTU + XEMACPS_HDR_SIZE +
XEMACPS_TRL_SIZE;
InstancePtr->MaxVlanFrameSize = InstancePtr->MaxFrameSize +
XEMACPS_HDR_VLAN_SIZE;
InstancePtr->RxBufMask = XEMACPS_RXBUF_LEN_MASK;
/* Setup hardware with default values */
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET,

9
XilinxProcessorIPLib/drivers/emacps/src/xemacps.h
View file

@ -305,6 +305,7 @@
* configured with PCS/PMA Core. Changes are made in the
* test app tcl(CR:827686).
* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.0 hk 02/20/15 Added support for jumbo frames.
* </pre>
*
****************************************************************************/
@ -405,6 +406,7 @@ extern "C" {
/**< Enable the TX checksum offload
* This option defaults to enabled (set) */
#define XEMACPS_JUMBO_ENABLE_OPTION 0x00004000U
#define XEMACPS_DEFAULT_OPTIONS \
((u32)XEMACPS_FLOW_CONTROL_OPTION | \
@ -441,6 +443,7 @@ extern "C" {
#define XEMACPS_MAC_ADDR_SIZE 6U /* size of Ethernet header */
#define XEMACPS_MTU 1500U /* max MTU size of Ethernet frame */
#define XEMACPS_MTU_JUMBO 10240U /* max MTU size of jumbo frame */
#define XEMACPS_HDR_SIZE 14U /* size of Ethernet header */
#define XEMACPS_HDR_VLAN_SIZE 18U /* size of Ethernet header with VLAN */
#define XEMACPS_TRL_SIZE 4U /* size of Ethernet trailer (FCS) */
@ -448,6 +451,8 @@ extern "C" {
XEMACPS_TRL_SIZE)
#define XEMACPS_MAX_VLAN_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
#define XEMACPS_MAX_VLAN_FRAME_SIZE_JUMBO (XEMACPS_MTU_JUMBO + XEMACPS_HDR_SIZE + \
XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
/* DMACR Bust length hash defines */
@ -522,6 +527,10 @@ typedef struct XEmacPs_Instance {
XEmacPs_ErrHandler ErrorHandler;
void *ErrorRef;
u32 Version;
u32 RxBufMask;
u32 MaxMtuSize;
u32 MaxFrameSize;
u32 MaxVlanFrameSize;
} XEmacPs;

22
XilinxProcessorIPLib/drivers/emacps/src/xemacps_bd.h
View file

@ -64,6 +64,7 @@
* 2.1 srt 07/15/14 Add support for Ronaldo GEM specification and 64-bit
* changes.
* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.0 hk 02/20/15 Added support for jumbo frames.
*
* </pre>
*
@ -329,6 +330,27 @@ typedef UINTPTR XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
(XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_LEN_MASK)
/*****************************************************************************/
/**
* Retrieve the RX frame size.
*
* The returned value is the size of the received packet.
* This API supports jumbo frame sizes if enabled.
*
* @param BdPtr is the BD pointer to operate on
*
* @return Length field processed by hardware or set by
* XEmacPs_BdSetLength().
*
* @note
* C-style signature:
* UINTPTR XEmacPs_GetRxFrameSize(XEmacPs* InstancePtr, XEmacPs_Bd* BdPtr)
* RxBufMask is dependent on whether jumbo is enabled or not.
*
*****************************************************************************/
#define XEmacPs_GetRxFrameSize(InstancePtr, BdPtr) \
(XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
(InstancePtr)->RxBufMask)
/*****************************************************************************/
/**

47
XilinxProcessorIPLib/drivers/emacps/src/xemacps_control.c
View file

@ -49,6 +49,7 @@
* in DMACR register.
* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture.
* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.0 hk 02/20/15 Added support for jumbo frames.
* </pre>
*****************************************************************************/
@ -521,6 +522,30 @@ LONG XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options)
RegNewNetCfg |= XEMACPS_NWCFG_RXCHKSUMEN_MASK;
}
/* Enable jumbo frames */
if (((Options & XEMACPS_JUMBO_ENABLE_OPTION) != 0x00000000U) &&
(InstancePtr->Version > 2)) {
RegNewNetCfg |= XEMACPS_NWCFG_JUMBO_MASK;
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_JUMBOMAXLEN_OFFSET, XEMACPS_RX_BUF_SIZE_JUMBO);
Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_DMACR_OFFSET);
Reg &= ~XEMACPS_DMACR_RXBUF_MASK;
Reg |= (((((u32)XEMACPS_RX_BUF_SIZE_JUMBO / (u32)XEMACPS_RX_BUF_UNIT) +
(((((u32)XEMACPS_RX_BUF_SIZE_JUMBO %
(u32)XEMACPS_RX_BUF_UNIT))!=(u32)0) ? 1U : 0U)) <<
(u32)(XEMACPS_DMACR_RXBUF_SHIFT)) &
(u32)(XEMACPS_DMACR_RXBUF_MASK));
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_DMACR_OFFSET, Reg);
InstancePtr->MaxMtuSize = XEMACPS_MTU_JUMBO;
InstancePtr->MaxFrameSize = XEMACPS_MTU_JUMBO +
XEMACPS_HDR_SIZE + XEMACPS_TRL_SIZE;
InstancePtr->MaxVlanFrameSize = InstancePtr->MaxFrameSize +
XEMACPS_HDR_VLAN_SIZE;
InstancePtr->RxBufMask = XEMACPS_RXBUF_LEN_JUMBO_MASK;
}
/* Officially change the NET_CONFIG registers if it needs to be
* modified.
*/
@ -658,6 +683,28 @@ LONG XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options)
RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_RXCHKSUMEN_MASK);
}
/* Disable jumbo frames */
if (((Options & XEMACPS_JUMBO_ENABLE_OPTION) != 0x00000000U) &&
(InstancePtr->Version > 2)) {
RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_JUMBO_MASK);
Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_DMACR_OFFSET);
Reg &= ~XEMACPS_DMACR_RXBUF_MASK;
Reg |= (((((u32)XEMACPS_RX_BUF_SIZE / (u32)XEMACPS_RX_BUF_UNIT) +
(((((u32)XEMACPS_RX_BUF_SIZE %
(u32)XEMACPS_RX_BUF_UNIT))!=(u32)0) ? 1U : 0U)) <<
(u32)(XEMACPS_DMACR_RXBUF_SHIFT)) &
(u32)(XEMACPS_DMACR_RXBUF_MASK));
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_DMACR_OFFSET, Reg);
InstancePtr->MaxMtuSize = XEMACPS_MTU;
InstancePtr->MaxFrameSize = XEMACPS_MTU +
XEMACPS_HDR_SIZE + XEMACPS_TRL_SIZE;
InstancePtr->MaxVlanFrameSize = InstancePtr->MaxFrameSize +
XEMACPS_HDR_VLAN_SIZE;
InstancePtr->RxBufMask = XEMACPS_RXBUF_LEN_MASK;
}
/* Officially change the NET_CONFIG registers if it needs to be
* modified.
*/

6
XilinxProcessorIPLib/drivers/emacps/src/xemacps_hw.h
View file

@ -55,6 +55,7 @@
* XEMACPS_NWCFG_LENERRDSCRD_MASK as it exceeds 31 characters.
* 3.0 kpc 1/23/15 Corrected the extended descriptor macro values.
* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.0 hk 02/20/15 Added support for jumbo frames.
* </pre>
*
******************************************************************************/
@ -113,6 +114,8 @@ typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
#define XEMACPS_RX_BUF_SIZE 1536U /**< Specify the receive buffer size in
bytes, 64, 128, ... 10240 */
#define XEMACPS_RX_BUF_SIZE_JUMBO 10240U
#define XEMACPS_RX_BUF_UNIT 64U /**< Number of receive buffer bytes as a
unit, this is HW setup */
@ -144,6 +147,8 @@ typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
#define XEMACPS_RXPAUSE_OFFSET 0x00000038U /**< RX Pause Time reg */
#define XEMACPS_TXPAUSE_OFFSET 0x0000003CU /**< TX Pause Time reg */
#define XEMACPS_JUMBOMAXLEN_OFFSET 0x00000048U /**< Jumbo max length reg */
#define XEMACPS_HASHL_OFFSET 0x00000080U /**< Hash Low address reg */
#define XEMACPS_HASHH_OFFSET 0x00000084U /**< Hash High address reg */
@ -572,6 +577,7 @@ typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
#define XEMACPS_RXBUF_EOF_MASK 0x00008000U /**< End of frame. */
#define XEMACPS_RXBUF_SOF_MASK 0x00004000U /**< Start of frame. */
#define XEMACPS_RXBUF_LEN_MASK 0x00001FFFU /**< Mask for length field */
#define XEMACPS_RXBUF_LEN_JUMBO_MASK 0x00003FFFU /**< Mask for jumbo length */
#define XEMACPS_RXBUF_WRAP_MASK 0x00000002U /**< Wrap bit, last BD */
#define XEMACPS_RXBUF_NEW_MASK 0x00000001U /**< Used bit.. */