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iicps_v2_4: TimeOut Register value is modified.

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This Patch modifies the TimeOut Register value,although timeout interrupt is not used, this register is changed to set to the maximum allowed HW timeout value.

Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
This commit is contained in:
P L Sai Krishna 2014-11-03 20:41:05 +05:30 • committed by Suneel Garapati
parent eeafc59a05
commit a1b1070f78
5 changed files with 9 additions and 5 deletions
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2
XilinxProcessorIPLib/drivers/iicps_v2_4/src/xiicps.c
View file

@ -48,6 +48,8 @@
* and state the same in the comments. CR# 784254.
* Fix for CR# 761060 - provision for repeated start.
* 2.3 sk 10/07/14 Repeated start feature removed.
* 2.4 sk 11/03/14 Modified TimeOut Register value to 0xFF
* in XIicPs_Reset.
*
* </pre>
*

2
XilinxProcessorIPLib/drivers/iicps_v2_4/src/xiicps.h
View file

@ -168,6 +168,8 @@
* read mode and clear transfer size register.
* Disable NACK to avoid interrupts on each retry.
* 2.3 sk 10/07/14 Repeated start feature deleted.
* 2.4 sk 11/03/14 Modified TimeOut Register value to 0xFF
* in XIicPs_Reset.
*
* </pre>
*

3
XilinxProcessorIPLib/drivers/iicps_v2_4/src/xiicps_hw.c
View file

@ -42,6 +42,7 @@
* Ver Who Date Changes
* ----- ------ -------- --------------------------------------------
* 1.04a kpc 11/07/13 First release
* 2.4 sk 11/03/14 Modified TimeOut Register value to 0xFF
*
* </pre>
*
@ -95,7 +96,7 @@ void XIicPs_ResetHw(u32 BaseAddress)
RegVal |= XIICPS_CR_CLR_FIFO_MASK;
XIicPs_WriteReg(BaseAddress, XIICPS_CR_OFFSET, RegVal);
/* Clear the timeout register */
XIicPs_WriteReg(BaseAddress, XIICPS_TIME_OUT_OFFSET, 0x0);
XIicPs_WriteReg(BaseAddress, XIICPS_TIME_OUT_OFFSET, XIICPS_TO_RESET_VALUE);
/* Clear the transfer size register */
XIicPs_WriteReg(BaseAddress, XIICPS_TRANS_SIZE_OFFSET, 0x0);
/* Clear the status register */

3
XilinxProcessorIPLib/drivers/iicps_v2_4/src/xiicps_hw.h
View file

@ -45,6 +45,7 @@
* ----- ------ -------- -----------------------------------------------
* 1.00a drg/jz 01/30/10 First release
* 1.04a kpc 11/07/13 Added function prototype.
* 2.4 sk 11/03/14 Modified the TimeOut Register value to 0xFF
* </pre>
*
******************************************************************************/
@ -253,7 +254,7 @@ extern "C" {
* @{
*/
#define XIICPS_TIME_OUT_MASK 0x000000FF /**< IIC Time Out mask */
#define XIICPS_TO_RESET_VALUE 0x0000001F /**< IIC Time Out reset value */
#define XIICPS_TO_RESET_VALUE 0x000000FF /**< IIC Time Out reset value */
/* @} */
/**************************** Type Definitions *******************************/

4
XilinxProcessorIPLib/drivers/iicps_v2_4/src/xiicps_selftest.c
View file

@ -44,6 +44,7 @@
* ----- ------ -------- ---------------------------------------------
* 1.00a drg/jz 01/30/10 First release
* 1.00a sdm 09/22/11 Removed unused code
* 2.4 sk 11/03/14 Removed TimeOut Register value check
* </pre>
*
******************************************************************************/
@ -99,9 +100,6 @@ int XIicPs_SelfTest(XIicPs *InstancePtr)
if ((XIICPS_CR_RESET_VALUE !=
XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
XIICPS_CR_OFFSET)) ||
(XIICPS_TO_RESET_VALUE !=
XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
XIICPS_TIME_OUT_OFFSET)) ||
(XIICPS_IXR_ALL_INTR_MASK !=
XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
XIICPS_IMR_OFFSET))) {