lwip: axiethernet: Support to get autoneg speed for different PHYs
Currently, the AXI Ethernet adapter is configured to support only Marvel PHYs which exist on all Xilinx boards. This patch allows to get the auto-negotiation speed of any PHY using IEEE specification. Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
This commit is contained in:
Srikanth Thokala
Jagannadha Sutradharudu Teki
parent
2ba225fa69
commit
a503a3dd66
2 changed files with 149 additions and 139 deletions
3
ThirdParty/sw_services/lwip140/src/ChangeLog
vendored
3
ThirdParty/sw_services/lwip140/src/ChangeLog
vendored
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@ -1,5 +1,8 @@
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Change Log for lwip
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=================================
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2014-06-06
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* Fix for CR 800240 - Removed the limitation of
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supporting only Marvel PHY in AXI Ethernet adapter.
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2014-1-30
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* Fix for CRs 771112 and 766087. The sys_arch.c
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last made (related to freertos) are reverted back.
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@ -147,6 +147,85 @@ static int detect_phy(XAxiEthernet *xaxiemacp)
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return 0;
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}
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unsigned get_phy_speed_88E1116R_model(XAxiEthernet *xaxiemacp, u32 phy_addr)
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{
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u16 phy_val;
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u16 control;
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u16 status;
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u16 partner_capabilities;
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xil_printf("Start PHY autonegotiation \r\n");
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XAxiEthernet_PhyWrite(xaxiemacp,phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 2);
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XAxiEthernet_PhyRead(xaxiemacp, phy_addr, IEEE_CONTROL_REG_MAC, &control);
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control |= IEEE_RGMII_TXRX_CLOCK_DELAYED_MASK;
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XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, IEEE_CONTROL_REG_MAC, control);
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XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 0);
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XAxiEthernet_PhyRead(xaxiemacp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, &control);
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control |= IEEE_ASYMMETRIC_PAUSE_MASK;
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control |= IEEE_PAUSE_MASK;
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control |= ADVERTISE_100;
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control |= ADVERTISE_10;
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XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, control);
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XAxiEthernet_PhyRead(xaxiemacp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET,
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&control);
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control |= ADVERTISE_1000;
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XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET,
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control);
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XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 0);
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XAxiEthernet_PhyRead(xaxiemacp, phy_addr, IEEE_COPPER_SPECIFIC_CONTROL_REG,
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&control);
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control |= (7 << 12); /* max number of gigabit atphy_valts */
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control |= (1 << 11); /* enable downshift */
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XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, IEEE_COPPER_SPECIFIC_CONTROL_REG,
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control);
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XAxiEthernet_PhyRead(xaxiemacp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control);
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control |= IEEE_CTRL_AUTONEGOTIATE_ENABLE;
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control |= IEEE_STAT_AUTONEGOTIATE_RESTART;
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XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, IEEE_CONTROL_REG_OFFSET, control);
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XAxiEthernet_PhyRead(xaxiemacp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control);
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control |= IEEE_CTRL_RESET_MASK;
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XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, IEEE_CONTROL_REG_OFFSET, control);
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while (1) {
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XAxiEthernet_PhyRead(xaxiemacp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control);
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if (control & IEEE_CTRL_RESET_MASK)
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continue;
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else
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break;
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}
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xil_printf("Waiting for PHY to complete autonegotiation.\r\n");
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XAxiEthernet_PhyRead(xaxiemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
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while ( !(status & IEEE_STAT_AUTONEGOTIATE_COMPLETE) ) {
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AxiEthernetUtilPhyDelay(1);
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XAxiEthernet_PhyRead(xaxiemacp, phy_addr, IEEE_COPPER_SPECIFIC_STATUS_REG_2,
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&phy_val);
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if (phy_val & IEEE_AUTONEG_ERROR_MASK) {
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xil_printf("Auto negotiation error \r\n");
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}
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XAxiEthernet_PhyRead(xaxiemacp, phy_addr, IEEE_STATUS_REG_OFFSET,
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&status);
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}
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xil_printf("autonegotiation complete \r\n");
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XAxiEthernet_PhyRead(xaxiemacp, phy_addr, IEEE_SPECIFIC_STATUS_REG,
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&partner_capabilities);
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if ( ((partner_capabilities >> 14) & 3) == 2)/* 1000Mbps */
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return 1000;
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else if ( ((partner_capabilities >> 14) & 3) == 1)/* 100Mbps */
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return 100;
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else /* 10Mbps */
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return 10;
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}
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unsigned get_IEEE_phy_speed(XAxiEthernet *xaxiemacp)
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{
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u32 phy_addr = detect_phy(xaxiemacp);
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@ -165,6 +244,12 @@ unsigned get_IEEE_phy_speed(XAxiEthernet *xaxiemacp)
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XAxiEthernet_PhyRead(xaxiemacp, phy_addr, 3, &phy_model);
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phy_model = phy_model & PHY_MODEL_NUM_MASK;
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if ((phy_identifier == MARVEL_PHY_IDENTIFIER) &&
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(phy_model == MARVEL_PHY_88E1116R_MODEL)) {
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return get_phy_speed_88E1116R_model(xaxiemacp, phy_addr);
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}
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if ((phy_identifier == MARVEL_PHY_IDENTIFIER) &&
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(phy_model == MARVEL_PHY_88E1111_MODEL)) {
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if (XAxiEthernet_GetPhysicalInterface(xaxiemacp) ==
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@ -190,171 +275,93 @@ unsigned get_IEEE_phy_speed(XAxiEthernet *xaxiemacp)
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xil_printf("%s: Phy Reset failed\n\r", __FUNCTION__);
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return 0;
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}
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}
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}
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}
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XAxiEthernet_PhyWrite(xaxiemacp, phy_addr,
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XAxiEthernet_PhyWrite(xaxiemacp, phy_addr,
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IEEE_1000_ADVERTISE_REG_OFFSET,
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ADVERTISE_1000);
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XAxiEthernet_PhyWrite(xaxiemacp, phy_addr,
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XAxiEthernet_PhyWrite(xaxiemacp, phy_addr,
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IEEE_AUTONEGO_ADVERTISE_REG,
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ADVERTISE_100_AND_10);
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XAxiEthernet_PhyRead(xaxiemacp, phy_addr,
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IEEE_CONTROL_REG_OFFSET,
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&control);
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control |= (IEEE_CTRL_AUTONEGOTIATE_ENABLE |
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IEEE_STAT_AUTONEGOTIATE_RESTART);
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XAxiEthernet_PhyRead(xaxiemacp, phy_addr,
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IEEE_CONTROL_REG_OFFSET,
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&control);
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control |= (IEEE_CTRL_AUTONEGOTIATE_ENABLE |
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IEEE_STAT_AUTONEGOTIATE_RESTART);
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XAxiEthernet_PhyWrite(xaxiemacp, phy_addr,
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XAxiEthernet_PhyWrite(xaxiemacp, phy_addr,
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IEEE_CONTROL_REG_OFFSET,
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control);
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/* Read PHY control and status registers is successful. */
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XAxiEthernet_PhyRead(xaxiemacp, phy_addr,
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IEEE_CONTROL_REG_OFFSET,
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&control);
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XAxiEthernet_PhyRead(xaxiemacp, phy_addr,
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/* Read PHY control and status registers is successful. */
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XAxiEthernet_PhyRead(xaxiemacp, phy_addr,
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IEEE_CONTROL_REG_OFFSET,
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&control);
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XAxiEthernet_PhyRead(xaxiemacp, phy_addr,
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IEEE_STATUS_REG_OFFSET,
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&status);
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if ((control & IEEE_CTRL_AUTONEGOTIATE_ENABLE) && (status &
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IEEE_STAT_AUTONEGOTIATE_CAPABLE)) {
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while ( !(status & IEEE_STAT_AUTONEGOTIATE_COMPLETE) ) {
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XAxiEthernet_PhyRead(xaxiemacp, phy_addr,
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IEEE_STATUS_REG_OFFSET,
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&status);
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}
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if ((control & IEEE_CTRL_AUTONEGOTIATE_ENABLE) && (status &
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IEEE_STAT_AUTONEGOTIATE_CAPABLE)) {
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while ( !(status & IEEE_STAT_AUTONEGOTIATE_COMPLETE) ) {
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XAxiEthernet_PhyRead(xaxiemacp, phy_addr,
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IEEE_STATUS_REG_OFFSET,
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&status);
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}
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XAxiEthernet_PhyRead(xaxiemacp, phy_addr,
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XAxiEthernet_PhyRead(xaxiemacp, phy_addr,
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IEEE_PARTNER_ABILITIES_1_REG_OFFSET,
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&partner_capabilities);
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if (status & IEEE_STAT_1GBPS_EXTENSIONS) {
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XAxiEthernet_PhyRead(xaxiemacp, phy_addr,
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if (status & IEEE_STAT_1GBPS_EXTENSIONS) {
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XAxiEthernet_PhyRead(xaxiemacp, phy_addr,
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IEEE_PARTNER_ABILITIES_3_REG_OFFSET,
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&partner_capabilities_1000);
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if (partner_capabilities_1000 &
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IEEE_AN3_ABILITY_MASK_1GBPS)
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return 1000;
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}
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if (partner_capabilities_1000 &
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IEEE_AN3_ABILITY_MASK_1GBPS)
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return 1000;
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}
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if (partner_capabilities & IEEE_AN1_ABILITY_MASK_100MBPS)
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return 100;
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if (partner_capabilities & IEEE_AN1_ABILITY_MASK_10MBPS)
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return 10;
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xil_printf("%s: unknown PHY link speed, setting TEMAC speed to be 10 Mbps\r\n",
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__FUNCTION__);
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if (partner_capabilities & IEEE_AN1_ABILITY_MASK_100MBPS)
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return 100;
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if (partner_capabilities & IEEE_AN1_ABILITY_MASK_10MBPS)
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return 10;
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xil_printf("%s: unknown PHY link speed, setting TEMAC speed to be 10 Mbps\r\n",
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__FUNCTION__);
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return 10;
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} else {
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/* Update TEMAC speed accordingly */
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if (status & IEEE_STAT_1GBPS_EXTENSIONS) {
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/* Get commanded link speed */
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phylinkspeed = control &
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IEEE_CTRL_1GBPS_LINKSPEED_MASK;
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switch (phylinkspeed) {
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case (IEEE_CTRL_LINKSPEED_1000M):
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return 1000;
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case (IEEE_CTRL_LINKSPEED_100M):
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return 100;
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case (IEEE_CTRL_LINKSPEED_10M):
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return 10;
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default:
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xil_printf("%s: unknown PHY link speed (%d), setting TEMAC speed to be 10 Mbps\r\n",
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__FUNCTION__, phylinkspeed);
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return 10;
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}
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} else {
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/* Update TEMAC speed accordingly */
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if (status & IEEE_STAT_1GBPS_EXTENSIONS) {
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/* Get commanded link speed */
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phylinkspeed = control &
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IEEE_CTRL_1GBPS_LINKSPEED_MASK;
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switch (phylinkspeed) {
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case (IEEE_CTRL_LINKSPEED_1000M):
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return 1000;
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case (IEEE_CTRL_LINKSPEED_100M):
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return 100;
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case (IEEE_CTRL_LINKSPEED_10M):
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return 10;
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default:
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xil_printf("%s: unknown PHY link speed (%d), setting TEMAC speed to be 10 Mbps\r\n",
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__FUNCTION__, phylinkspeed);
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return 10;
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}
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} else {
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return (control & IEEE_CTRL_LINKSPEED_MASK) ? 100 : 10;
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}
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}
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} else if ((phy_identifier == MARVEL_PHY_IDENTIFIER) &&
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(phy_model == MARVEL_PHY_88E1116R_MODEL)) {
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xil_printf("Start PHY autonegotiation \r\n");
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XAxiEthernet_PhyWrite(xaxiemacp,phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 2);
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XAxiEthernet_PhyRead(xaxiemacp, phy_addr, IEEE_CONTROL_REG_MAC, &control);
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control |= IEEE_RGMII_TXRX_CLOCK_DELAYED_MASK;
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XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, IEEE_CONTROL_REG_MAC, control);
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XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 0);
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XAxiEthernet_PhyRead(xaxiemacp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, &control);
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control |= IEEE_ASYMMETRIC_PAUSE_MASK;
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control |= IEEE_PAUSE_MASK;
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control |= ADVERTISE_100;
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control |= ADVERTISE_10;
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XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, control);
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XAxiEthernet_PhyRead(xaxiemacp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET,
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&control);
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control |= ADVERTISE_1000;
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XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET,
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control);
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XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 0);
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XAxiEthernet_PhyRead(xaxiemacp, phy_addr, IEEE_COPPER_SPECIFIC_CONTROL_REG,
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&control);
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control |= (7 << 12); /* max number of gigabit atphy_valts */
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control |= (1 << 11); /* enable downshift */
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XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, IEEE_COPPER_SPECIFIC_CONTROL_REG,
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control);
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XAxiEthernet_PhyRead(xaxiemacp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control);
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control |= IEEE_CTRL_AUTONEGOTIATE_ENABLE;
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control |= IEEE_STAT_AUTONEGOTIATE_RESTART;
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XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, IEEE_CONTROL_REG_OFFSET, control);
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XAxiEthernet_PhyRead(xaxiemacp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control);
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control |= IEEE_CTRL_RESET_MASK;
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XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, IEEE_CONTROL_REG_OFFSET, control);
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while (1) {
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XAxiEthernet_PhyRead(xaxiemacp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control);
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if (control & IEEE_CTRL_RESET_MASK)
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continue;
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else
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break;
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return (control & IEEE_CTRL_LINKSPEED_MASK) ? 100 : 10;
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}
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xil_printf("Waiting for PHY to complete autonegotiation.\r\n");
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XAxiEthernet_PhyRead(xaxiemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
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while ( !(status & IEEE_STAT_AUTONEGOTIATE_COMPLETE) ) {
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AxiEthernetUtilPhyDelay(1);
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XAxiEthernet_PhyRead(xaxiemacp, phy_addr, IEEE_COPPER_SPECIFIC_STATUS_REG_2,
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&phy_val);
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if (phy_val & IEEE_AUTONEG_ERROR_MASK) {
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xil_printf("Auto negotiation error \r\n");
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}
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XAxiEthernet_PhyRead(xaxiemacp, phy_addr, IEEE_STATUS_REG_OFFSET,
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&status);
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}
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xil_printf("autonegotiation complete \r\n");
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XAxiEthernet_PhyRead(xaxiemacp, phy_addr, IEEE_SPECIFIC_STATUS_REG,
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&partner_capabilities);
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if ( ((partner_capabilities >> 14) & 3) == 2)/* 1000Mbps */
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return 1000;
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else if ( ((partner_capabilities >> 14) & 3) == 1)/* 100Mbps */
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return 100;
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else /* 10Mbps */
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return 10;
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} else {
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xil_printf("%s: unknown PHY link speed\r\n", __FUNCTION__);
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return 0;
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}
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}
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