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dprxss: Added new driver DisplayPort Receiver Subsystem

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This patch adds DisplayPort Receiver Subsystem (dprxss) driver.

Signed-off-by: Shadul Shaikh <shaduls@xilinx.com>
Acked-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
This commit is contained in:
Shadul Shaikh 2015-08-11 11:41:54 +05:30 • committed by Nava kishore Manne
parent 1ec39318a8
commit a540e65ca9
17 changed files with 3203 additions and 0 deletions
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41
XilinxProcessorIPLib/drivers/dprxss/data/dprxss.mdd Normal file
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##############################################################################
#
# Copyright (C) 2015 Xilinx, Inc. All rights reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"),to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
#
# Use of the Software is limited solely to applications:
# (a) running on a Xilinx device, or
# (b) that interact with a Xilinx device through a bus or interconnect.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
# XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
# IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
#
# Except as contained in this notice, the name of the Xilinx shall not be used
# in advertising or otherwise to promote the sale, use or other dealings in
# this Software without prior written authorization from Xilinx.
###############################################################################
OPTION psf_version = 2.1;
BEGIN driver dprxss
OPTION supported_peripherals = (dp_rx_subsystem);
OPTION driver_state = ACTIVE;
OPTION depends = (video_common_v2_0);
OPTION copyfiles = all;
OPTION VERSION = 1.0;
OPTION NAME = dprxss;
END driver

180
XilinxProcessorIPLib/drivers/dprxss/data/dprxss.tcl Normal file
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##############################################################################
#
# Copyright (C) 2015 Xilinx, Inc. All rights reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"),to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
#
# Use of the Software is limited solely to applications:
# (a) running on a Xilinx device, or
# (b) that interact with a Xilinx device through a bus or interconnect.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
# XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
# IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
#
# Except as contained in this notice, the name of the Xilinx shall not be used
# in advertising or otherwise to promote the sale, use or other dealings in
# this Software without prior written authorization from Xilinx.
###############################################################################
proc generate {drv_handle} {
::hsi::utils::define_include_file $drv_handle "xparameters.h" "XDpRxSs" "NUM_INSTANCES" "DEVICE_ID" "C_BASEADDR" "C_HIGHADDR" "AUDIO_ENABLE" "NUM_AUD_CH" "BITS_PER_COLOR" "HDCP_ENABLE" "LANE_COUNT" "MODE" "NUM_STREAMS" "COLOR_FORMAT" "SIM_MODE"
hier_ip_define_config_file $drv_handle "xdprxss_g.c" "XDpRxSs" "DEVICE_ID" "C_BASEADDR" "AUDIO_ENABLE" "NUM_AUD_CH" "BITS_PER_COLOR" "HDCP_ENABLE" "LANE_COUNT" "MODE" "NUM_STREAMS" "COLOR_FORMAT"
::hsi::utils::define_canonical_xpars $drv_handle "xparameters.h" "DpRxSs" "DEVICE_ID" "C_BASEADDR" "C_HIGHADDR" "AUDIO_ENABLE" "NUM_AUD_CH" "BITS_PER_COLOR" "HDCP_ENABLE" "LANE_COUNT" "MODE" "NUM_STREAMS" "COLOR_FORMAT" "SIM_MODE"
}
##
# This procedure creates parameters XPAR_* of each sub-cores in xdprxss_g.c file.
# to align with subsystem config structure. Basically, subsystem is hierarchical IP (HIP),
# includes configuration parameters of each sub-cores along with its configuration
# parameters.
##
proc hier_ip_define_config_file {drv_handle file_name drv_string args} {
set args [::hsi::utils::get_exact_arg_list $args]
set brace 0
array set sub_core_params {}
set sub_core_params(displayport) "BASEADDR S_AXI_ACLK LANE_COUNT LINK_RATE MAX_BITS_PER_COLOR QUAD_PIXEL_ENABLE DUAL_PIXEL_ENABLE YCRCB_ENABLE YONLY_ENABLE GT_DATAWIDTH SECONDARY_SUPPORT AUDIO_CHANNELS MST_ENABLE NUMBER_OF_MST_STREAMS PROTOCOL_SELECTION FLOW_DIRECTION"
set sub_core_params(axi_iic) "BASEADDR TEN_BIT_ADR GPO_WIDTH"
set sub_core_params(hdcp) "BASEADDR S_AXI_FREQUENCY IS_RX IS_HDMI"
set total_subcores [array size sub_core_params]
set filename [file join "src" $file_name]
set config_file [open $filename w]
::hsi::utils::write_c_header $config_file "Driver configuration"
puts $config_file "#include \"xparameters.h\""
puts $config_file "#include \"[string tolower $drv_string].h\""
puts $config_file "\n/*"
puts $config_file "* The configuration table for devices"
puts $config_file "*/\n"
set periphs_g [::hsi::utils::get_common_driver_ips $drv_handle]
foreach periph_g $periphs_g {
::hsi::current_hw_instance $periph_g;
set child_cells_g [::hsi::get_cells]
foreach child_cell_g $child_cells_g {
set child_cell_vlnv [::common::get_property VLNV $child_cell_g]
set vlnv_arr [split $child_cell_vlnv :]
lassign $vlnv_arr ip_vendor ip_library ip_name ip_version
set child_cell_name_g [common::get_property NAME $child_cell_g]
set ip_type_g [common::get_property IP_TYPE $child_cell_g]
set final_child_cell_instance_name_present_g XPAR_${child_cell_name_g}_PRESENT
if { [string compare -nocase "BUS" $ip_type_g] != 0 } {
set interfaces [hsi::get_intf_pins -of_objects $child_cell_g]
set is_slave 0
foreach interface $interfaces {
set intf_type [common::get_property TYPE $interface]
if { [string compare -nocase "SLAVE" $intf_type] == 0 } {
set is_slave 1
}
}
if { $is_slave != 0 } {
puts -nonewline $config_file "#define [string toupper $final_child_cell_instance_name_present_g]\t1\n"
}
}
}
puts $config_file "\n"
::hsi::current_hw_instance
}
puts $config_file [format "%s_Config %s_ConfigTable\[\] =" $drv_string $drv_string]
puts $config_file "\{"
set periphs [::hsi::utils::get_common_driver_ips $drv_handle]
set start_comma ""
foreach periph $periphs {
puts $config_file [format "%s\t\{" $start_comma]
set comma ""
foreach arg $args {
if {[string compare -nocase "DEVICE_ID" $arg] == 0} {
puts -nonewline $config_file [format "%s\t\t%s,\n" $comma [::hsi::utils::get_ip_param_name $periph $arg]]
continue
}
puts -nonewline $config_file [format "%s\t\t%s" $comma [::hsi::utils::get_ip_param_name $periph $arg]]
set comma ",\n"
}
::hsi::current_hw_instance $periph
set child_cells [::hsi::get_cells]
puts $config_file ",\n"
foreach child_cell $child_cells {
set child_cell_vlnv [::common::get_property VLNV $child_cell]
set vlnv_arr [split $child_cell_vlnv :]
lassign $vlnv_arr ip_vendor ip_library ip_name ip_version
set ip_type [common::get_property IP_TYPE $child_cell]
set child_cell_name [common::get_property NAME $child_cell]
set final_child_cell_instance_name XPAR_${child_cell_name}_DEVICE_ID
set final_child_cell_instance_name_present XPAR_${child_cell_name}_PRESENT
if { [string compare -nocase "BUS" $ip_type] != 0 } {
set interfaces [hsi::get_intf_pins -of_objects $child_cell]
set is_slave 0
foreach interface $interfaces {
set intf_type [common::get_property TYPE $interface]
if { [string compare -nocase "SLAVE" $intf_type] == 0 } {
set is_slave 1
}
}
if { $is_slave != 0 } {
set comma ",\n"
puts $config_file "\t\t\{"
puts -nonewline $config_file [format "\t\t\t%s" [string toupper $final_child_cell_instance_name_present]]
puts $config_file ","
puts $config_file "\t\t\t\{"
puts -nonewline $config_file [format "\t\t\t\t%s" [string toupper $final_child_cell_instance_name]]
set params_str $sub_core_params($ip_name)
set params_arr [split $params_str " " ]
foreach param $params_arr {
set final_child_cell_param_name XPAR_${child_cell_name}_$param
puts $config_file ","
puts -nonewline $config_file [format "\t\t\t\t%s" [string toupper $final_child_cell_param_name]]
}
puts $config_file "\n\t\t\t\}"
if { $brace < $total_subcores - 1 } {
puts $config_file "\t\t\},"
incr brace
} else {
puts $config_file "\t\t\}"
}
}
}
}
::hsi::current_hw_instance
puts -nonewline $config_file "\t\}"
set start_comma ",\n"
}
puts $config_file "\n\};"
puts $config_file "\n";
close $config_file
}

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XilinxProcessorIPLib/drivers/dprxss/src/Makefile Normal file
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COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=-Wall -Wextra
LIB=libxil.a
CC_FLAGS = $(COMPILER_FLAGS)
ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}
OUTS = *.o
INCLUDEFILES=*.h ./dp/*.h ./iic/*.h ./hdcp1x/*.h
LIBSOURCES=*.c ./dp/*.c ./iic/*.c ./hdcp1x/*.c
OBJECTS = $(addsuffix .o, $(basename ./dp/xdprxss_dprx.c ./iic/xdprxss_iic.c ./hdcp1x/xdprxss_hdcp1x.c $(wildcard *.c)))
libs: banner xdprxss_libs clean
%.o: %.c
${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
banner:
echo "Compiling DisplayPort Receiver Subsystem"
xdprxss_libs: ${OBJECTS}
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
.PHONY: include
include: xdprxss_includes
xdprxss_includes:
${CP} ${INCLUDEFILES} ${INCLUDEDIR}
clean:
rm -rf ${OBJECTS}

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XilinxProcessorIPLib/drivers/dprxss/src/dp/xdprxss_dprx.c Normal file
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/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xdprxss_dprx.c
*
* This file contains a minimal set of functions for the DisplayPort core
* to configure.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ---- --- -------- -----------------------------------------------------
* 1.00 sha 05/18/15 Initial release.
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xdprxss_dprx.h"
/************************** Constant Definitions *****************************/
/***************** Macros (Inline Functions) Definitions *********************/
/**************************** Type Definitions *******************************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/************************** Function Definitions *****************************/

80
XilinxProcessorIPLib/drivers/dprxss/src/dp/xdprxss_dprx.h Normal file
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/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xdprxss_dprx.h
*
* This is the header file for Xilinx DisplayPort Receiver Subsystem sub-core,
* is DisplayPort.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ---- --- -------- -----------------------------------------------------
* 1.00 sha 05/18/15 Initial release.
* </pre>
*
******************************************************************************/
#ifndef XDPRXSS_DPRX_H_
#define XDPRXSS_DPRX_H_ /**< Prevent circular inclusions
* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xdp.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Declarations ****************************/
#ifdef __cplusplus
}
#endif
#endif /* End of protection macro */

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XilinxProcessorIPLib/drivers/dprxss/src/hdcp1x/xdprxss_hdcp1x.c Normal file
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/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xdprxss_hdcp1x.c
*
* This file contains a minimal set of functions for the High-Bandwidth Content
* Protection core to configure.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ---- --- -------- -----------------------------------------------------
* 1.00 sha 05/18/15 Initial release.
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xdprxss_hdcp1x.h"
/************************** Constant Definitions *****************************/
/***************** Macros (Inline Functions) Definitions *********************/
/**************************** Type Definitions *******************************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/************************** Function Definitions *****************************/

80
XilinxProcessorIPLib/drivers/dprxss/src/hdcp1x/xdprxss_hdcp1x.h Normal file
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/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xdprxss_hdcp1x.h
*
* This is the header file for Xilinx DisplayPort Receiver Subsystem sub-core,
* is High-Bandwidth Content Protection (HDCP).
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ---- --- -------- -----------------------------------------------------
* 1.00 sha 05/18/15 Initial release.
* </pre>
*
******************************************************************************/
#ifndef XDPRXSS_HDCP1X_H_
#define XDPRXSS_HDCP1X_H_ /**< Prevent circular inclusions
* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xhdcp1x.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Declarations ****************************/
#ifdef __cplusplus
}
#endif
#endif /* End of protection macro */

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XilinxProcessorIPLib/drivers/dprxss/src/iic/xdprxss_iic.c Normal file
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/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xdprxss_iic.c
*
* This file contains a minimal set of functions for the IIC core to configure.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ---- --- -------- -----------------------------------------------------
* 1.00 sha 05/18/15 Initial release.
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xdprxss_iic.h"
/************************** Constant Definitions *****************************/
/***************** Macros (Inline Functions) Definitions *********************/
/**************************** Type Definitions *******************************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/************************** Function Definitions *****************************/

80
XilinxProcessorIPLib/drivers/dprxss/src/iic/xdprxss_iic.h Normal file
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/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xdprxss_iic.h
*
* This is the header file for Xilinx DisplayPort Receiver Subsystem sub-core,
* is IIC.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ---- --- -------- -----------------------------------------------------
* 1.00 sha 05/18/15 Initial release.
* </pre>
*
******************************************************************************/
#ifndef XDPRXSS_IIC_H_
#define XDPRXSS_IIC_H_ /**< Prevent circular inclusions
* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xiic.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Declarations ****************************/
#ifdef __cplusplus
}
#endif
#endif /* End of protection macro */

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/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xdprxss.c
*
* This is the main file for Xilinx DisplayPort Receiver Subsystem driver.
* This file contains a minimal set of functions for the XDpRxSs driver that
* allow access to all of the DisplayPort Receiver Subsystem core's
* functionality. Please see xdprxss.h for more details of the driver.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ---- --- -------- -----------------------------------------------------
* 1.00 sha 05/18/15 Initial release.
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xdprxss.h"
#include "xvidc_dp159.h"
#include "string.h"
#include "xdebug.h"
/************************** Constant Definitions *****************************/
/***************** Macros (Inline Functions) Definitions *********************/
/**************************** Type Definitions *******************************/
/* Subsystem sub-core's structure includes instances of each sub-core */
typedef struct {
XDp DpInst;
XIic IicInst;
} XDpRxSs_SubCores;
/************************** Function Prototypes ******************************/
static void DpRxSs_GetIncludedSubCores(XDpRxSs *InstancePtr);
static void DpRxSs_PopulateDpRxPorts(XDpRxSs *InstancePtr);
static void StubTp1Callback(void *InstancePtr);
static void StubTp2Callback(void *InstancePtr);
static void StubUnplugCallback(void *InstancePtr);
/************************** Variable Definitions *****************************/
/* A generic EDID structure. */
u8 GenEdid[128] = {
0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
0x61, 0x2c, 0x01, 0x00, 0x78, 0x56, 0x34, 0x12,
0x01, 0x18, 0x01, 0x04, 0xa0, 0x2f, 0x1e, 0x78,
0x00, 0xee, 0x95, 0xa3, 0x54, 0x4c, 0x99, 0x26,
0x0f, 0x50, 0x54, 0x21, 0x08, 0x00, 0x71, 0x4f,
0x81, 0x80, 0xb3, 0x00, 0xd1, 0xc0, 0x01, 0x01,
0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x3a,
0x80, 0x18, 0x71, 0x38, 0x2d, 0x40, 0x58, 0x2c,
0x45, 0x00, 0x40, 0x84, 0x63, 0x00, 0x00, 0x1e,
0x00, 0x00, 0x00, 0xff, 0x00, 0x58, 0x49, 0x4c,
0x44, 0x50, 0x53, 0x49, 0x4e, 0x4b, 0x0a, 0x20,
0x20, 0x20, 0x00, 0x00, 0x00, 0xfc, 0x00, 0x58,
0x49, 0x4c, 0x20, 0x44, 0x50, 0x0a, 0x20, 0x20,
0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xfd,
0x00, 0x38, 0x3c, 0x1e, 0x53, 0x10, 0x00, 0x0a,
0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x00, 0x39
};
/* A generic DPCD structure. */
u8 GenDpcd[] = {
0x12, 0x0a, 0x84, 0x01, 0x01, 0x00, 0x00, 0x00, 0x02
};
/* DisplayPort RX subcores instance */
XDpRxSs_SubCores DpRxSsSubCores;
/************************** Function Definitions *****************************/
/*****************************************************************************/
/**
*
* This function initializes the DisplayPort Receiver Subsystem core. This
* function must be called prior to using the core. Initialization of the core
* includes setting up the instance data and ensuring the hardware is in a
* quiescent state.
*
* @param InstancePtr is a pointer to the XDpRxSs core instance.
* @param CfgPtr points to the configuration structure associated with
* the DisplayPort RX Subsystem core.
* @param EffectiveAddr is the base address of the device. If address
* translation is being used, then this parameter must reflect the
* virtual base address. Otherwise, the physical address should be
* used.
*
* @return
* - XST_DEVICE_NOT_FOUND if sub-core not found.
* - XST_FAILURE if sub-core initialization failed.
* - XST_SUCCESS if XDpRxSs_CfgInitialize successful.
*
* @note None.
*
******************************************************************************/
u32 XDpRxSs_CfgInitialize(XDpRxSs *InstancePtr, XDpRxSs_Config *CfgPtr,
u32 EffectiveAddr)
{
XIic_Config IicConfig;
XDp_Config DpConfig;
u32 Status;
/* Verify arguments. */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(CfgPtr != NULL);
Xil_AssertNonvoid(EffectiveAddr != (u32)0x0);
/* Setup the instance */
(void)memset((void *)InstancePtr, 0, sizeof(XDpRxSs));
(void)memcpy((void *)&(InstancePtr->Config), (const void *)CfgPtr,
sizeof(XDpRxSs_Config));
InstancePtr->Config.BaseAddress = EffectiveAddr;
/* Get included sub-cores in the DisplayPort RX Subsystem */
DpRxSs_GetIncludedSubCores(InstancePtr);
/* Check for IIC availability */
if (InstancePtr->IicPtr) {
xdbg_printf((XDBG_DEBUG_GENERAL),"SS INFO: Initializing "
"IIC IP\n\r");
/* Calculate absolute base address of IIC sub-core */
InstancePtr->Config.IicSubCore.IicConfig.BaseAddress +=
InstancePtr->Config.BaseAddress;
/* Copy IIC config into local IIC config */
(void)memcpy((void *)&(IicConfig),
(const void *)&CfgPtr->IicSubCore.IicConfig,
sizeof(IicConfig));
/* IIC config initialize */
IicConfig.BaseAddress += InstancePtr->Config.BaseAddress;
Status = XIic_CfgInitialize(InstancePtr->IicPtr, &IicConfig,
IicConfig.BaseAddress);
if ((Status != XST_SUCCESS) && (Status !=
XST_DEVICE_IS_STARTED)) {
xdbg_printf(XDBG_DEBUG_GENERAL,"SS ERR:: IIC "
"initialization failed!\n\r");
return XST_FAILURE;
}
/* Reset DP159 */
XVidC_Dp159Reset(InstancePtr->IicPtr, TRUE);
/* IIC initialization for dynamic functionality */
Status = XIic_DynamicInitialize(InstancePtr->IicPtr);
if (Status != XST_SUCCESS) {
xdbg_printf(XDBG_DEBUG_GENERAL,"SS ERR:: IIC "
"dynamic initialization failed!\n\r");
return XST_FAILURE;
}
}
/* Check for DisplayPort availability */
if (InstancePtr->DpPtr) {
xdbg_printf((XDBG_DEBUG_GENERAL),"SS INFO: Initializing "
"DisplayPort Receiver IP\n\r");
/* Assign number of streams to one when MST is not enabled */
if (InstancePtr->Config.MstSupport) {
InstancePtr->UsrOpt.NumOfStreams =
InstancePtr->Config.NumMstStreams;
}
else {
InstancePtr->Config.DpSubCore.DpConfig.NumMstStreams =
1;
InstancePtr->UsrOpt.NumOfStreams = 1;
InstancePtr->Config.NumMstStreams = 1;
}
/* Calculate absolute base address of DP sub-core */
InstancePtr->Config.DpSubCore.DpConfig.BaseAddr +=
InstancePtr->Config.BaseAddress;
/* Copy DP config into local DP config */
(void)memcpy((void *)&(DpConfig),
(const void *)&CfgPtr->DpSubCore.DpConfig,
sizeof(XDp_Config));
/* DisplayPort config initialize */
DpConfig.BaseAddr += InstancePtr->Config.BaseAddress;
XDp_CfgInitialize(InstancePtr->DpPtr, &DpConfig,
DpConfig.BaseAddr);
/* Set maximum link rate for the first time */
XDp_RxSetLinkRate(InstancePtr->DpPtr,
InstancePtr->DpPtr->Config.MaxLinkRate);
/* Set maximum lane count for the first time */
XDp_RxSetLaneCount(InstancePtr->DpPtr,
InstancePtr->Config.MaxLaneCount);
/* Bring DP159 out of reset */
XVidC_Dp159Reset(InstancePtr->IicPtr, FALSE);
/* Wait for us */
XDp_WaitUs(InstancePtr->DpPtr, 800);
/* Initialize DP159 */
XVidC_Dp159Initialize(InstancePtr->IicPtr);
/* Wait for us */
XDp_WaitUs(InstancePtr->DpPtr, 900);
/* Initialize default training pattern callbacks in DP RX
* Subsystem
*/
XDp_RxSetIntrTp1Handler(InstancePtr->DpPtr, StubTp1Callback,
(void *)InstancePtr);
XDp_RxSetIntrTp2Handler(InstancePtr->DpPtr, StubTp2Callback,
(void *)InstancePtr);
XDp_RxSetIntrTp3Handler(InstancePtr->DpPtr, StubTp2Callback,
(void *)InstancePtr);
XDp_RxSetIntrUnplugHandler(InstancePtr->DpPtr,
StubUnplugCallback, (void *)InstancePtr);
/* Initialize configurable parameters */
InstancePtr->UsrOpt.Bpc = InstancePtr->Config.MaxBpc;
InstancePtr->UsrOpt.LaneCount =
InstancePtr->Config.MaxLaneCount;
InstancePtr->UsrOpt.LinkRate =
InstancePtr->DpPtr->Config.MaxLinkRate;
InstancePtr->UsrOpt.MstSupport =
InstancePtr->Config.MstSupport;
/* Populate the RX core's ports with default values */
DpRxSs_PopulateDpRxPorts(InstancePtr);
}
/* Set the flag to indicate the subsystem is ready */
InstancePtr->IsReady = (u32)(XIL_COMPONENT_IS_READY);
return XST_SUCCESS;
}
/*****************************************************************************/
/**
*
* This function resets the DisplayPort Receiver Subsystem including all
* sub-cores.
*
* @param InstancePtr is a pointer to the XDpRxSs core instance.
*
* @return None.
*
* @note IIC needs to be reinitialized after reset.
*
******************************************************************************/
void XDpRxSs_Reset(XDpRxSs *InstancePtr)
{
/* Verify argument. */
Xil_AssertVoid(InstancePtr != NULL);
/* Reset the video and AUX logic from DP RX */
XDpRxSs_WriteReg(InstancePtr->DpPtr->Config.BaseAddr,
XDP_RX_SOFT_RESET, XDP_RX_SOFT_RESET_VIDEO_MASK |
XDP_RX_SOFT_RESET_AUX_MASK);
/* Reset the IIC core */
XIic_Reset(InstancePtr->IicPtr);
}
/*****************************************************************************/
/**
*
* This function starts the DisplayPort Receiver Subsystem including all
* sub-cores.
*
* @param InstancePtr is a pointer to the XDpRxSs core instance.
*
* @return
* - XST_SUCCESS, if DP RX Subsystem and its included sub-cores
* configured successfully.
* - XST_FAILURE, otherwise.
*
* @note None.
*
******************************************************************************/
u32 XDpRxSs_Start(XDpRxSs *InstancePtr)
{
u32 Status;
/* Verify arguments. */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid((InstancePtr->UsrOpt.MstSupport == 0) ||
(InstancePtr->UsrOpt.MstSupport == 1));
/* Reinitialize DP */
Status = XDp_Initialize(InstancePtr->DpPtr);
if (Status != (XST_SUCCESS)) {
xdbg_printf((XDBG_DEBUG_GENERAL),"SS ERR::DP RX "
"start failed!\n\r");
Status = XST_FAILURE;
}
return Status;
}
/*****************************************************************************/
/**
*
* This function sets the data rate to be used by the DisplayPort RX Subsystem
* core.
*
* @param InstancePtr is a pointer to the XDpRxSs instance.
* @param LinkRate is the rate at which link needs to be driven.
* - XDPRXSS_LINK_BW_SET_162GBPS = 0x06(for a 1.62 Gbps data rate)
* - XDPRXSS_LINK_BW_SET_270GBPS = 0x0A(for a 2.70 Gbps data rate)
* - XDPRXSS_LINK_BW_SET_540GBPS = 0x14(for a 5.40 Gbps data rate)
*
* @return
* - XST_SUCCESS if setting the new lane rate was successful.
* - XST_FAILURE otherwise.
*
* @note None.
*
******************************************************************************/
u32 XDpRxSs_SetLinkRate(XDpRxSs *InstancePtr, u8 LinkRate)
{
/* Verify arguments. */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid((LinkRate == (XDPRXSS_LINK_BW_SET_162GBPS)) ||
(LinkRate == (XDPRXSS_LINK_BW_SET_270GBPS)) ||
(LinkRate == (XDPRXSS_LINK_BW_SET_540GBPS)));
/* Check for maximum supported link rate */
if (LinkRate > InstancePtr->DpPtr->Config.MaxLinkRate) {
xdbg_printf((XDBG_DEBUG_GENERAL),"SS info: This link rate is "
"not supported by Source/Sink.\n\rMax Supported link "
"rate is 0x%x.\n\rSetting maximum supported link "
"rate.\n\r", InstancePtr->DpPtr->Config.MaxLinkRate);
LinkRate = InstancePtr->DpPtr->Config.MaxLinkRate;
}
/* Set link rate */
XDp_RxSetLinkRate(InstancePtr->DpPtr, LinkRate);
InstancePtr->UsrOpt.LinkRate = LinkRate;
return XST_SUCCESS;
}
/*****************************************************************************/
/**
*
* This function sets the number of lanes to be used by DisplayPort RX Subsystem
* core.
*
* @param InstancePtr is a pointer to the XDpRxSs instance.
* @param LaneCount is the number of lanes to be used.
* - 1 = XDPRXSS_LANE_COUNT_SET_1
* - 2 = XDPRXSS_LANE_COUNT_SET_2
* - 4 = XDPRXSS_LANE_COUNT_SET_4
* @return
* - XST_SUCCESS if setting the new lane count was successful.
* - XST_FAILURE otherwise.
*
* @note None.
*
******************************************************************************/
u32 XDpRxSs_SetLaneCount(XDpRxSs *InstancePtr, u8 LaneCount)
{
/* Verify arguments. */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid((LaneCount == (XDPRXSS_LANE_COUNT_SET_1)) ||
(LaneCount == (XDPRXSS_LANE_COUNT_SET_2)) ||
(LaneCount == (XDPRXSS_LANE_COUNT_SET_4)));
/* Check for maximum supported lane count */
if (LaneCount > InstancePtr->DpPtr->Config.MaxLaneCount) {
xdbg_printf((XDBG_DEBUG_GENERAL),"SS info: This lane count is "
"not supported by Source/Sink.\n\rMax Supported lane "
"count is 0x%x.\n\rSetting maximum supported lane "
"count.\n\r", InstancePtr->DpPtr->Config.MaxLaneCount);
LaneCount = InstancePtr->DpPtr->Config.MaxLaneCount;
}
/* Set lane count */
XDp_RxSetLaneCount(InstancePtr->DpPtr, LaneCount);
InstancePtr->UsrOpt.LaneCount = LaneCount;
return XST_SUCCESS;
}
/*****************************************************************************/
/**
*
* This function allows the user to select number of ports to be exposed when
* replying to a LINK_ADDRESS sideband message and hides rest of the ports.
*
* @param InstancePtr is a pointer to the XDpRxSs core instance.
* @param Port specifies the number of ports to be exposed within the
* range 1 to 4.
*
* @return
* - XST_SUCCESS, if ports exposed successfully.
* - XST_FAILURE, if exposing ports which are already exposed or
* ports are exceeding total number of stream supported by the
* system.
*
* @note Number of ports are equal to number of streams.
*
******************************************************************************/
u32 XDpRxSs_ExposePort(XDpRxSs *InstancePtr, u8 Port)
{
u32 Status;
u8 PortIndex;
/* Verify arguments. */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(Port > 0x0);
if (Port == InstancePtr->UsrOpt.NumOfStreams) {
xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO:Subsystem is "
"already in %s mode with port[s] %d.\n\r",
InstancePtr->UsrOpt.MstSupport? "MST": "SST",
Port);
Status = XST_FAILURE;
}
/* Check for stream[s] less than supported stream[s] */
else if (Port < InstancePtr->Config.NumMstStreams) {
/* Expose each port */
for (PortIndex = 0; PortIndex < Port; PortIndex++) {
/* Expose the ports configured above. Used when
* replying to a LINK_ADDRESS request. Make sure that
* the number of downstream ports matches the number
* exposed, otherwise the LINK_ADDRESS reply will be
* incorrect
*/
XDp_RxMstExposePort(InstancePtr->DpPtr,
PortIndex + 1, 1);
}
/* Set number of ports/stream[s] are exposed */
InstancePtr->UsrOpt.NumOfStreams = Port;
/* Hide remaining ports */
for (PortIndex = Port;
PortIndex <= InstancePtr->Config.NumMstStreams;
PortIndex++) {
XDp_RxMstExposePort(InstancePtr->DpPtr,
PortIndex + 1, 0);
}
Status = XST_SUCCESS;
}
/* Everything else */
else {
xdbg_printf((XDBG_DEBUG_GENERAL),"SS ERR::Subsystem does not "
"support %s mode with stream[s] %d\n\r",
InstancePtr->UsrOpt.MstSupport? "MST": "SST",
Port);
Status = XST_FAILURE;
}
return Status;
}
/*****************************************************************************/
/**
*
* This function checks if the receiver's DisplayPort Configuration Data (DPCD)
* indicates that the receiver has achieved clock recovery, channel
* equalization, symbol lock, and interlane alignment for all lanes currently
* in use.
*
* @param InstancePtr is a pointer to the XDpRxSs core instance.
*
* @return
* - XST_SUCCESS if the RX device has achieved clock recovery,
* channel equalization, symbol lock, and interlane alignment.
* - XST_DEVICE_NOT_FOUND if no RX device is connected.
* - XST_FAILURE otherwise.
*
* @note None.
*
******************************************************************************/
u32 XDpRxSs_CheckLinkStatus(XDpRxSs *InstancePtr)
{
u32 Status;
/* Verify argument.*/
Xil_AssertNonvoid(InstancePtr != NULL);
/* Check link status */
Status = XDp_RxCheckLinkStatus(InstancePtr->DpPtr);
return Status;
}
/*****************************************************************************/
/**
*
* This function configures the number of pixels output through the user data
* interface.
*
* @param InstancePtr is a pointer to the XDpRxSs core instance.
* @param UserPixelWidth is the user pixel width to be configured.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XDpRxSs_SetUserPixelWidth(XDpRxSs *InstancePtr, u8 UserPixelWidth)
{
/* Verify arguments.*/
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid((UserPixelWidth == 1) || (UserPixelWidth == 2) ||
(UserPixelWidth == 4));
/* Set user pixel width */
XDp_RxSetUserPixelWidth(InstancePtr->DpPtr, UserPixelWidth);
}
/*****************************************************************************/
/**
*
* This function handles incoming sideband messages. It will
* 1) Read the contents of the down request registers,
* 2) Delegate control depending on the request type, and
* 3) Send a down reply.
*
* @param InstancePtr is a pointer to the XDpRxSs core instance.
*
* @return
* - XST_SUCCESS if the entire message was sent successfully.
* - XST_DEVICE_NOT_FOUND if no device is connected.
* - XST_ERROR_COUNT_MAX if sending one of the message fragments
* timed out.
* - XST_FAILURE otherwise.
*
* @note None.
*
******************************************************************************/
u32 XDpRxSs_HandleDownReq(XDpRxSs *InstancePtr)
{
u32 Status;
/* Verify argument.*/
Xil_AssertNonvoid(InstancePtr != NULL);
Status = XDp_RxHandleDownReq(InstancePtr->DpPtr);
return Status;
}
/*****************************************************************************/
/**
*
* This function reports list of cores included in DisplayPort RX Subsystem.
*
* @param InstancePtr is a pointer to the XDpRxSs core instance.
*
* @return None.
*
* @note None.
*
******************************************************************************/
static void DpRxSs_GetIncludedSubCores(XDpRxSs *InstancePtr)
{
/* Assign instance of DisplayPort core */
InstancePtr->DpPtr = ((InstancePtr->Config.DpSubCore.IsPresent)?
(&DpRxSsSubCores.DpInst): NULL);
/* Assign instance of IIC core */
InstancePtr->IicPtr = ((InstancePtr->Config.DpSubCore.IsPresent)?
(&DpRxSsSubCores.IicInst): NULL);
}
/*****************************************************************************/
/**
*
* This function sets up the downstream topology that will be used by the
* DisplayPort RX to respond to down requests coming from the TX.
* - Sinks equal to number of streams (each with its own global unique
* identifier) are exposed to LINK_ADDRESS sideband messages.
* - The extended display identification data (EDID) will be set to a generic
* EDID (GenEdid) for each of the sinks. REMOTE_I2C_READ sideband messages
* on address 0x50 will be replied to with the contents set by
* XDp_RxSetIicMapEntry for 0x50.
* - REMOTE_DPCD_READ sideband messages will be responded to with the contents
* set for the sink using XDp_RxSetDpcdMap. All sinks are given the a generic
* DPCD (GenDpcd).
* - ENUM_PATH_RESOURCES sideband messages will be responded to with the value
* set by XDp_RxMstSetPbn (or 0 if the sink already has a stream allocated to
* it).
*
* @param InstancePtr is a pointer to the XDpRxSs core instance.
*
* @return None.
*
* @note None.
*
******************************************************************************/
static void DpRxSs_PopulateDpRxPorts(XDpRxSs *InstancePtr)
{
XDp_SbMsgLinkAddressReplyPortDetail Port;
u8 PortIndex;
u8 GuidIndex;
u8 StreamIndex;
/* Check for MST */
if (InstancePtr->Config.MstSupport) {
/* Ensure that all ports are not exposed in the link address */
for (PortIndex = 0; PortIndex < XDP_MAX_NPORTS; PortIndex++) {
XDp_RxMstExposePort(InstancePtr->DpPtr, PortIndex, 0);
}
/* Configure the commonality between the downstream sink
* devices
*/
Port.InputPort = 0;
Port.PeerDeviceType = 0x3;
Port.MsgCapStatus = 0;
Port.DpDevPlugStatus = 1;
Port.LegacyDevPlugStatus = 0;
Port.DpcdRev = 0x11;
Port.NumSdpStreams = InstancePtr->Config.MaxNumAudioCh;
Port.NumSdpStreamSinks = InstancePtr->Config.MaxNumAudioCh;
/* Configure the unique port number and GUID for all possible
* downstream sinks
*/
for (PortIndex = 1; PortIndex < XDPRXSS_MAX_NPORTS;
PortIndex++) {
/* Set the GUID to a repeating pattern of the port
* number
*/
for (GuidIndex = 0; GuidIndex < XDPRXSS_GUID_NBYTES;
GuidIndex++) {
Port.Guid[GuidIndex] = PortIndex;
}
/* Port.PortNum is set to the index. */
XDp_RxMstSetPort(InstancePtr->DpPtr, PortIndex, &Port);
}
/* Configure each port with I2C, DPCD and PBN values */
for (StreamIndex = 0;
StreamIndex < InstancePtr->Config.NumMstStreams;
StreamIndex++) {
/* Set I2C maps. */
XDp_RxSetIicMapEntry(InstancePtr->DpPtr,
StreamIndex + 1, 0x50, 128, GenEdid);
/* Set DPCD maps. */
XDp_RxSetDpcdMap(InstancePtr->DpPtr, StreamIndex + 1,
0, sizeof(GenDpcd), GenDpcd);
/* Set available PBN. */
XDp_RxMstSetPbn(InstancePtr->DpPtr, StreamIndex + 1,
2560);
/* Expose the ports configured above. Used when
* replying to a LINK_ADDRESS request. Make sure that
* the number of downstream ports matches the number
* exposed, otherwise the LINK_ADDRESS reply will be
* incorrect
*/
XDp_RxMstExposePort(InstancePtr->DpPtr,
StreamIndex + 1, 1);
}
/* Set up the input port and expose it */
XDp_RxMstSetInputPort(InstancePtr->DpPtr, 0, NULL);
}
}
/*****************************************************************************/
/**
*
* This routine is a stub for the asynchronous training pattern 1 interrupt
* callback. On initialization, training pattern 1 interrupt handler is set to
* this callback. It is considered as an training pattern 1 for this handler
* to be invoked.
*
* @param InstancePtr is a pointer to the XDpRxSs core instance.
*
* @return None.
*
* @note None.
*
******************************************************************************/
static void StubTp1Callback(void *InstancePtr)
{
XDpRxSs *DpRxSsPtr = (XDpRxSs *)InstancePtr;
/* Verify argument.*/
Xil_AssertVoid(DpRxSsPtr != NULL);
/* Read link rate */
DpRxSsPtr->UsrOpt.LinkRate =
XDpRxSs_ReadReg(DpRxSsPtr->DpPtr->Config.BaseAddr,
XDPRXSS_DPCD_LINK_BW_SET);
/* Read lane count */
DpRxSsPtr->UsrOpt.LaneCount =
XDpRxSs_ReadReg(DpRxSsPtr->DpPtr->Config.BaseAddr,
XDPRXSS_DPCD_LANE_COUNT_SET);
/* Link bandwidth callback */
if (DpRxSsPtr->LinkBwCallback) {
DpRxSsPtr->LinkBwCallback(DpRxSsPtr->LinkBwRef);
}
/* DP159 config for TP1 */
XVidC_Dp159Config(DpRxSsPtr->IicPtr, XVIDC_DP159_CT_TP1,
DpRxSsPtr->UsrOpt.LinkRate,
DpRxSsPtr->UsrOpt.LaneCount);
XDpRxSs_WriteReg(DpRxSsPtr->DpPtr->Config.BaseAddr,
XDPRXSS_RX_PHY_CONFIG, 0x3800000);
/* PLL reset callback */
if (DpRxSsPtr->PllResetCallback) {
DpRxSsPtr->PllResetCallback(DpRxSsPtr->PllResetRef);
}
/* Set vertical blank */
DpRxSsPtr->VBlankEnable = 1;
/* Enable vertical blank interrupt */
XDp_RxInterruptEnable(DpRxSsPtr->DpPtr, XDPRXSS_INTR_VBLANK_MASK);
/* Set vertical blank count */
DpRxSsPtr->VBlankCount = 0;
}
/*****************************************************************************/
/**
*
* This routine is a stub for the asynchronous training pattern 2 interrupt
* callback. On initialization, training pattern 2 interrupt handler is set to
* this callback. It is considered as an training pattern 2 for this handler
* to be invoked.
*
* @param InstancePtr is a pointer to the XDpRxSs core instance.
*
* @return None.
*
* @note None.
*
******************************************************************************/
static void StubTp2Callback(void *InstancePtr)
{
XDpRxSs *DpRxSsPtr = (XDpRxSs *)InstancePtr;
/* Verify argument.*/
Xil_AssertVoid(DpRxSsPtr != NULL);
/* DP159 config for TP2 */
XVidC_Dp159Config(DpRxSsPtr->IicPtr, XVIDC_DP159_CT_TP2,
DpRxSsPtr->UsrOpt.LinkRate,
DpRxSsPtr->UsrOpt.LaneCount);
}
/*****************************************************************************/
/**
*
* This routine is a stub for the asynchronous unplug interrupt callback.
* On initialization, unplug interrupt handler is set to this callback. It is
* considered as an unplug for this handler to be invoked.
*
* @param InstancePtr is a pointer to the XDpRxSs core instance.
*
* @return None.
*
* @note None.
*
******************************************************************************/
static void StubUnplugCallback(void *InstancePtr)
{
XDpRxSs *DpRxSsPtr = (XDpRxSs *)InstancePtr;
/* Verify argument.*/
Xil_AssertVoid(DpRxSsPtr != NULL);
/* DP159 config for TP2 */
XVidC_Dp159Config(DpRxSsPtr->IicPtr, XVIDC_DP159_CT_UNPLUG,
DpRxSsPtr->UsrOpt.LinkRate, DpRxSsPtr->UsrOpt.LaneCount);
/* Disable unplug interrupt so that no unplug event when RX is
* disconnected
*/
XDp_RxInterruptDisable(DpRxSsPtr->DpPtr,
XDP_RX_INTERRUPT_MASK_UNPLUG_MASK);
/* Unplug event callback */
if (DpRxSsPtr->UnplugCallback) {
DpRxSsPtr->UnplugCallback(DpRxSsPtr->UnplugRef);
}
}

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/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xdprxss.h
*
* This is the main header file for Xilinx DisplayPort Receiver Subsystem core.
* It abstracts Subsystem cores and provides high level API's to application
* developer.
*
* <b>Core Features</b>
*
* For a full description of DisplayPort Receiver Subsystem core, please
* see the hardware specification.
*
* <b>Software Initialization & Configuration</b>
*
* The application needs to do following steps in order for preparing the
* DisplayPort Receiver Subsystem core to be ready.
*
* - Call XDpRxSs_LookupConfig using a device ID to find the core
* configuration.
* - Call XDpRxSs_CfgInitialize to initialize the device and the driver
* instance associated with it.
*
* <b>Interrupts</b>
*
* The DisplayPort RX Subsystem driver provides an interrupt handler
* XDpRxSs_DpIntrHandler for handling the interrupt from the DisplayPort
* sub-core. The users of this driver have to register this handler with
* the interrupt system and provide the callback functions by using
* XDpRxSs_SetCallBack API.
*
* <b>Virtual Memory</b>
*
* This driver supports Virtual Memory. The RTOS is responsible for calculating
* the correct device base address in Virtual Memory space.
*
* <b>Threads</b>
*
* This driver is not thread safe. Any needs for threads or thread mutual
* exclusion must be satisfied by the layer above this driver.
*
* <b>Asserts</b>
*
* Asserts are used within all Xilinx drivers to enforce constraints on argument
* values. Asserts can be turned off on a system-wide basis by defining at
* compile time, the NDEBUG identifier. By default, asserts are turned on and it
* is recommended that users leave asserts on during development.
*
* <b>Building the driver</b>
*
* The DisplayPort Receiver Subsystem driver is composed of several source
* files. This allows the user to build and link only those parts of the driver
* that are necessary.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ---- --- -------- -----------------------------------------------------
* 1.00 sha 05/18/15 Initial release.
* </pre>
*
******************************************************************************/
#ifndef XDPRXSS_H_
#define XDPRXSS_H_ /**< Prevent circular inclusions
* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xdprxss_hw.h"
#include "xil_assert.h"
#include "xstatus.h"
/* Subsystem sub-cores header files */
#include "xdprxss_dprx.h"
#include "xdprxss_iic.h"
#include "xdprxss_hdcp1x.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/**
* These constants specify different types of handler and used to differentiate
* interrupt requests from sub-cores.
*/
typedef enum {
XDPRXSS_HANDLER_DP_VM_CHG_EVENT = 1, /**< Video mode change event
* interrupt type for
* DisplayPort core */
XDPRXSS_HANDLER_DP_PWR_CHG_EVENT = 2, /**< Power state change
* interrupt type for
* DisplayPort core */
XDPRXSS_HANDLER_DP_NO_VID_EVENT = 3, /**< No video event
* interrupt type for
* DisplayPort core */
XDPRXSS_HANDLER_DP_VBLANK_EVENT = 4, /**< Vertical blanking event
* interrupt type for
* DisplayPort core */
XDPRXSS_HANDLER_DP_TLOST_EVENT = 5, /**< Training lost event
* interrupt type for
* DisplayPort core */
XDPRXSS_HANDLER_DP_VID_EVENT = 6, /**< Valid video event
* interrupt type for
* DisplayPort core */
XDPRXSS_HANDLER_DP_INFO_PKT_EVENT = 7, /**< Info packet event
* interrupt type for
* DisplayPort core */
XDPRXSS_HANDLER_DP_EXT_PKT_EVENT = 8, /**< Extension packet event
* interrupt type for
* DisplayPort core */
XDPRXSS_HANDLER_DP_TDONE_EVENT = 9, /**< Training done event
* interrupt type for
* DisplayPort core */
XDPRXSS_HANDLER_DP_BW_CHG_EVENT = 10, /**< Bandwidth change event
* interrupt type for
* DisplayPort core */
XDPRXSS_HANDLER_DP_DWN_REQ_EVENT = 11, /**< Down request event
* interrupt type for
* DisplayPort core */
XDPRXSS_HANDLER_DP_DWN_REP_EVENT = 12, /**< Down reply event
* interrupt type for
* DisplayPort core */
XDPRXSS_HANDLER_DP_AUD_OVRFLW_EVENT = 13, /**< Audio packet overflow
* event interrupt type for
* DisplayPort core */
XDPRXSS_HANDLER_DP_PAYLOAD_ALLOC_EVENT = 14, /**< Payload allocation
* event interrupt
* type for
* DisplayPort
* core */
XDPRXSS_HANDLER_DP_ACT_RX_EVENT = 15, /**< ACT sequence received
* event interrupt type for
* DisplayPort core */
XDPRXSS_HANDLER_DP_CRC_TEST_EVENT = 16, /**< CRC test start event
* interrupt type for
* DisplayPort core */
XDPRXSS_HANDLER_DP_HDCP_DBG_WR_EVENT = 17, /**< HDCP debug
* register write
* event interrupt
* type for
* DisplayPort
* core */
XDPRXSS_HANDLER_DP_HDCP_AKSV_WR_EVENT = 18, /**< HDCP AKSV MSB
* register write
* event interrupt
* type for
* DisplayPort
* core */
XDPRXSS_HANDLER_DP_HDCP_AN_WR_EVENT = 19, /**< HDCP AN MSB
* register write
* event interrupt
* type for
* DisplayPort
* core */
XDPRXSS_HANDLER_DP_HDCP_A_INFO_WR_EVENT = 20, /**< HDCP A info
* register write
* event interrupt
* type for
* DisplayPort
* core */
XDPRXSS_HANDLER_DP_HDCP_RO_RD_EVENT = 21, /**< HDCP RO register
* read event
* interrupt type for
* DisplayPort
* core */
XDPRXSS_HANDLER_DP_HDCP_B_INFO_RD_EVENT = 22, /**< HDCP B info
* register read
* event interrupt
* type for
* DisplayPort
* core */
XDPRXSS_HANDLER_UNPLUG_EVENT = 23, /**< Unplug event type for
* DisplayPort RX
* Subsystem */
XDPRXSS_HANDLER_LINKBW_EVENT = 24, /**< Link BW event type for
* DisplayPort RX Subsystem
*/
XDPRXSS_HANDLER_PLL_RESET_EVENT = 25 /**< PLL reset event type for
* DisplayPort RX Subsystem
*/
} XDpRxSs_HandlerType;
/**
* User input structure
*/
typedef struct {
u8 Bpc; /**< Bits per color */
u8 LaneCount; /**< Lane count */
u8 LinkRate; /**< Link rate */
u8 MstSupport; /**< Multi-stream transport (MST) support */
u8 NumOfStreams; /**< The total number of MST streams */
} XDpRxSs_UsrOpt;
/**
* DisplayPort Sub-core structure.
*/
typedef struct {
u16 IsPresent; /**< Flag to hold the presence of DisplayPort
* Receiver core. */
XDp_Config DpConfig; /**< DisplayPort core configuration
* information */
} XDpRxSs_DpSubCore;
/**
* IIC Sub-core structure.
*/
typedef struct {
u16 IsPresent; /**< Flag to hold the presence of DisplayPort
* Receiver core. */
XIic_Config IicConfig; /**< IIC core configuration
* information */
} XDpRxSs_IicSubCore;
/**
* High-Bandwidth Content Protection (HDCP) Sub-core structure.
*/
typedef struct {
u16 IsPresent; /**< Flag to hold the presence of HDCP core. */
XHdcp1x_Config Hdcp1xConfig; /**< HDCP core configuration
* information */
} XDpRxSs_Hdcp1xSubCore;
/**
* This typedef contains configuration information for the DisplayPort
* Receiver Subsystem core. Each DisplayPort RX Subsystem core should have
* a configuration structure associated.
*/
typedef struct {
u16 DeviceId; /**< DeviceId is the unique ID of the
* DisplayPort RX Subsystem core */
u32 BaseAddress; /**< BaseAddress is the physical base address
* of the core's registers */
u8 SecondaryChEn; /**< This Subsystem core supports audio packets
* being sent by the secondary channel. */
u8 MaxNumAudioCh; /**< The total number of Audio channels
* supported by this core instance. */
u8 MaxBpc; /**< The maximum bits/color supported by this
* Subsystem core */
u8 HdcpEnable; /**< This Subsystem core supports digital
* content protection. */
u8 MaxLaneCount; /**< The maximum lane count supported by this
* core instance. */
u8 MstSupport; /**< Multi-stream transport (MST) mode is
* enabled by this core instance. */
u8 NumMstStreams; /**< The total number of MST streams supported
* by this core instance. */
u8 ColorFormat; /**< Type of color format supported by this
* core instance. */
XDpRxSs_DpSubCore DpSubCore; /**< DisplayPort Configuration */
XDpRxSs_Hdcp1xSubCore Hdcp1xSubCore; /**< HDCP Configuration */
XDpRxSs_IicSubCore IicSubCore; /**< IIC Configuration */
} XDpRxSs_Config;
/*****************************************************************************/
/**
*
* Callback type which represents the handler for events.
*
* @param InstancePtr is a pointer to the XDpRxSs instance.
*
* @note None.
*
******************************************************************************/
typedef void (*XDpRxSs_Callback)(void *InstancePtr);
/**
* The DisplayPort RX Subsystem driver instance data. An instance must be
* allocated for each core in use.
*/
typedef struct {
XDpRxSs_Config Config; /**< Hardware Configuration */
u32 IsReady; /**< Core and the driver instance are
* initialized */
/* Sub-core instances */
XDp *DpPtr; /**< DisplayPort sub-core instance */
XIic *IicPtr; /**< IIC sub-core instance */
/* Callback */
XDpRxSs_Callback PllResetCallback; /**< Callback function for PLL
* reset */
void *PllResetRef; /**< A pointer to the user data passed
* to the PLL reset callback
* function */
XDpRxSs_Callback LinkBwCallback; /**< Callback function for
* link bandwidth */
void *LinkBwRef; /**< A pointer to the user data passed
* to the link bandwidth callback
* function */
XDpRxSs_Callback UnplugCallback; /**< Callback function for
* unplug event */
void *UnplugRef; /**< A pointer to the user data passed
* to the unplug event callback
* function */
/* Vertical blank */
u8 VBlankEnable; /**< Vertical Blank Enable */
u8 VBlankCount; /**< Vertical Blank Count */
/* User options */
XDpRxSs_UsrOpt UsrOpt; /**< User Options structure */
} XDpRxSs;
/***************** Macros (Inline Functions) Definitions *********************/
/**
* Callback type which represents a custom timer wait handler.
*/
#define XDpRxSs_TimerHandler XDp_TimerHandler
/*****************************************************************************/
/**
*
* This function macro enables the display timing generator (DTG).
*
* @param InstancePtr is a pointer to the XDpRxSs core instance.
*
* @return None.
*
* @note C-style signature:
* void XDpRxSs_DtgEnable(XDpRxSs *InstancePtr)
*
******************************************************************************/
#define XDpRxSs_DtgEnable(InstancePtr) XDp_RxDtgEn((InstancePtr)->DpPtr)
/*****************************************************************************/
/**
*
* This function macro disables the display timing generator (DTG).
*
* @param InstancePtr is a pointer to the XDpRxSs core instance.
*
* @return None.
*
* @note C-style signature:
* void XDpRxSs_DtgDisable(XDpRxSs *InstancePtr)
*
******************************************************************************/
#define XDpRxSs_DtgDisable(InstancePtr) XDp_RxDtgDis((InstancePtr)->DpPtr)
/*****************************************************************************/
/**
*
* This function macro enables audio stream packets on the main link.
*
* @param InstancePtr is a pointer to the XDpRxSs core instance.
*
* @return None.
*
* @note C-style signature:
* void XDpRxSs_AudioEnable(XDpRxSs *InstancePtr)
*
******************************************************************************/
#define XDpRxSs_AudioEnable(InstancePtr) \
XDp_RxAudioEn((InstancePtr)->DpPtr)
/*****************************************************************************/
/**
*
* This function macro disables audio stream packets on the main link.
*
* @param InstancePtr is a pointer to the XDpRxSs core instance.
*
* @return None.
*
* @note C-style signature:
* void XDpRxSs_AudioDisable(XDpRxSs *InstancePtr)
*
******************************************************************************/
#define XDpRxSs_AudioDisable(InstancePtr) \
XDp_RxAudioDis((InstancePtr)->DpPtr)
/*****************************************************************************/
/**
*
* This function macro resets the reception of audio stream packets on the
* main link.
*
* @param InstancePtr is a pointer to the XDpRxSs core instance.
*
* @return None.
*
* @note C-style signature:
* void XDpRxSs_AudioReset(XDpRxSs *InstancePtr)
*
******************************************************************************/
#define XDpRxSs_AudioReset(InstancePtr) \
XDp_RxAudioReset((InstancePtr)->DpPtr)
/******************************************************************************/
/**
*
* This function macro is the delay/sleep function for the XDpRxSs driver.
*
* @param InstancePtr is a pointer to the XDpRxSs core instance.
* @param MicroSeconds is the number of microseconds to delay/sleep for.
*
* @return None.
*
* @note C-style signature:
* void XDpRxSs_WaitUs(XDpRxSs *InstancePtr)
*
*******************************************************************************/
#define XDpRxSs_WaitUs(InstancePtr, MicroSeconds) \
XDp_WaitUs((InstancePtr)->DpPtr, MicroSeconds)
/************************** Function Prototypes ******************************/
/* Initialization function in xdprxss_sinit.c */
XDpRxSs_Config* XDpRxSs_LookupConfig(u16 DeviceId);
/* Initialization and control functions in xdprxss.c */
u32 XDpRxSs_CfgInitialize(XDpRxSs *InstancePtr, XDpRxSs_Config *CfgPtr,
u32 EffectiveAddr);
u32 XDpRxSs_Start(XDpRxSs *InstancePtr);
void XDpRxSs_Reset(XDpRxSs *InstancePtr);
u32 XDpRxSs_SetLinkRate(XDpRxSs *InstancePtr, u8 LinkRate);
u32 XDpRxSs_SetLaneCount(XDpRxSs *InstancePtr, u8 LaneCount);
u32 XDpRxSs_ExposePort(XDpRxSs *InstancePtr, u8 Port);
u32 XDpRxSs_CheckLinkStatus(XDpRxSs *InstancePtr);
u32 XDpRxSs_HandleDownReq(XDpRxSs *InstancePtr);
void XDpRxSs_SetUserPixelWidth(XDpRxSs *InstancePtr, u8 UserPixelWidth);
void XDpRxSs_ReportCoreInfo(XDpRxSs *InstancePtr);
void XDpRxSs_ReportLinkInfo(XDpRxSs *InstancePtr);
void XDpRxSs_ReportMsaInfo(XDpRxSs *InstancePtr);
void XDpRxSs_ReportDp159BitErrCount(XDpRxSs *InstancePtr);
/* Self test function in xdprxss_selftest.c */
u32 XDpRxSs_SelfTest(XDpRxSs *InstancePtr);
/* Interrupt functions in xdprxss_intr.c */
void XDpRxSs_DpIntrHandler(void *InstancePtr);
u32 XDpRxSs_SetCallBack(XDpRxSs *InstancePtr, u32 HandlerType,
void *CallbackFunc, void *CallbackRef);
void XDpRxSs_SetUserTimerHandler(XDpRxSs *InstancePtr,
XDpRxSs_TimerHandler CallbackFunc, void *CallbackRef);
/************************** Variable Declarations ****************************/
#ifdef __cplusplus
}
#endif
#endif /* End of protection macro */

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/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xdprxss_dbg.c
*
* This file contains functions to report debug information of DisplayPort RX
* Subsystem sub-cores.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ---- --- -------- -----------------------------------------------------
* 1.00 sha 05/18/15 Initial release.
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xdprxss.h"
#include "xvidc_dp159.h"
#include "xdebug.h"
/************************** Constant Definitions *****************************/
/***************** Macros (Inline Functions) Definitions *********************/
/**************************** Type Definitions *******************************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/************************** Function Definitions *****************************/
/*****************************************************************************/
/**
*
* This function reports list of sub-cores included in DisplayPort RX Subsystem.
*
* @param InstancePtr is a pointer to the XDpRxSs core instance.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XDpRxSs_ReportCoreInfo(XDpRxSs *InstancePtr)
{
/* Verify argument. */
Xil_AssertVoid(InstancePtr != NULL);
xil_printf("\n\rDisplayPort RX Subsystem info:\n\r");
/* Report all the included cores in the subsystem instance */
if (InstancePtr->DpPtr) {
xil_printf("DisplayPort Receiver(DPRX):Yes\n\r");
}
if (InstancePtr->IicPtr) {
xil_printf("IIC:Yes\n\r");
}
xil_printf("Audio enabled:%s\n\r",
InstancePtr->Config.SecondaryChEn? "Yes": "No");
xil_printf("Max supported audio channels:%d\n\r",
InstancePtr->Config.MaxNumAudioCh);
xil_printf("Max supported bits per color:%d\n\r",
InstancePtr->Config.MaxBpc);
xil_printf("Supported color format:%d\n\r",
InstancePtr->Config.ColorFormat);
xil_printf("HDCP enabled:%s\n\r",
InstancePtr->Config.HdcpEnable? "Yes": "No");
xil_printf("Max supported lane count:%d\n\r",
InstancePtr->Config.MaxLaneCount);
xil_printf("Max supported link rate:%d\n\r",
InstancePtr->DpPtr->Config.MaxLinkRate);
xil_printf("Multi-Stream Transport mode:%s\n\r",
InstancePtr->Config.MstSupport? "Yes": "No (SST)");
xil_printf("Max number of supported streams:%d\n\r",
InstancePtr->Config.NumMstStreams);
xil_printf("DP RX Subsystem is running in: %s with streams %d\n\r",
InstancePtr->UsrOpt.MstSupport? "MST": "SST",
InstancePtr->UsrOpt.NumOfStreams);
xil_printf("\n\r");
}
/*****************************************************************************/
/**
*
* This function prints the link status, selected resolution, link rate /lane
* count symbol error.
*
* @param InstancePtr is a pointer to the XDpRxSs core instance.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XDpRxSs_ReportLinkInfo(XDpRxSs *InstancePtr)
{
XDp_Config *RxConfig = &InstancePtr->DpPtr->Config;
/* Verify argument. */
Xil_AssertVoid(InstancePtr != NULL);
/* Read link rate and lane count */
xil_printf("\n\rLINK_BW_SET (0x09C) status in DPCD = 0x%x\n\r",
XDpRxSs_ReadReg(RxConfig->BaseAddr,
XDP_RX_OVER_LINK_BW_SET));
xil_printf("\n\rLANE_COUNT_SET (0x0A0) status in DPCD = 0x%x\n\r",
XDpRxSs_ReadReg(RxConfig->BaseAddr,
XDP_RX_OVER_LANE_COUNT_SET));
/* Read lanes status */
xil_printf("LANE0_1_STATUS (0x043C) in DPCD = 0x%x\n\r",
XDpRxSs_ReadReg(RxConfig->BaseAddr,
XDP_RX_DPCD_LANE01_STATUS));
xil_printf("LANE2_3_STATUS (0x440) in DPCD = 0x%x\n\r",
XDpRxSs_ReadReg(RxConfig->BaseAddr,
XDP_RX_DPCD_LANE23_STATUS));
/* Read symbol error */
xil_printf("SYM_ERR_CNT01 (0x448) = 0x%x\n\r"
"SYM_ERR_CNT23 (0x44C) = 0x%x\n\r",
XDpRxSs_ReadReg(RxConfig->BaseAddr,
XDP_RX_DPCD_SYM_ERR_CNT01),
XDpRxSs_ReadReg(RxConfig->BaseAddr,
XDP_RX_DPCD_SYM_ERR_CNT23));
/* PHY status */
xil_printf("PHY_STATUS (0x208) = 0x%x\n\r",
XDpRxSs_ReadReg(RxConfig->BaseAddr, XDP_RX_PHY_STATUS));
xil_printf("\n\r");
}
/*****************************************************************************/
/**
*
* This function prints the current main stream attributes from the DisplayPort
* RX core.
*
* @param InstancePtr is a pointer to the XDpRxSs core instance.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XDpRxSs_ReportMsaInfo(XDpRxSs *InstancePtr)
{
XDp_Config *RxConfig = &InstancePtr->DpPtr->Config;
/* Verify argument. */
Xil_AssertVoid(InstancePtr != NULL);
xil_printf("RX MSA registers:\n\r"
"\tClocks, H Total (0x510) : %d\n\r"
"\tClocks, V Total (0x524) : %d\n\r"
"\tHSyncPolarity (0x504) : %d\n\r"
"\tVSyncPolarity (0x528) : %d\n\r"
"\tHSync Width (0x508) : %d\n\r"
"\tVSync Width (0x51C) : %d\n\r"
"\tHorz Resolution (0x500) : %d\n\r"
"\tVert Resolution (0x514) : %d\n\r"
"\tHorz Start (0x50C) : %d\n\r"
"\tVert Start (0x520) : %d\n\r"
"\tMisc0 (0x528) : 0x%08X\n\r"
"\tMisc1 (0x52C) : 0x%08X\n\r"
"\tUser Pixel Width (0x010) : %d\n\r"
"\tM Vid (0x530) : %d\n\r"
"\tN Vid (0x534) : %d\n\r"
"\tVB-ID (0x538) : %d\n\r",
XDp_ReadReg(RxConfig->BaseAddr, XDP_RX_MSA_HTOTAL),
XDp_ReadReg(RxConfig->BaseAddr, XDP_RX_MSA_VTOTAL),
XDp_ReadReg(RxConfig->BaseAddr, XDP_RX_MSA_HSPOL),
XDp_ReadReg(RxConfig->BaseAddr, XDP_RX_MSA_VSPOL),
XDp_ReadReg(RxConfig->BaseAddr, XDP_RX_MSA_HSWIDTH),
XDp_ReadReg(RxConfig->BaseAddr, XDP_RX_MSA_VSWIDTH),
XDp_ReadReg(RxConfig->BaseAddr, XDP_RX_MSA_HRES),
XDp_ReadReg(RxConfig->BaseAddr, XDP_RX_MSA_VHEIGHT),
XDp_ReadReg(RxConfig->BaseAddr, XDP_RX_MSA_HSTART),
XDp_ReadReg(RxConfig->BaseAddr, XDP_RX_MSA_VSTART),
XDp_ReadReg(RxConfig->BaseAddr, XDP_RX_MSA_MISC0),
XDp_ReadReg(RxConfig->BaseAddr, XDP_RX_MSA_MISC1),
XDp_ReadReg(RxConfig->BaseAddr, XDP_RX_USER_PIXEL_WIDTH),
XDp_ReadReg(RxConfig->BaseAddr, XDP_RX_MSA_MVID),
XDp_ReadReg(RxConfig->BaseAddr, XDP_RX_MSA_NVID),
XDp_ReadReg(RxConfig->BaseAddr, XDP_RX_MSA_VBID));
xil_printf("\n\r");
}
/*****************************************************************************/
/**
*
* This function prints the bit error encountered in DP159.
*
* @param InstancePtr is a pointer to the XDpRxSs core instance.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XDpRxSs_ReportDp159BitErrCount(XDpRxSs *InstancePtr)
{
u8 Data;
/* Verify argument. */
Xil_AssertVoid(InstancePtr != NULL);
/* Select page 0 */
XVidC_Dp159Write(InstancePtr->IicPtr, XVIDC_DP159_IIC_SLAVE,
0xFF, 0x00);
/* Read TST_INT/Q */
XVidC_Dp159Read(InstancePtr->IicPtr, XVIDC_DP159_IIC_SLAVE,
0x17, &Data);
xil_printf("TST_INT/Q : %d\n\r", Data);
/* BERT counter0[7:0] */
XVidC_Dp159Read(InstancePtr->IicPtr, XVIDC_DP159_IIC_SLAVE,
0x18, &Data);
xil_printf("BERT counter0[7:0] : %d\n\r", Data);
/* BERT counter0[11:8] */
XVidC_Dp159Read(InstancePtr->IicPtr, XVIDC_DP159_IIC_SLAVE,
0x19, &Data);
xil_printf("BERT counter0[11:8] : %d\n\r", Data);
/* BERT counter1[7:0] */
XVidC_Dp159Read(InstancePtr->IicPtr, XVIDC_DP159_IIC_SLAVE,
0x1A, &Data);
xil_printf("BERT counter0[7:0] : %d\n\r", Data);
/* BERT counter1[11:8] */
XVidC_Dp159Read(InstancePtr->IicPtr, XVIDC_DP159_IIC_SLAVE,
0x1B, &Data);
xil_printf("BERT counter0[11:8] : %d\n\r", Data);
/* BERT counter2[7:0] */
XVidC_Dp159Read(InstancePtr->IicPtr, XVIDC_DP159_IIC_SLAVE,
0x1C, &Data);
xil_printf("BERT counter2[7:0] : %d\n\r", Data);
/* BERT counter2[11:8] */
XVidC_Dp159Read(InstancePtr->IicPtr, XVIDC_DP159_IIC_SLAVE,
0x1D, &Data);
xil_printf("BERT counter2[11:8] : %d\n\r", Data);
/* BERT counter3[7:0] */
XVidC_Dp159Read(InstancePtr->IicPtr, XVIDC_DP159_IIC_SLAVE,
0x1E, &Data);
xil_printf("BERT counter3[7:0] : %d\n\r", Data);
/* BERT counter3[11:8] */
XVidC_Dp159Read(InstancePtr->IicPtr, XVIDC_DP159_IIC_SLAVE,
0x1F, &Data);
xil_printf("BERT counter3[11:8] : %d\n\r", Data);
/* Clear BERT counters and TST_INTQ latches - Self-clearing in DP159 */
XVidC_Dp159Write(InstancePtr->IicPtr, XVIDC_DP159_IIC_SLAVE,
0xFF, 0x00);
/* Select page 1 */
XVidC_Dp159Write(InstancePtr->IicPtr, XVIDC_DP159_IIC_SLAVE,
0xFF, 0x01);
}

108
XilinxProcessorIPLib/drivers/dprxss/src/xdprxss_g.c Normal file
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/*******************************************************************
*
* CAUTION: This file is automatically generated by HSI.
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
*copies of the Software, and to permit persons to whom the Software is
*furnished to do so, subject to the following conditions:
*
*The above copyright notice and this permission notice shall be included in
*all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
*(a) running on a Xilinx device, or
*(b) that interact with a Xilinx device through a bus or interconnect.
*
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*Except as contained in this notice, the name of the Xilinx shall not be used
*in advertising or otherwise to promote the sale, use or other dealings in
*this Software without prior written authorization from Xilinx.
*
*
* Description: Driver configuration
*
*******************************************************************/
#include "xparameters.h"
#include "xdprxss.h"
/*
* The configuration table for devices
*/
#define XPAR_DP_RX_SUBSYSTEM_0_DP_PRESENT 1
#define XPAR_DP_RX_SUBSYSTEM_0_DP_RX_HDCP_PRESENT 1
#define XPAR_DP_RX_SUBSYSTEM_0_IIC_PRESENT 1
XDpRxSs_Config XDpRxSs_ConfigTable[] =
{
{
XPAR_DP_RX_SUBSYSTEM_0_DEVICE_ID,
XPAR_DP_RX_SUBSYSTEM_0_BASEADDR,
XPAR_DP_RX_SUBSYSTEM_0_AUDIO_ENABLE,
XPAR_DP_RX_SUBSYSTEM_0_NUM_AUD_CH,
XPAR_DP_RX_SUBSYSTEM_0_BITS_PER_COLOR,
XPAR_DP_RX_SUBSYSTEM_0_HDCP_ENABLE,
XPAR_DP_RX_SUBSYSTEM_0_LANE_COUNT,
XPAR_DP_RX_SUBSYSTEM_0_MODE,
XPAR_DP_RX_SUBSYSTEM_0_NUM_STREAMS,
XPAR_DP_RX_SUBSYSTEM_0_COLOR_FORMAT,
{
XPAR_DP_RX_SUBSYSTEM_0_DP_PRESENT,
{
XPAR_DP_RX_SUBSYSTEM_0_DP_DEVICE_ID,
XPAR_DP_RX_SUBSYSTEM_0_DP_BASEADDR,
XPAR_DP_RX_SUBSYSTEM_0_DP_S_AXI_ACLK,
XPAR_DP_RX_SUBSYSTEM_0_DP_LANE_COUNT,
XPAR_DP_RX_SUBSYSTEM_0_DP_LINK_RATE,
XPAR_DP_RX_SUBSYSTEM_0_DP_MAX_BITS_PER_COLOR,
XPAR_DP_RX_SUBSYSTEM_0_DP_QUAD_PIXEL_ENABLE,
XPAR_DP_RX_SUBSYSTEM_0_DP_DUAL_PIXEL_ENABLE,
XPAR_DP_RX_SUBSYSTEM_0_DP_YCRCB_ENABLE,
XPAR_DP_RX_SUBSYSTEM_0_DP_YONLY_ENABLE,
XPAR_DP_RX_SUBSYSTEM_0_DP_GT_DATAWIDTH,
XPAR_DP_RX_SUBSYSTEM_0_DP_SECONDARY_SUPPORT,
XPAR_DP_RX_SUBSYSTEM_0_DP_AUDIO_CHANNELS,
XPAR_DP_RX_SUBSYSTEM_0_DP_MST_ENABLE,
XPAR_DP_RX_SUBSYSTEM_0_DP_NUMBER_OF_MST_STREAMS,
XPAR_DP_RX_SUBSYSTEM_0_DP_PROTOCOL_SELECTION,
XPAR_DP_RX_SUBSYSTEM_0_DP_FLOW_DIRECTION
}
},
{
XPAR_DP_RX_SUBSYSTEM_0_DP_RX_HDCP_PRESENT,
{
XPAR_DP_RX_SUBSYSTEM_0_DP_RX_HDCP_DEVICE_ID,
XPAR_DP_RX_SUBSYSTEM_0_DP_RX_HDCP_BASEADDR,
XPAR_DP_RX_SUBSYSTEM_0_DP_RX_HDCP_S_AXI_FREQUENCY,
XPAR_DP_RX_SUBSYSTEM_0_DP_RX_HDCP_IS_RX,
XPAR_DP_RX_SUBSYSTEM_0_DP_RX_HDCP_IS_HDMI
}
},
{
XPAR_DP_RX_SUBSYSTEM_0_IIC_PRESENT,
{
XPAR_DP_RX_SUBSYSTEM_0_IIC_DEVICE_ID,
XPAR_DP_RX_SUBSYSTEM_0_IIC_BASEADDR,
XPAR_DP_RX_SUBSYSTEM_0_IIC_TEN_BIT_ADR,
XPAR_DP_RX_SUBSYSTEM_0_IIC_GPO_WIDTH
}
}
}
};

189
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/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xdprxss_hw.h
*
* This header file contains identifiers and register-level core functions (or
* macros) that can be used to access the Xilinx DisplayPort Receiver Subsystem.
*
* For more information about the operation of this core see the hardware
* specification and documentation in the higher level driver xdprxss.h file.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ---- --- -------- -----------------------------------------------------
* 1.00 sha 05/18/15 Initial release.
* </pre>
*
******************************************************************************/
#ifndef XDPRXSS_HW_H_
#define XDPRXSS_HW_H_ /**< Prevent circular inclusions
* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_io.h"
/************************** Constant Definitions *****************************/
/* 0x09C: OVER_LINK_BW_SET */
#define XDPRXSS_LINK_BW_SET_162GBPS XDP_RX_OVER_LINK_BW_SET_162GBPS /**< 1.62
* Gbps
* link
* rate.
*/
#define XDPRXSS_LINK_BW_SET_270GBPS XDP_RX_OVER_LINK_BW_SET_270GBPS /**< 2.70
* Gbps
* link
* rate.
*/
#define XDPRXSS_LINK_BW_SET_540GBPS XDP_RX_OVER_LINK_BW_SET_540GBPS /**< 5.40
* Gbps
* link
* rate.
*/
/* 0x0A0: OVER_LANE_COUNT_SET */
#define XDPRXSS_LANE_COUNT_SET_1 XDP_RX_OVER_LANE_COUNT_SET_1 /**< Lane count
* of 1. */
#define XDPRXSS_LANE_COUNT_SET_2 XDP_RX_OVER_LANE_COUNT_SET_2 /**< Lane count
* of 2. */
#define XDPRXSS_LANE_COUNT_SET_4 XDP_RX_OVER_LANE_COUNT_SET_4 /**< Lane count
* of 4. */
#define XDPRXSS_RX_PHY_CONFIG XDP_RX_PHY_CONFIG /**< PHY reset and
* config */
#define XDPRXSS_PHY_POWER_DOWN XDP_RX_PHY_POWER_DOWN /**< PHY power down */
#define XDPRXSS_MSA_HRES XDP_RX_MSA_HRES /**< Number of active pixels
* per line (the horizontal
* resolution). */
#define XDPRXSS_MSA_VRES XDP_RX_MSA_VHEIGHT /**< Number of active
* lines (the
* vertical
* resolution). */
/* Link bandwidth and lane count setting as exposed in the RX DPCD */
#define XDPRXSS_DPCD_LINK_BW_SET XDP_RX_DPCD_LINK_BW_SET
#define XDPRXSS_DPCD_LANE_COUNT_SET XDP_RX_DPCD_LANE_COUNT_SET
/* Link training status for lanes 0, lane 1, lane 2 and lane 3 as exposed in
* the RX DPCD
*/
#define XDPRXSS_DPCD_LANE01_STATUS XDP_RX_DPCD_LANE01_STATUS
#define XDPRXSS_DPCD_LANE23_STATUS XDP_RX_DPCD_LANE23_STATUS
/* Vertical blank interrupt mask */
#define XDPRXSS_INTR_VBLANK_MASK XDP_RX_INTERRUPT_MASK_VBLANK_MASK
#define XDPRXSS_NUM_STREAMS 4 /**< Maximum number of
* streams supported */
#define XDPRXSS_MAX_NPORTS XDP_MAX_NPORTS /**< Maximum number of
* RX ports */
#define XDPRXSS_GUID_NBYTES XDP_GUID_NBYTES /**< Number of bytes
* for GUID */
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/** @name Register access macro definition
* @{
*/
#define XDpRxSs_In32 Xil_In32 /**< Input Operations */
#define XDpRxSs_Out32 Xil_Out32 /**< Output Operations */
/*****************************************************************************/
/**
*
* This macro reads a value from a DisplayPort Receiver Subsystem register.
* A 32 bit read is performed. If the component is implemented in a smaller
* width, only the least significant data is read from the register. The most
* significant data will be read as 0.
*
* @param BaseAddress is the base address of the XDpRxSs core instance.
* @param RegOffset is the register offset of the register (defined at
* the top of this file).
*
* @return The 32-bit value of the register.
*
* @note C-style signature:
* u32 XDpRxSs_ReadReg(u32 BaseAddress, u32 RegOffset)
*
******************************************************************************/
#define XDpRxSs_ReadReg(BaseAddress, RegOffset) \
XDpRxSs_In32((BaseAddress) + ((u32)RegOffset))
/*****************************************************************************/
/**
*
* This macro writes a value to a DisplayPort Receiver Subsystem register.
* A 32 bit write is performed. If the component is implemented in a smaller
* width, only the least significant data is written.
*
* @param BaseAddress is the base address of the XDpRxSs core instance.
* @param RegOffset is the register offset of the register (defined at
* the top of this file) to be written.
* @param Data is the 32-bit value to write into the register.
*
* @return None.
*
* @note C-style signature:
* void XDpRxSs_WriteReg(u32 BaseAddress, u32 RegOffset,
* u32 Data)
*
******************************************************************************/
#define XDpRxSs_WriteReg(BaseAddress, RegOffset, Data) \
XDpRxSs_Out32((BaseAddress) + ((u32)RegOffset), (u32)(Data))
/*@}*/
/************************** Function Prototypes ******************************/
/************************** Variable Declarations ****************************/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xdprxss_intr.c
*
* This file contains interrupt related functions of Xilinx DisplayPort RX
* Subsystem core. Please see xdprxss.h for more details of the core.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ---- --- -------- -----------------------------------------------------
* 1.00 sha 05/18/15 Initial release.
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xdprxss.h"
/************************** Constant Definitions *****************************/
/***************** Macros (Inline Functions) Definitions *********************/
/**************************** Type Definitions *******************************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/************************** Function Definitions *****************************/
/*****************************************************************************/
/**
*
* This function is the interrupt handler for the DisplayPort RX core operating
* in RX mode.
*
* The application is responsible for connecting this function to the interrupt
* system. Application beyond this driver is also responsible for providing
* callbacks to handle interrupts and installing the callbacks using
* XDpRxSs_SetCallBack() during initialization phase.
*
* @param InstancePtr is a pointer to the XDpRxSs core instance that
* just interrupted.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XDpRxSs_DpIntrHandler(void *InstancePtr)
{
XDpRxSs *XDpRxSsPtr = (XDpRxSs *)InstancePtr;
/* Verify arguments. */
Xil_AssertVoid(XDpRxSsPtr != NULL);
Xil_AssertVoid(XDpRxSsPtr->IsReady == XIL_COMPONENT_IS_READY);
/* DisplayPort RX interrupt handler */
XDp_InterruptHandler(XDpRxSsPtr->DpPtr);
}
/*****************************************************************************/
/**
*
* This function installs an asynchronous callback function for the given
* HandlerType:
*
* <pre>
* HandlerType Callback Function Type
* ---------------------------------------- -----------------------------------
* XDPRXSS_HANDLER_DP_VM_CHG_EVENT XDp_RxSetIntrVmChangeHandler
* XDPRXSS_HANDLER_DP_PWR_CHG_EVENT XDp_RxSetIntrPowerStateHandler
* XDPRXSS_HANDLER_DP_NO_VID_EVENT XDp_RxSetIntrNoVideoHandler
* XDPRXSS_HANDLER_DP_VBLANK_EVENT XDp_RxSetIntrVBlankHandler
* XDPRXSS_HANDLER_DP_TLOST_EVENT XDp_RxSetIntrTrainingLostHandler
* XDPRXSS_HANDLER_DP_VID_EVENT XDp_RxSetIntrVideoHandler
* XDPRXSS_HANDLER_DP_INFO_PKT_EVENT XDp_RxSetIntrInfoPktHandler
* XDPRXSS_HANDLER_DP_EXT_PKT_EVENT XDp_RxSetIntrExtPktHandler
* XDPRXSS_HANDLER_DP_TDONE_EVENT XDp_RxSetIntrTrainingDoneHandler
* XDPRXSS_HANDLER_DP_BW_CHG_EVENT XDp_RxSetIntrBwChangeHandler
* XDPRXSS_HANDLER_DP_DWN_REQ_EVENT XDp_RxSetIntrDownReqHandler
* XDPRXSS_HANDLER_DP_DWN_REP_EVENT XDp_RxSetIntrDownReplyHandler
* XDPRXSS_HANDLER_DP_AUD_OVRFLW_EVENT XDp_RxSetIntrAudioOverHandler
* XDPRXSS_HANDLER_DP_PAYLOAD_ALLOC_EVENT XDp_RxSetIntrPayloadAllocHandler
* XDPRXSS_HANDLER_DP_ACT_RX_EVENT XDp_RxSetIntrActRxHandler
* XDPRXSS_HANDLER_DP_CRC_TEST_EVENT XDp_RxSetIntrCrcTestHandler
* XDPRXSS_HANDLER_DP_HDCP_DBG_WR_EVENT XDp_RxSetIntrHdcpDebugWriteHandler
* XDPRXSS_HANDLER_DP_HDCP_AKSV_WR_EVENT XDp_RxSetIntrHdcpAksvWriteHandler
* XDPRXSS_HANDLER_DP_HDCP_AN_WR_EVENT XDp_RxSetIntrHdcpAnWriteHandler
* XDPRXSS_HANDLER_DP_HDCP_A_INFO_WR_EVENT XDp_RxSetIntrHdcpAinfoWriteHandler
* XDPRXSS_HANDLER_DP_HDCP_RO_RD_EVENT XDp_RxSetIntrHdcpRoReadHandler
* XDPRXSS_HANDLER_DP_HDCP_B_INFO_RD_EVENT XDp_RxSetIntrHdcpBinfoReadHandler
* XDPRXSS_HANDLER_UNPLUG_EVENT UnplugCallback
* XDPRXSS_HANDLER_LINKBW_EVENT LinkBwCallback
* XDPRXSS_HANDLER_PLL_RESET_EVENT PllResetCallback
* </pre>
*
* @param InstancePtr is a pointer to the XDpRxSs core instance.
* @param HandlerType specifies the type of handler.
* @param CallbackFunc is the address of the callback function.
* @param CallbackRef is a user data item that will be passed to the
* callback function when it is invoked.
*
* @return
* - XST_SUCCESS if callback function installed successfully.
* - XST_INVALID_PARAM when HandlerType is invalid.
*
* @note Invoking this function for a handler that already has been
* installed replaces it with the new handler.
*
******************************************************************************/
u32 XDpRxSs_SetCallBack(XDpRxSs *InstancePtr, u32 HandlerType,
void *CallbackFunc, void *CallbackRef)
{
u32 Status;
/* Verify arguments. */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(HandlerType >= XDPRXSS_HANDLER_DP_VM_CHG_EVENT);
Xil_AssertNonvoid(CallbackFunc != NULL);
Xil_AssertNonvoid(CallbackRef != NULL);
/* Assign callback based on handler type */
switch (HandlerType) {
case XDPRXSS_HANDLER_DP_VM_CHG_EVENT:
XDp_RxSetIntrVmChangeHandler(InstancePtr->DpPtr,
CallbackFunc, CallbackRef);
Status = XST_SUCCESS;
break;
case XDPRXSS_HANDLER_DP_PWR_CHG_EVENT:
XDp_RxSetIntrPowerStateHandler(InstancePtr->DpPtr,
CallbackFunc, CallbackRef);
Status = XST_SUCCESS;
break;
case XDPRXSS_HANDLER_DP_NO_VID_EVENT:
XDp_RxSetIntrNoVideoHandler(InstancePtr->DpPtr,
CallbackFunc, CallbackRef);
Status = XST_SUCCESS;
break;
case XDPRXSS_HANDLER_DP_VBLANK_EVENT:
XDp_RxSetIntrVBlankHandler(InstancePtr->DpPtr,
CallbackFunc, CallbackRef);
Status = XST_SUCCESS;
break;
case XDPRXSS_HANDLER_DP_TLOST_EVENT:
XDp_RxSetIntrTrainingLostHandler(InstancePtr->DpPtr,
CallbackFunc, CallbackRef);
Status = XST_SUCCESS;
break;
case XDPRXSS_HANDLER_DP_VID_EVENT:
XDp_RxSetIntrVideoHandler(InstancePtr->DpPtr,
CallbackFunc, CallbackRef);
Status = XST_SUCCESS;
break;
case XDPRXSS_HANDLER_DP_INFO_PKT_EVENT:
XDp_RxSetIntrInfoPktHandler(InstancePtr->DpPtr,
CallbackFunc, CallbackRef);
Status = XST_SUCCESS;
break;
case XDPRXSS_HANDLER_DP_EXT_PKT_EVENT:
XDp_RxSetIntrExtPktHandler(InstancePtr->DpPtr,
CallbackFunc, CallbackRef);
Status = XST_SUCCESS;
break;
case XDPRXSS_HANDLER_DP_TDONE_EVENT:
XDp_RxSetIntrTrainingDoneHandler(InstancePtr->DpPtr,
CallbackFunc, CallbackRef);
Status = XST_SUCCESS;
break;
case XDPRXSS_HANDLER_DP_BW_CHG_EVENT:
XDp_RxSetIntrBwChangeHandler(InstancePtr->DpPtr,
CallbackFunc, CallbackRef);
Status = XST_SUCCESS;
break;
case XDPRXSS_HANDLER_DP_DWN_REQ_EVENT:
XDp_RxSetIntrDownReqHandler(InstancePtr->DpPtr,
CallbackFunc, CallbackRef);
Status = XST_SUCCESS;
break;
case XDPRXSS_HANDLER_DP_DWN_REP_EVENT:
XDp_RxSetIntrDownReplyHandler(InstancePtr->DpPtr,
CallbackFunc, CallbackRef);
Status = XST_SUCCESS;
break;
case XDPRXSS_HANDLER_DP_AUD_OVRFLW_EVENT:
XDp_RxSetIntrAudioOverHandler(InstancePtr->DpPtr,
CallbackFunc, CallbackRef);
Status = XST_SUCCESS;
break;
case XDPRXSS_HANDLER_DP_PAYLOAD_ALLOC_EVENT:
XDp_RxSetIntrPayloadAllocHandler(InstancePtr->DpPtr,
CallbackFunc, CallbackRef);
Status = XST_SUCCESS;
break;
case XDPRXSS_HANDLER_DP_ACT_RX_EVENT:
XDp_RxSetIntrActRxHandler(InstancePtr->DpPtr,
CallbackFunc, CallbackRef);
Status = XST_SUCCESS;
break;
case XDPRXSS_HANDLER_DP_CRC_TEST_EVENT:
XDp_RxSetIntrCrcTestHandler(InstancePtr->DpPtr,
CallbackFunc, CallbackRef);
Status = XST_SUCCESS;
break;
case XDPRXSS_HANDLER_DP_HDCP_DBG_WR_EVENT:
XDp_RxSetIntrHdcpDebugWriteHandler(InstancePtr->DpPtr,
CallbackFunc, CallbackRef);
Status = XST_SUCCESS;
break;
case XDPRXSS_HANDLER_DP_HDCP_AKSV_WR_EVENT:
XDp_RxSetIntrHdcpAksvWriteHandler(InstancePtr->DpPtr,
CallbackFunc, CallbackRef);
Status = XST_SUCCESS;
break;
case XDPRXSS_HANDLER_DP_HDCP_AN_WR_EVENT:
XDp_RxSetIntrHdcpAnWriteHandler(InstancePtr->DpPtr,
CallbackFunc, CallbackRef);
Status = XST_SUCCESS;
break;
case XDPRXSS_HANDLER_DP_HDCP_A_INFO_WR_EVENT:
XDp_RxSetIntrHdcpAinfoWriteHandler(InstancePtr->DpPtr,
CallbackFunc, CallbackRef);
Status = XST_SUCCESS;
break;
case XDPRXSS_HANDLER_DP_HDCP_RO_RD_EVENT:
XDp_RxSetIntrHdcpRoReadHandler(InstancePtr->DpPtr,
CallbackFunc, CallbackRef);
Status = XST_SUCCESS;
break;
case XDPRXSS_HANDLER_DP_HDCP_B_INFO_RD_EVENT:
XDp_RxSetIntrHdcpBinfoReadHandler(InstancePtr->DpPtr,
CallbackFunc, CallbackRef);
Status = XST_SUCCESS;
break;
case XDPRXSS_HANDLER_UNPLUG_EVENT:
InstancePtr->UnplugCallback =
(XDpRxSs_Callback)((void *)CallbackFunc);
InstancePtr->UnplugRef = CallbackRef;
Status = XST_SUCCESS;
break;
case XDPRXSS_HANDLER_LINKBW_EVENT:
InstancePtr->LinkBwCallback =
(XDpRxSs_Callback)((void *)CallbackFunc);
InstancePtr->LinkBwRef = CallbackRef;
Status = XST_SUCCESS;
break;
case XDPRXSS_HANDLER_PLL_RESET_EVENT:
InstancePtr->PllResetCallback =
(XDpRxSs_Callback)((void *)CallbackFunc);
InstancePtr->PllResetRef = CallbackRef;
Status = XST_SUCCESS;
break;
default:
Status = XST_INVALID_PARAM;
break;
}
return Status;
}
/*****************************************************************************/
/**
*
* This function installs a custom delay/sleep function to be used by the
* DisplayPort RX Subsystem.
*
* @param InstancePtr is a pointer to the XDpRxSs core instance.
* @param CallbackFunc is the address to the callback function.
* @param CallbackRef is the user data item (microseconds to delay) that
* will be passed to the custom sleep/delay function when it is
* invoked.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XDpRxSs_SetUserTimerHandler(XDpRxSs *InstancePtr,
XDpRxSs_TimerHandler CallbackFunc, void *CallbackRef)
{
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(CallbackFunc != NULL);
Xil_AssertVoid(CallbackRef != NULL);
/* Set custom timer wait handler */
XDp_SetUserTimerHandler(InstancePtr->DpPtr, CallbackFunc, CallbackRef);
}

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/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xdprxss_selftest.c
*
* This file contains self test function for the DisplayPort Receiver
* Subsystem core.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ---- --- -------- -----------------------------------------------------
* 1.00 sha 05/18/15 Initial release.
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xdprxss.h"
#include "xdebug.h"
/************************** Constant Definitions *****************************/
/***************** Macros (Inline Functions) Definitions *********************/
/**************************** Type Definitions *******************************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/************************** Function Definitions *****************************/
/*****************************************************************************/
/**
*
* This function performs self test on DisplayPort Receiver Subsystem
* sub-cores.
*
* @param InstancePtr is a pointer to the XDpRxSs core instance.
*
* @return
* - XST_SUCCESS if self test passed.
* - Otherwise, prints self test failed message.
*
* @note None.
*
******************************************************************************/
u32 XDpRxSs_SelfTest(XDpRxSs *InstancePtr)
{
u32 Status;
/* Verify argument. */
Xil_AssertNonvoid(InstancePtr != NULL);
/* Check DP availability */
if (InstancePtr->DpPtr) {
Status = XDp_SelfTest(InstancePtr->DpPtr);
if (Status != XST_SUCCESS) {
xdbg_printf(XDBG_DEBUG_GENERAL,"ERR::DP Self test "
"failed\n\r");
}
}
/* Check IIC availability */
if (InstancePtr->IicPtr) {
Status = (u32)XIic_SelfTest(InstancePtr->IicPtr);
if (Status != XST_SUCCESS) {
xdbg_printf(XDBG_DEBUG_GENERAL,"ERR::IIC Self test "
"failed\n\r");
}
}
return XST_SUCCESS;
}

109
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/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xdprxss_sinit.c
*
* This file contains static initialization method for Xilinx DisplayPort
* Receiver Subsystem core.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ---- --- -------- -----------------------------------------------------
* 1.00 sha 05/18/15 Initial release.
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xdprxss.h"
#include "xparameters.h"
/************************** Constant Definitions *****************************/
/***************** Macros (Inline Functions) Definitions *********************/
/**************************** Type Definitions *******************************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/************************** Function Definitions *****************************/
/*****************************************************************************/
/**
*
* This function returns a reference to an XDpRxSs_Config structure based
* on the core id, <i>DeviceId</i>. The return value will refer to an entry in
* the device configuration table defined in the xdprxss_g.c file.
*
* @param DeviceId is the unique core ID of the XDpRxSs core for
* the lookup operation.
*
* @return XDpRxSs_LookupConfig returns a reference to a config record
* in the configuration table (in xdprxss_g.c) corresponding
* to <i>DeviceId</i>, or NULL if no match is found.
*
* @note None.
*
******************************************************************************/
XDpRxSs_Config *XDpRxSs_LookupConfig(u16 DeviceId)
{
extern XDpRxSs_Config XDpRxSs_ConfigTable[XPAR_XDPRXSS_NUM_INSTANCES];
XDpRxSs_Config *CfgPtr = NULL;
u32 Index;
/* Checking for device id for which instance it is matching */
for (Index = (u32)0x0; Index < (u32)(XPAR_XDPRXSS_NUM_INSTANCES);
Index++) {
/* Assigning address of config table if both device ids
* are matched
*/
if (XDpRxSs_ConfigTable[Index].DeviceId == DeviceId) {
CfgPtr = &XDpRxSs_ConfigTable[Index];
break;
}
}
return (XDpRxSs_Config *)CfgPtr;
}