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v_vscaler: Updated driver to align with hip flow

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This patch supports HIP based video processing subsystem by reorganizing
the HLS generated code to align with xilinx driver guidelines.

Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Reviewed-by: Andrei Simion <andreis@xilinx.com>
This commit is contained in:
Rohit Consul 2015-07-16 17:05:01 -07:00 • committed by Nava kishore Manne
parent e9d58acc53
commit a545768505
9 changed files with 206 additions and 98 deletions
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0
XilinxProcessorIPLib/drivers/v_vscaler/data/v_vscaler.mdd Normal file → Executable file
View file

79
XilinxProcessorIPLib/drivers/v_vscaler/data/v_vscaler.tcl Normal file → Executable file
View file

@ -1,9 +1,33 @@
# ==============================================================
# File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
# Version: 2015.1
# Copyright (C) 2015 Xilinx Inc. All rights reserved.
##############################################################################
#
# ==============================================================
# Copyright (C) 2015 Xilinx, Inc. All rights reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"),to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
#
# Use of the Software is limited solely to applications:
# (a) running on a Xilinx device, or
# (b) that interact with a Xilinx device through a bus or interconnect.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
# XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
# IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
#
# Except as contained in this notice, the name of the Xilinx shall not be used
# in advertising or otherwise to promote the sale, use or other dealings in
# this Software without prior written authorization from Xilinx.
###############################################################################
proc generate {drv_handle} {
xdefine_include_file $drv_handle "xparameters.h" "XV_vscaler" \
@ -11,35 +35,38 @@ proc generate {drv_handle} {
"DEVICE_ID" \
"C_S_AXI_CTRL_BASEADDR" \
"C_S_AXI_CTRL_HIGHADDR" \
"SAMPLES_PER_CLOCK" \
"MAX_COLS" \
"MAX_ROWS" \
"MAX_DATA_WIDTH" \
"PHASE_SHIFT" \
"SCALE_MODE" \
"TAPS"
"SAMPLES_PER_CLOCK" \
"NUM_VIDEO_COMPONENTS" \
"MAX_COLS" \
"MAX_ROWS" \
"MAX_DATA_WIDTH" \
"PHASE_SHIFT" \
"SCALE_MODE" \
"TAPS"
xdefine_config_file $drv_handle "xv_vscaler_g.c" "XV_vscaler" \
"DEVICE_ID" \
"C_S_AXI_CTRL_BASEADDR" \
"SAMPLES_PER_CLOCK" \
"MAX_COLS" \
"MAX_ROWS" \
"MAX_DATA_WIDTH" \
"PHASE_SHIFT" \
"SCALE_MODE" \
"TAPS"
"SAMPLES_PER_CLOCK" \
"NUM_VIDEO_COMPONENTS" \
"MAX_COLS" \
"MAX_ROWS" \
"MAX_DATA_WIDTH" \
"PHASE_SHIFT" \
"SCALE_MODE" \
"TAPS"
xdefine_canonical_xpars $drv_handle "xparameters.h" "XV_vscaler" \
"DEVICE_ID" \
"C_S_AXI_CTRL_BASEADDR" \
"C_S_AXI_CTRL_HIGHADDR" \
"SAMPLES_PER_CLOCK" \
"MAX_COLS" \
"MAX_ROWS" \
"MAX_DATA_WIDTH" \
"PHASE_SHIFT" \
"SCALE_MODE" \
"TAPS"
"SAMPLES_PER_CLOCK" \
"NUM_VIDEO_COMPONENTS" \
"MAX_COLS" \
"MAX_ROWS" \
"MAX_DATA_WIDTH" \
"PHASE_SHIFT" \
"SCALE_MODE" \
"TAPS"
}

77
XilinxProcessorIPLib/drivers/v_vscaler/src/xv_vscaler.c
View file

@ -11,16 +11,21 @@
/************************** Function Implementation *************************/
#ifndef __linux__
int XV_vscaler_CfgInitialize(XV_vscaler *InstancePtr, XV_vscaler_Config *ConfigPtr) {
int XV_vscaler_CfgInitialize(XV_vscaler *InstancePtr,
XV_vscaler_Config *ConfigPtr,
u32 EffectiveAddr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(ConfigPtr != NULL);
Xil_AssertNonvoid(EffectiveAddr != (u32)0x0);
/* Setup the instance */
(void)memset((void *)InstancePtr, 0, sizeof(XV_vscaler));
(void)memcpy((void *)&(InstancePtr->Config), (const void *)ConfigPtr,
sizeof(XV_vscaler_Config));
/* Setup the instance */
(void)memset((void *)InstancePtr, 0, sizeof(XV_vscaler));
(void)memcpy((void *)&(InstancePtr->Config), (const void *)ConfigPtr,
sizeof(XV_vscaler_Config));
InstancePtr->Ctrl_BaseAddress = ConfigPtr->Ctrl_BaseAddress;
InstancePtr->Config.BaseAddress = EffectiveAddr;
/* Set the flag to indicate the driver is ready */
InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
return XST_SUCCESS;
@ -33,8 +38,8 @@ void XV_vscaler_Start(XV_vscaler *InstancePtr) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_vscaler_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_VSCALER_CTRL_ADDR_AP_CTRL) & 0x80;
XV_vscaler_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_VSCALER_CTRL_ADDR_AP_CTRL, Data | 0x01);
Data = XV_vscaler_ReadReg(InstancePtr->Config.BaseAddress, XV_VSCALER_CTRL_ADDR_AP_CTRL) & 0x80;
XV_vscaler_WriteReg(InstancePtr->Config.BaseAddress, XV_VSCALER_CTRL_ADDR_AP_CTRL, Data | 0x01);
}
u32 XV_vscaler_IsDone(XV_vscaler *InstancePtr) {
@ -43,7 +48,7 @@ u32 XV_vscaler_IsDone(XV_vscaler *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_vscaler_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_VSCALER_CTRL_ADDR_AP_CTRL);
Data = XV_vscaler_ReadReg(InstancePtr->Config.BaseAddress, XV_VSCALER_CTRL_ADDR_AP_CTRL);
return (Data >> 1) & 0x1;
}
@ -53,7 +58,7 @@ u32 XV_vscaler_IsIdle(XV_vscaler *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_vscaler_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_VSCALER_CTRL_ADDR_AP_CTRL);
Data = XV_vscaler_ReadReg(InstancePtr->Config.BaseAddress, XV_VSCALER_CTRL_ADDR_AP_CTRL);
return (Data >> 2) & 0x1;
}
@ -63,7 +68,7 @@ u32 XV_vscaler_IsReady(XV_vscaler *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_vscaler_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_VSCALER_CTRL_ADDR_AP_CTRL);
Data = XV_vscaler_ReadReg(InstancePtr->Config.BaseAddress, XV_VSCALER_CTRL_ADDR_AP_CTRL);
// check ap_start to see if the pcore is ready for next input
return !(Data & 0x1);
}
@ -72,21 +77,21 @@ void XV_vscaler_EnableAutoRestart(XV_vscaler *InstancePtr) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_vscaler_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_VSCALER_CTRL_ADDR_AP_CTRL, 0x80);
XV_vscaler_WriteReg(InstancePtr->Config.BaseAddress, XV_VSCALER_CTRL_ADDR_AP_CTRL, 0x80);
}
void XV_vscaler_DisableAutoRestart(XV_vscaler *InstancePtr) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_vscaler_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_VSCALER_CTRL_ADDR_AP_CTRL, 0);
XV_vscaler_WriteReg(InstancePtr->Config.BaseAddress, XV_VSCALER_CTRL_ADDR_AP_CTRL, 0);
}
void XV_vscaler_Set_HwReg_HeightIn(XV_vscaler *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_vscaler_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_VSCALER_CTRL_ADDR_HWREG_HEIGHTIN_DATA, Data);
XV_vscaler_WriteReg(InstancePtr->Config.BaseAddress, XV_VSCALER_CTRL_ADDR_HWREG_HEIGHTIN_DATA, Data);
}
u32 XV_vscaler_Get_HwReg_HeightIn(XV_vscaler *InstancePtr) {
@ -95,7 +100,7 @@ u32 XV_vscaler_Get_HwReg_HeightIn(XV_vscaler *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_vscaler_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_VSCALER_CTRL_ADDR_HWREG_HEIGHTIN_DATA);
Data = XV_vscaler_ReadReg(InstancePtr->Config.BaseAddress, XV_VSCALER_CTRL_ADDR_HWREG_HEIGHTIN_DATA);
return Data;
}
@ -103,7 +108,7 @@ void XV_vscaler_Set_HwReg_Width(XV_vscaler *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_vscaler_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_VSCALER_CTRL_ADDR_HWREG_WIDTH_DATA, Data);
XV_vscaler_WriteReg(InstancePtr->Config.BaseAddress, XV_VSCALER_CTRL_ADDR_HWREG_WIDTH_DATA, Data);
}
u32 XV_vscaler_Get_HwReg_Width(XV_vscaler *InstancePtr) {
@ -112,7 +117,7 @@ u32 XV_vscaler_Get_HwReg_Width(XV_vscaler *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_vscaler_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_VSCALER_CTRL_ADDR_HWREG_WIDTH_DATA);
Data = XV_vscaler_ReadReg(InstancePtr->Config.BaseAddress, XV_VSCALER_CTRL_ADDR_HWREG_WIDTH_DATA);
return Data;
}
@ -120,7 +125,7 @@ void XV_vscaler_Set_HwReg_HeightOut(XV_vscaler *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_vscaler_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_VSCALER_CTRL_ADDR_HWREG_HEIGHTOUT_DATA, Data);
XV_vscaler_WriteReg(InstancePtr->Config.BaseAddress, XV_VSCALER_CTRL_ADDR_HWREG_HEIGHTOUT_DATA, Data);
}
u32 XV_vscaler_Get_HwReg_HeightOut(XV_vscaler *InstancePtr) {
@ -129,7 +134,7 @@ u32 XV_vscaler_Get_HwReg_HeightOut(XV_vscaler *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_vscaler_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_VSCALER_CTRL_ADDR_HWREG_HEIGHTOUT_DATA);
Data = XV_vscaler_ReadReg(InstancePtr->Config.BaseAddress, XV_VSCALER_CTRL_ADDR_HWREG_HEIGHTOUT_DATA);
return Data;
}
@ -137,7 +142,7 @@ void XV_vscaler_Set_HwReg_LineRate(XV_vscaler *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_vscaler_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_VSCALER_CTRL_ADDR_HWREG_LINERATE_DATA, Data);
XV_vscaler_WriteReg(InstancePtr->Config.BaseAddress, XV_VSCALER_CTRL_ADDR_HWREG_LINERATE_DATA, Data);
}
u32 XV_vscaler_Get_HwReg_LineRate(XV_vscaler *InstancePtr) {
@ -146,7 +151,7 @@ u32 XV_vscaler_Get_HwReg_LineRate(XV_vscaler *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_vscaler_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_VSCALER_CTRL_ADDR_HWREG_LINERATE_DATA);
Data = XV_vscaler_ReadReg(InstancePtr->Config.BaseAddress, XV_VSCALER_CTRL_ADDR_HWREG_LINERATE_DATA);
return Data;
}
@ -154,14 +159,14 @@ u32 XV_vscaler_Get_HwReg_vfltCoeff_BaseAddress(XV_vscaler *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
return (InstancePtr->Ctrl_BaseAddress + XV_VSCALER_CTRL_ADDR_HWREG_VFLTCOEFF_BASE);
return (InstancePtr->Config.BaseAddress + XV_VSCALER_CTRL_ADDR_HWREG_VFLTCOEFF_BASE);
}
u32 XV_vscaler_Get_HwReg_vfltCoeff_HighAddress(XV_vscaler *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
return (InstancePtr->Ctrl_BaseAddress + XV_VSCALER_CTRL_ADDR_HWREG_VFLTCOEFF_HIGH);
return (InstancePtr->Config.BaseAddress + XV_VSCALER_CTRL_ADDR_HWREG_VFLTCOEFF_HIGH);
}
u32 XV_vscaler_Get_HwReg_vfltCoeff_TotalBytes(XV_vscaler *InstancePtr) {
@ -195,7 +200,7 @@ u32 XV_vscaler_Write_HwReg_vfltCoeff_Words(XV_vscaler *InstancePtr, int offset,
return 0;
for (i = 0; i < length; i++) {
*(int *)(InstancePtr->Ctrl_BaseAddress + XV_VSCALER_CTRL_ADDR_HWREG_VFLTCOEFF_BASE + (offset + i)*4) = *(data + i);
*(int *)(InstancePtr->Config.BaseAddress + XV_VSCALER_CTRL_ADDR_HWREG_VFLTCOEFF_BASE + (offset + i)*4) = *(data + i);
}
return length;
}
@ -210,7 +215,7 @@ u32 XV_vscaler_Read_HwReg_vfltCoeff_Words(XV_vscaler *InstancePtr, int offset, i
return 0;
for (i = 0; i < length; i++) {
*(data + i) = *(int *)(InstancePtr->Ctrl_BaseAddress + XV_VSCALER_CTRL_ADDR_HWREG_VFLTCOEFF_BASE + (offset + i)*4);
*(data + i) = *(int *)(InstancePtr->Config.BaseAddress + XV_VSCALER_CTRL_ADDR_HWREG_VFLTCOEFF_BASE + (offset + i)*4);
}
return length;
}
@ -225,7 +230,7 @@ u32 XV_vscaler_Write_HwReg_vfltCoeff_Bytes(XV_vscaler *InstancePtr, int offset,
return 0;
for (i = 0; i < length; i++) {
*(char *)(InstancePtr->Ctrl_BaseAddress + XV_VSCALER_CTRL_ADDR_HWREG_VFLTCOEFF_BASE + offset + i) = *(data + i);
*(char *)(InstancePtr->Config.BaseAddress + XV_VSCALER_CTRL_ADDR_HWREG_VFLTCOEFF_BASE + offset + i) = *(data + i);
}
return length;
}
@ -240,7 +245,7 @@ u32 XV_vscaler_Read_HwReg_vfltCoeff_Bytes(XV_vscaler *InstancePtr, int offset, c
return 0;
for (i = 0; i < length; i++) {
*(data + i) = *(char *)(InstancePtr->Ctrl_BaseAddress + XV_VSCALER_CTRL_ADDR_HWREG_VFLTCOEFF_BASE + offset + i);
*(data + i) = *(char *)(InstancePtr->Config.BaseAddress + XV_VSCALER_CTRL_ADDR_HWREG_VFLTCOEFF_BASE + offset + i);
}
return length;
}
@ -249,14 +254,14 @@ void XV_vscaler_InterruptGlobalEnable(XV_vscaler *InstancePtr) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_vscaler_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_VSCALER_CTRL_ADDR_GIE, 1);
XV_vscaler_WriteReg(InstancePtr->Config.BaseAddress, XV_VSCALER_CTRL_ADDR_GIE, 1);
}
void XV_vscaler_InterruptGlobalDisable(XV_vscaler *InstancePtr) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_vscaler_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_VSCALER_CTRL_ADDR_GIE, 0);
XV_vscaler_WriteReg(InstancePtr->Config.BaseAddress, XV_VSCALER_CTRL_ADDR_GIE, 0);
}
void XV_vscaler_InterruptEnable(XV_vscaler *InstancePtr, u32 Mask) {
@ -265,8 +270,8 @@ void XV_vscaler_InterruptEnable(XV_vscaler *InstancePtr, u32 Mask) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Register = XV_vscaler_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_VSCALER_CTRL_ADDR_IER);
XV_vscaler_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_VSCALER_CTRL_ADDR_IER, Register | Mask);
Register = XV_vscaler_ReadReg(InstancePtr->Config.BaseAddress, XV_VSCALER_CTRL_ADDR_IER);
XV_vscaler_WriteReg(InstancePtr->Config.BaseAddress, XV_VSCALER_CTRL_ADDR_IER, Register | Mask);
}
void XV_vscaler_InterruptDisable(XV_vscaler *InstancePtr, u32 Mask) {
@ -275,27 +280,27 @@ void XV_vscaler_InterruptDisable(XV_vscaler *InstancePtr, u32 Mask) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Register = XV_vscaler_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_VSCALER_CTRL_ADDR_IER);
XV_vscaler_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_VSCALER_CTRL_ADDR_IER, Register & (~Mask));
Register = XV_vscaler_ReadReg(InstancePtr->Config.BaseAddress, XV_VSCALER_CTRL_ADDR_IER);
XV_vscaler_WriteReg(InstancePtr->Config.BaseAddress, XV_VSCALER_CTRL_ADDR_IER, Register & (~Mask));
}
void XV_vscaler_InterruptClear(XV_vscaler *InstancePtr, u32 Mask) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_vscaler_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_VSCALER_CTRL_ADDR_ISR, Mask);
XV_vscaler_WriteReg(InstancePtr->Config.BaseAddress, XV_VSCALER_CTRL_ADDR_ISR, Mask);
}
u32 XV_vscaler_InterruptGetEnabled(XV_vscaler *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
return XV_vscaler_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_VSCALER_CTRL_ADDR_IER);
return XV_vscaler_ReadReg(InstancePtr->Config.BaseAddress, XV_VSCALER_CTRL_ADDR_IER);
}
u32 XV_vscaler_InterruptGetStatus(XV_vscaler *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
return XV_vscaler_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_VSCALER_CTRL_ADDR_ISR);
return XV_vscaler_ReadReg(InstancePtr->Config.BaseAddress, XV_VSCALER_CTRL_ADDR_ISR);
}

16
XilinxProcessorIPLib/drivers/v_vscaler/src/xv_vscaler.h
View file

@ -45,14 +45,15 @@ typedef uint32_t u32;
*/
typedef struct {
u16 DeviceId; /**< Unique ID of device */
u32 Ctrl_BaseAddress; /**< The base address of the core instance. */
int PixPerClk; /**< Samples Per Clock supported by core instance */
u32 BaseAddress; /**< The base address of the core instance. */
u16 PixPerClk; /**< Samples Per Clock supported by core instance */
u16 NumVidComponents; /**< Number of Video Components */
u16 MaxWidth; /**< Maximum columns supported by core instance */
u16 MaxHeight; /**< Maximum rows supported by core instance */
int MaxDataWidth; /**< Maximum Data width of each channel */
u16 MaxDataWidth; /**< Maximum Data width of each channel */
u16 PhaseShift; /**< Max num of phases (2^PhaseShift) */
int ScalerType; /**< Scaling Algorithm Selected */
int NumTaps; /**< Number of taps */
u16 ScalerType; /**< Scaling Algorithm Selected */
u16 NumTaps; /**< Number of taps */
} XV_vscaler_Config;
#endif
@ -61,7 +62,6 @@ typedef struct {
*/
typedef struct {
XV_vscaler_Config Config; /**< Hardware Configuration */
u32 Ctrl_BaseAddress; /**< The base address of the core instance. */
u32 IsReady; /**< Device is initialized and ready */
} XV_vscaler;
@ -90,7 +90,9 @@ typedef struct {
#ifndef __linux__
int XV_vscaler_Initialize(XV_vscaler *InstancePtr, u16 DeviceId);
XV_vscaler_Config* XV_vscaler_LookupConfig(u16 DeviceId);
int XV_vscaler_CfgInitialize(XV_vscaler *InstancePtr, XV_vscaler_Config *ConfigPtr);
int XV_vscaler_CfgInitialize(XV_vscaler *InstancePtr,
XV_vscaler_Config *ConfigPtr,
u32 EffectiveAddr);
#else
int XV_vscaler_Initialize(XV_vscaler *InstancePtr, const char* InstanceName);
int XV_vscaler_Release(XV_vscaler *InstancePtr);

63
XilinxProcessorIPLib/drivers/v_vscaler/src/xv_vscaler_g.c Normal file
View file

@ -0,0 +1,63 @@
/*******************************************************************
*
* CAUTION: This file is automatically generated by HSI.
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
*copies of the Software, and to permit persons to whom the Software is
*furnished to do so, subject to the following conditions:
*
*The above copyright notice and this permission notice shall be included in
*all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
*(a) running on a Xilinx device, or
*(b) that interact with a Xilinx device through a bus or interconnect.
*
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*Except as contained in this notice, the name of the Xilinx shall not be used
*in advertising or otherwise to promote the sale, use or other dealings in
*this Software without prior written authorization from Xilinx.
*
*
* Description: Driver configuration
*
*******************************************************************/
#include "xparameters.h"
#include "xv_vscaler.h"
/*
* The configuration table for devices
*/
XV_vscaler_Config XV_vscaler_ConfigTable[] =
{
{
#ifdef XPAR_XV_VSCALER_NUM_INSTANCES
XPAR_V_PROC_SS_0_V_VSCALER_DEVICE_ID,
XPAR_V_PROC_SS_0_V_VSCALER_S_AXI_CTRL_BASEADDR,
XPAR_V_PROC_SS_0_V_VSCALER_SAMPLES_PER_CLOCK,
XPAR_V_PROC_SS_0_V_VSCALER_NUM_VIDEO_COMPONENTS,
XPAR_V_PROC_SS_0_V_VSCALER_MAX_COLS,
XPAR_V_PROC_SS_0_V_VSCALER_MAX_ROWS,
XPAR_V_PROC_SS_0_V_VSCALER_MAX_DATA_WIDTH,
XPAR_V_PROC_SS_0_V_VSCALER_PHASE_SHIFT,
XPAR_V_PROC_SS_0_V_VSCALER_SCALE_MODE,
XPAR_V_PROC_SS_0_V_VSCALER_TAPS
#endif
}
};

8
XilinxProcessorIPLib/drivers/v_vscaler/src/xv_vscaler_l2.c
View file

@ -35,6 +35,7 @@
* @file xv_vscaler_l2.c
* @addtogroup v_vscaler_v1_0
* @{
* @details
*
* The Vertical Scaler Layer-2 Driver.
* The functions in this file provides an abstraction from the register peek/poke
@ -46,7 +47,7 @@
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00 rc 05/01/15 Initial Release
* 1.00 rco 07/21/15 Initial Release
* </pre>
*
@ -393,6 +394,9 @@ void XV_VScalerSetup(XV_vscaler *InstancePtr,
*/
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(pVscL2Data != NULL);
Xil_AssertVoid((WidthIn>0) && (WidthIn<=InstancePtr->Config.MaxWidth));
Xil_AssertVoid((HeightIn>0) && (HeightIn<=InstancePtr->Config.MaxHeight));
Xil_AssertVoid((HeightOut>0) && (HeightOut<=InstancePtr->Config.MaxHeight));
if(InstancePtr->Config.ScalerType == XV_VSCALER_POLYPHASE)
{
@ -450,7 +454,7 @@ void XV_VScalerDbgReportStatus(XV_vscaler *InstancePtr)
done = XV_vscaler_IsDone(pVsc);
idle = XV_vscaler_IsIdle(pVsc);
ready = XV_vscaler_IsReady(pVsc);
ctrl = XV_vscaler_ReadReg(pVsc->Ctrl_BaseAddress, XV_VSCALER_CTRL_ADDR_AP_CTRL);
ctrl = XV_vscaler_ReadReg(pVsc->Config.BaseAddress, XV_VSCALER_CTRL_ADDR_AP_CTRL);
heightin = XV_vscaler_Get_HwReg_HeightIn(pVsc);

3
XilinxProcessorIPLib/drivers/v_vscaler/src/xv_vscaler_l2.h
View file

@ -35,6 +35,7 @@
* @file xv_vscaler_l2.h
* @addtogroup v_vscaler_v1_0
* @{
* @details
*
* This header file contains layer 2 API's of the verrtical scaler sub-core
* driver.The functions contained herein provides a high level implementation of
@ -97,7 +98,7 @@
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00 rc 05/01/15 Initial Release
* 1.00 rco 07/21/15 Initial Release
* </pre>
*

18
XilinxProcessorIPLib/drivers/v_vscaler/src/xv_vscaler_linux.c
View file

@ -87,8 +87,8 @@ static int uio_info_read_map_size(XV_vscaler_uio_info* info, int n) {
}
int XV_vscaler_Initialize(XV_vscaler *InstancePtr, const char* InstanceName) {
XV_vscaler_uio_info *InfoPtr = &uio_info;
struct dirent **namelist;
XV_vscaler_uio_info *InfoPtr = &uio_info;
struct dirent **namelist;
int i, n;
char* s;
char file[ MAX_UIO_PATH_SIZE ];
@ -100,9 +100,9 @@ int XV_vscaler_Initialize(XV_vscaler *InstancePtr, const char* InstanceName) {
n = scandir("/sys/class/uio", &namelist, 0, alphasort);
if (n < 0) return XST_DEVICE_NOT_FOUND;
for (i = 0; i < n; i++) {
strcpy(file, "/sys/class/uio/");
strcat(file, namelist[i]->d_name);
strcat(file, "/name");
strcpy(file, "/sys/class/uio/");
strcat(file, namelist[i]->d_name);
strcat(file, "/name");
if ((line_from_file(file, name) == 0) && (strcmp(name, InstanceName) == 0)) {
flag = 1;
s = namelist[i]->d_name;
@ -126,8 +126,8 @@ int XV_vscaler_Initialize(XV_vscaler *InstancePtr, const char* InstanceName) {
}
// NOTE: slave interface 'Ctrl' should be mapped to uioX/map0
InstancePtr->Ctrl_BaseAddress = (u32)mmap(NULL, InfoPtr->maps[0].size, PROT_READ|PROT_WRITE, MAP_SHARED, InfoPtr->uio_fd, 0 * getpagesize());
assert(InstancePtr->Ctrl_BaseAddress);
InstancePtr->Config.BaseAddress = (u32)mmap(NULL, InfoPtr->maps[0].size, PROT_READ|PROT_WRITE, MAP_SHARED, InfoPtr->uio_fd, 0 * getpagesize());
assert(InstancePtr->Config.BaseAddress);
InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
@ -135,12 +135,12 @@ int XV_vscaler_Initialize(XV_vscaler *InstancePtr, const char* InstanceName) {
}
int XV_vscaler_Release(XV_vscaler *InstancePtr) {
XV_vscaler_uio_info *InfoPtr = &uio_info;
XV_vscaler_uio_info *InfoPtr = &uio_info;
assert(InstancePtr != NULL);
assert(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
munmap((void*)InstancePtr->Ctrl_BaseAddress, InfoPtr->maps[0].size);
munmap((void*)InstancePtr->Config.BaseAddress, InfoPtr->maps[0].size);
close(InfoPtr->uio_fd);

40
XilinxProcessorIPLib/drivers/v_vscaler/src/xv_vscaler_sinit.c
View file

@ -11,35 +11,41 @@
#include "xparameters.h"
#include "xv_vscaler.h"
#ifndef XPAR_XV_VSCALER_NUM_INSTANCES
#define XPAR_XV_VSCALER_NUM_INSTANCES 0
#endif
extern XV_vscaler_Config XV_vscaler_ConfigTable[];
XV_vscaler_Config *XV_vscaler_LookupConfig(u16 DeviceId) {
XV_vscaler_Config *ConfigPtr = NULL;
XV_vscaler_Config *ConfigPtr = NULL;
int Index;
int Index;
for (Index = 0; Index < XPAR_XV_VSCALER_NUM_INSTANCES; Index++) {
if (XV_vscaler_ConfigTable[Index].DeviceId == DeviceId) {
ConfigPtr = &XV_vscaler_ConfigTable[Index];
break;
}
}
for (Index = 0; Index < XPAR_XV_VSCALER_NUM_INSTANCES; Index++) {
if (XV_vscaler_ConfigTable[Index].DeviceId == DeviceId) {
ConfigPtr = &XV_vscaler_ConfigTable[Index];
break;
}
}
return ConfigPtr;
return ConfigPtr;
}
int XV_vscaler_Initialize(XV_vscaler *InstancePtr, u16 DeviceId) {
XV_vscaler_Config *ConfigPtr;
XV_vscaler_Config *ConfigPtr;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr != NULL);
ConfigPtr = XV_vscaler_LookupConfig(DeviceId);
if (ConfigPtr == NULL) {
InstancePtr->IsReady = 0;
return (XST_DEVICE_NOT_FOUND);
}
ConfigPtr = XV_vscaler_LookupConfig(DeviceId);
if (ConfigPtr == NULL) {
InstancePtr->IsReady = 0;
return (XST_DEVICE_NOT_FOUND);
}
return XV_vscaler_CfgInitialize(InstancePtr, ConfigPtr);
return XV_vscaler_CfgInitialize(InstancePtr,
ConfigPtr,
ConfigPtr->BaseAddress);
}
#endif