dp: rx: Use definitions instead of hard-coded values.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
This commit is contained in:
Andrei-Liviu Simion
Nava kishore Manne
parent
01658a8c12
commit
aa72195688
2 changed files with 53 additions and 42 deletions
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@ -144,46 +144,54 @@ u32 XDprx_InitializeRx(XDprx *InstancePtr)
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Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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/* Disable the main link. */
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XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_LINK_ENABLE, 0x00);
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XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_LINK_ENABLE, 0x0);
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/* Set the AUX clock divider. */
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XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_AUX_CLK_DIVIDER,
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(InstancePtr->Config.SAxiClkHz / 1000000));
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/* Put both GT RX/TX and CPLL into reset. */
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XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_PHY_CONFIG, 0x03);
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XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_PHY_CONFIG,
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XDPRX_PHY_CONFIG_GTPLL_RESET_MASK |
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XDPRX_PHY_CONFIG_GTRX_RESET_MASK);
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/* Release CPLL reset. */
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XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_PHY_CONFIG, 0x02);
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XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_PHY_CONFIG,
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XDPRX_PHY_CONFIG_GTRX_RESET_MASK);
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/* Wait until all lane CPLLs have locked. */
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Status = XDprx_WaitPhyReady(InstancePtr, 0x30);
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Status = XDprx_WaitPhyReady(InstancePtr,
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XDPRX_PHY_STATUS_PLL_LANE0_1_LOCK_MASK |
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XDPRX_PHY_STATUS_PLL_LANE2_3_LOCK_MASK);
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if (Status != XST_SUCCESS) {
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return XST_FAILURE;
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}
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/* Remove the reset from the PHY. */
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XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_PHY_CONFIG, 0x00);
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XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_PHY_CONFIG,
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XDPRX_PHY_CONFIG_PHY_RESET_ENABLE_MASK);
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/* Wait until the PHY has completed the reset cycle. */
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Status = XDprx_WaitPhyReady(InstancePtr, 0xFF);
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Status = XDprx_WaitPhyReady(InstancePtr,
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XDPRX_PHY_STATUS_ALL_LANES_READY_MASK |
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XDPRX_PHY_STATUS_PLL_FABRIC_LOCK_MASK |
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XDPRX_PHY_STATUS_RX_CLK_LOCK_MASK);
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if (Status != XST_SUCCESS) {
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return XST_FAILURE;
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}
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/* Enable the RX core. */
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XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_LINK_ENABLE, 0x01);
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XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_LINK_ENABLE, 0x1);
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/* Set other user parameters. */
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XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_MIN_VOLTAGE_SWING,
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0x01);
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XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_SINK_COUNT, 0x01);
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/* Set the AUX training interval. */
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XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_OVER_CTRL_DPCD,
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0x01);
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XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_OVER_TP_SET, 0x0200);
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XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_OVER_CTRL_DPCD,
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0x00);
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XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_OVER_CTRL_DPCD, 0x1);
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XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_OVER_TP_SET,
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(2 << XDPRX_OVER_TP_SET_TRAINING_AUX_RD_INTERVAL_SHIFT));
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XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_OVER_CTRL_DPCD, 0x0);
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/* Set the link configuration.*/
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XDprx_SetLinkRate(InstancePtr, InstancePtr->LinkConfig.LinkRate);
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XDprx_SetLaneCount(InstancePtr, InstancePtr->LinkConfig.LaneCount);
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@ -265,9 +273,11 @@ void XDprx_DtgEn(XDprx *InstancePtr)
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Xil_AssertVoid(InstancePtr != NULL);
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Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_SOFT_RESET, 0x01);
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XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_SOFT_RESET, 0x00);
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XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_DTG_ENABLE, 0x01);
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XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_SOFT_RESET,
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XDPRX_SOFT_RESET_VIDEO_MASK);
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XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_SOFT_RESET, 0x0);
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XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_DTG_ENABLE, 0x1);
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}
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/******************************************************************************/
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@ -287,9 +297,11 @@ void XDprx_DtgDis(XDprx *InstancePtr)
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Xil_AssertVoid(InstancePtr != NULL);
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Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_DTG_ENABLE, 0x00);
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XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_SOFT_RESET, 0x01);
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XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_SOFT_RESET, 0x00);
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XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_DTG_ENABLE, 0x0);
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XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_SOFT_RESET,
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XDPRX_SOFT_RESET_VIDEO_MASK);
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XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_SOFT_RESET, 0x0);
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}
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/******************************************************************************/
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@ -320,14 +332,12 @@ void XDprx_SetLinkRate(XDprx *InstancePtr, u8 LinkRate)
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InstancePtr->LinkConfig.LinkRate = LinkRate;
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XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_OVER_CTRL_DPCD,
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0x01);
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XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_OVER_CTRL_DPCD, 0x1);
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XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_OVER_LINK_BW_SET,
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LinkRate);
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XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_OVER_CTRL_DPCD,
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0x00);
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XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_OVER_CTRL_DPCD, 0x0);
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XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_LOCAL_EDID_VIDEO,
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0x01);
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0x1);
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}
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/******************************************************************************/
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@ -354,14 +364,12 @@ void XDprx_SetLaneCount(XDprx *InstancePtr, u8 LaneCount)
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InstancePtr->LinkConfig.LaneCount = LaneCount;
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XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_OVER_CTRL_DPCD,
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0x01);
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XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_OVER_CTRL_DPCD, 0x1);
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XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_OVER_LANE_COUNT_SET,
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LaneCount);
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XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_OVER_CTRL_DPCD,
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0x00);
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XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_OVER_CTRL_DPCD, 0x0);
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XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_LOCAL_EDID_VIDEO,
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0x01);
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0x1);
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}
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/******************************************************************************/
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@ -388,8 +396,8 @@ void XDprx_SetUserPixelWidth(XDprx *InstancePtr, u8 UserPixelWidth)
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XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_USER_PIXEL_WIDTH,
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UserPixelWidth);
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XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_SOFT_RESET, 0x01);
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XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_SOFT_RESET, 0x00);
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XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_SOFT_RESET, 0x1);
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XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_SOFT_RESET, 0x0);
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}
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/******************************************************************************/
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@ -82,17 +82,19 @@ void XDprx_InterruptHandler(XDprx *InstancePtr)
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* Note: XDPRX_INTERRUPT_CAUSE is an RC (read-clear) register. */
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IntrStatus = XDprx_ReadReg(InstancePtr->Config.BaseAddr,
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XDPRX_INTERRUPT_CAUSE);
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IntrVmChange = (IntrStatus & 0x00001);
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IntrPowerState = ((IntrStatus & 0x00002) >> 1);
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IntrNoVideo = ((IntrStatus & 0x00004) >> 2);
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IntrVBlank = ((IntrStatus & 0x00008) >> 3);
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IntrTrainingLost = ((IntrStatus & 0x00010) >> 4);
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IntrVideo = ((IntrStatus & 0x00040) >> 6);
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IntrTrainingDone = ((IntrStatus & 0x04000) >> 14);
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IntrBwChange = ((IntrStatus & 0x08000) >> 15);
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IntrTp1 = ((IntrStatus & 0x10000) >> 16);
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IntrTp2 = ((IntrStatus & 0x20000) >> 17);
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IntrTp3 = ((IntrStatus & 0x40000) >> 18);
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IntrVmChange = (IntrStatus & XDPRX_INTERRUPT_CAUSE_VM_CHANGE_MASK);
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IntrPowerState = (IntrStatus & XDPRX_INTERRUPT_CAUSE_POWER_STATE_MASK);
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IntrNoVideo = (IntrStatus & XDPRX_INTERRUPT_CAUSE_NO_VIDEO_MASK);
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IntrVBlank = (IntrStatus & XDPRX_INTERRUPT_CAUSE_VBLANK_MASK);
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IntrTrainingLost = (IntrStatus &
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XDPRX_INTERRUPT_CAUSE_TRAINING_LOST_MASK);
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IntrVideo = (IntrStatus & XDPRX_INTERRUPT_CAUSE_VIDEO_MASK);
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IntrTrainingDone = (IntrStatus &
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XDPRX_INTERRUPT_CAUSE_TRAINING_DONE_MASK);
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IntrBwChange = (IntrStatus & XDPRX_INTERRUPT_CAUSE_BW_CHANGE_MASK);
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IntrTp1 = (IntrStatus & XDPRX_INTERRUPT_CAUSE_TP1_MASK);
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IntrTp2 = (IntrStatus & XDPRX_INTERRUPT_CAUSE_TP2_MASK);
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IntrTp3 = (IntrStatus & XDPRX_INTERRUPT_CAUSE_TP3_MASK);
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/* Training pattern 1 has started. */
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if (IntrTp1) {
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@ -176,7 +178,8 @@ void XDprx_GenerateHpdInterrupt(XDprx *InstancePtr, u16 DurationUs)
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Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_HPD_INTERRUPT,
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(DurationUs << 16) | 0x1);
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(DurationUs << XDPRX_HPD_INTERRUPT_LENGTH_US_SHIFT) |
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XDPRX_HPD_INTERRUPT_ASSERT_MASK);
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}
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/******************************************************************************/
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