Sync with next version of standalone driver

lib/bsp/standalone/src/changelog.txt

@@ -39,7 +39,7 @@
  *                     driver tcl in xparameters.h. Update the gcc/translationtable.s
  *                     for the QSPI complete address range - DT644567
  *                     Removed profile directory for armcc compiler and changed
- *                     profiling setting to false in standalone_0.tcl file
+ *                     profiling setting to false in standalone_v2_1_0.tcl file
  *                     Deleting boot.S file after preprocessing for armcc compiler
  * 3.05a asa  03/11/12 Updated the function Xil_EnableMMU in file xil_mmu.c to
  *		       invalidate the caches before enabling back the MMU and
@@ -229,4 +229,7 @@
  *		       Xil_L2CacheInvalidateRange API. Xil_L1DCacheInvalidate and
  *		       Xil_L2CacheInvalidate APIs are modified to flush the complete stack
  *		       instead of just System Stack
+ * 5.1 pkp   14/05/15  Modified cortexa9/gcc/Makefile to keep a correct check of a compiler
+ *		       to update ECC_FLAGS and also take the compiler and archiver as specified
+ *		       in settings instead of hardcoding it.
  *****************************************************************************************/

lib/bsp/standalone/src/cortexa53/gcc/boot.S

@@ -201,7 +201,6 @@ OKToRun:
 	orr      x1, x1, #(1 << 12)	//Enable I cache
 	orr      x1, x1, #(1 << 3)	//Enable SP alignment check
 	orr      x1, x1, #(1 << 2)	//Enable caches
-	orr      x1, x1, #(1 << 1)	//Enable alignment
 	orr      x1, x1, #(1 << 0)	//Enable MMU
 	msr      SCTLR_EL3, x1
 	dsb	 sy

lib/bsp/standalone/src/cortexa53/xfpd_slcr.h

@@ -0,0 +1,382 @@
+/* ### HEADER ### */
+
+#ifndef __XFPD_SLCR_H__
+#define __XFPD_SLCR_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XfpdSlcr Base Address
+ */
+#define XFPD_SLCR_BASEADDR      0xFD610000UL
+
+/**
+ * Register: XfpdSlcrWprot0
+ */
+#define XFPD_SLCR_WPROT0    ( ( XFPD_SLCR_BASEADDR ) + 0x00000000UL )
+#define XFPD_SLCR_WPROT0_RSTVAL   0x00000001UL
+
+#define XFPD_SLCR_WPROT0_ACT_SHIFT   0UL
+#define XFPD_SLCR_WPROT0_ACT_WIDTH   1UL
+#define XFPD_SLCR_WPROT0_ACT_MASK    0x00000001UL
+#define XFPD_SLCR_WPROT0_ACT_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdSlcrCtrl
+ */
+#define XFPD_SLCR_CTRL    ( ( XFPD_SLCR_BASEADDR ) + 0x00000004UL )
+#define XFPD_SLCR_CTRL_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_CTRL_SLVERR_EN_SHIFT   0UL
+#define XFPD_SLCR_CTRL_SLVERR_EN_WIDTH   1UL
+#define XFPD_SLCR_CTRL_SLVERR_EN_MASK    0x00000001UL
+#define XFPD_SLCR_CTRL_SLVERR_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrIsr
+ */
+#define XFPD_SLCR_ISR    ( ( XFPD_SLCR_BASEADDR ) + 0x00000008UL )
+#define XFPD_SLCR_ISR_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_ISR_ADDR_DECD_ERR_SHIFT   0UL
+#define XFPD_SLCR_ISR_ADDR_DECD_ERR_WIDTH   1UL
+#define XFPD_SLCR_ISR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XFPD_SLCR_ISR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrImr
+ */
+#define XFPD_SLCR_IMR    ( ( XFPD_SLCR_BASEADDR ) + 0x0000000CUL )
+#define XFPD_SLCR_IMR_RSTVAL   0x00000001UL
+
+#define XFPD_SLCR_IMR_ADDR_DECD_ERR_SHIFT   0UL
+#define XFPD_SLCR_IMR_ADDR_DECD_ERR_WIDTH   1UL
+#define XFPD_SLCR_IMR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XFPD_SLCR_IMR_ADDR_DECD_ERR_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdSlcrIer
+ */
+#define XFPD_SLCR_IER    ( ( XFPD_SLCR_BASEADDR ) + 0x00000010UL )
+#define XFPD_SLCR_IER_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_IER_ADDR_DECD_ERR_SHIFT   0UL
+#define XFPD_SLCR_IER_ADDR_DECD_ERR_WIDTH   1UL
+#define XFPD_SLCR_IER_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XFPD_SLCR_IER_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrIdr
+ */
+#define XFPD_SLCR_IDR    ( ( XFPD_SLCR_BASEADDR ) + 0x00000014UL )
+#define XFPD_SLCR_IDR_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_IDR_ADDR_DECD_ERR_SHIFT   0UL
+#define XFPD_SLCR_IDR_ADDR_DECD_ERR_WIDTH   1UL
+#define XFPD_SLCR_IDR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XFPD_SLCR_IDR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrItr
+ */
+#define XFPD_SLCR_ITR    ( ( XFPD_SLCR_BASEADDR ) + 0x00000018UL )
+#define XFPD_SLCR_ITR_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_ITR_ADDR_DECD_ERR_SHIFT   0UL
+#define XFPD_SLCR_ITR_ADDR_DECD_ERR_WIDTH   1UL
+#define XFPD_SLCR_ITR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XFPD_SLCR_ITR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrWdtClkSel
+ */
+#define XFPD_SLCR_WDT_CLK_SEL    ( ( XFPD_SLCR_BASEADDR ) + 0x00000100UL )
+#define XFPD_SLCR_WDT_CLK_SEL_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_WDT_CLK_SEL_SHIFT   0UL
+#define XFPD_SLCR_WDT_CLK_SEL_WIDTH   1UL
+#define XFPD_SLCR_WDT_CLK_SEL_MASK    0x00000001UL
+#define XFPD_SLCR_WDT_CLK_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrIntFpd
+ */
+#define XFPD_SLCR_INT_FPD    ( ( XFPD_SLCR_BASEADDR ) + 0x00000200UL )
+#define XFPD_SLCR_INT_FPD_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_INT_FPD_GFM_SEL_SHIFT   0UL
+#define XFPD_SLCR_INT_FPD_GFM_SEL_WIDTH   1UL
+#define XFPD_SLCR_INT_FPD_GFM_SEL_MASK    0x00000001UL
+#define XFPD_SLCR_INT_FPD_GFM_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrGpu
+ */
+#define XFPD_SLCR_GPU    ( ( XFPD_SLCR_BASEADDR ) + 0x0000100CUL )
+#define XFPD_SLCR_GPU_RSTVAL   0x00000007UL
+
+#define XFPD_SLCR_GPU_ARCACHE_SHIFT   7UL
+#define XFPD_SLCR_GPU_ARCACHE_WIDTH   4UL
+#define XFPD_SLCR_GPU_ARCACHE_MASK    0x00000780UL
+#define XFPD_SLCR_GPU_ARCACHE_DEFVAL  0x0UL
+
+#define XFPD_SLCR_GPU_AWCACHE_SHIFT   3UL
+#define XFPD_SLCR_GPU_AWCACHE_WIDTH   4UL
+#define XFPD_SLCR_GPU_AWCACHE_MASK    0x00000078UL
+#define XFPD_SLCR_GPU_AWCACHE_DEFVAL  0x0UL
+
+#define XFPD_SLCR_GPU_PP1_IDLE_SHIFT   2UL
+#define XFPD_SLCR_GPU_PP1_IDLE_WIDTH   1UL
+#define XFPD_SLCR_GPU_PP1_IDLE_MASK    0x00000004UL
+#define XFPD_SLCR_GPU_PP1_IDLE_DEFVAL  0x1UL
+
+#define XFPD_SLCR_GPU_PP0_IDLE_SHIFT   1UL
+#define XFPD_SLCR_GPU_PP0_IDLE_WIDTH   1UL
+#define XFPD_SLCR_GPU_PP0_IDLE_MASK    0x00000002UL
+#define XFPD_SLCR_GPU_PP0_IDLE_DEFVAL  0x1UL
+
+#define XFPD_SLCR_GPU_IDLE_SHIFT   0UL
+#define XFPD_SLCR_GPU_IDLE_WIDTH   1UL
+#define XFPD_SLCR_GPU_IDLE_MASK    0x00000001UL
+#define XFPD_SLCR_GPU_IDLE_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdSlcrGdmaCfg
+ */
+#define XFPD_SLCR_GDMA_CFG    ( ( XFPD_SLCR_BASEADDR ) + 0x00003000UL )
+#define XFPD_SLCR_GDMA_CFG_RSTVAL   0x00000048UL
+
+#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_SHIFT   5UL
+#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_WIDTH   2UL
+#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_MASK    0x00000060UL
+#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_DEFVAL  0x2UL
+
+#define XFPD_SLCR_GDMA_CFG_NUM_CH_SHIFT   0UL
+#define XFPD_SLCR_GDMA_CFG_NUM_CH_WIDTH   5UL
+#define XFPD_SLCR_GDMA_CFG_NUM_CH_MASK    0x0000001fUL
+#define XFPD_SLCR_GDMA_CFG_NUM_CH_DEFVAL  0x8UL
+
+/**
+ * Register: XfpdSlcrGdma
+ */
+#define XFPD_SLCR_GDMA    ( ( XFPD_SLCR_BASEADDR ) + 0x00003010UL )
+#define XFPD_SLCR_GDMA_RSTVAL   0x00003b3bUL
+
+#define XFPD_SLCR_GDMA_RAM1_EMAB_SHIFT   12UL
+#define XFPD_SLCR_GDMA_RAM1_EMAB_WIDTH   3UL
+#define XFPD_SLCR_GDMA_RAM1_EMAB_MASK    0x00007000UL
+#define XFPD_SLCR_GDMA_RAM1_EMAB_DEFVAL  0x3UL
+
+#define XFPD_SLCR_GDMA_RAM1_EMASA_SHIFT   11UL
+#define XFPD_SLCR_GDMA_RAM1_EMASA_WIDTH   1UL
+#define XFPD_SLCR_GDMA_RAM1_EMASA_MASK    0x00000800UL
+#define XFPD_SLCR_GDMA_RAM1_EMASA_DEFVAL  0x1UL
+
+#define XFPD_SLCR_GDMA_RAM1_EMAA_SHIFT   8UL
+#define XFPD_SLCR_GDMA_RAM1_EMAA_WIDTH   3UL
+#define XFPD_SLCR_GDMA_RAM1_EMAA_MASK    0x00000700UL
+#define XFPD_SLCR_GDMA_RAM1_EMAA_DEFVAL  0x3UL
+
+#define XFPD_SLCR_GDMA_RAM0_EMAB_SHIFT   4UL
+#define XFPD_SLCR_GDMA_RAM0_EMAB_WIDTH   3UL
+#define XFPD_SLCR_GDMA_RAM0_EMAB_MASK    0x00000070UL
+#define XFPD_SLCR_GDMA_RAM0_EMAB_DEFVAL  0x3UL
+
+#define XFPD_SLCR_GDMA_RAM0_EMASA_SHIFT   3UL
+#define XFPD_SLCR_GDMA_RAM0_EMASA_WIDTH   1UL
+#define XFPD_SLCR_GDMA_RAM0_EMASA_MASK    0x00000008UL
+#define XFPD_SLCR_GDMA_RAM0_EMASA_DEFVAL  0x1UL
+
+#define XFPD_SLCR_GDMA_RAM0_EMAA_SHIFT   0UL
+#define XFPD_SLCR_GDMA_RAM0_EMAA_WIDTH   3UL
+#define XFPD_SLCR_GDMA_RAM0_EMAA_MASK    0x00000007UL
+#define XFPD_SLCR_GDMA_RAM0_EMAA_DEFVAL  0x3UL
+
+/**
+ * Register: XfpdSlcrAfiFs
+ */
+#define XFPD_SLCR_AFI_FS    ( ( XFPD_SLCR_BASEADDR ) + 0x00005000UL )
+#define XFPD_SLCR_AFI_FS_RSTVAL   0x00000a00UL
+
+#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_SHIFT   10UL
+#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_WIDTH   2UL
+#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_MASK    0x00000c00UL
+#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_DEFVAL  0x2UL
+
+#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_SHIFT   8UL
+#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_WIDTH   2UL
+#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_MASK    0x00000300UL
+#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_DEFVAL  0x2UL
+
+/**
+ * Register: XfpdSlcrErrAtbIsr
+ */
+#define XFPD_SLCR_ERR_ATB_ISR    ( ( XFPD_SLCR_BASEADDR ) + 0x00006000UL )
+#define XFPD_SLCR_ERR_ATB_ISR_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_SHIFT   2UL
+#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_MASK    0x00000004UL
+#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_DEFVAL  0x0UL
+
+#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_SHIFT   1UL
+#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_MASK    0x00000002UL
+#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_DEFVAL  0x0UL
+
+#define XFPD_SLCR_ERR_ATB_ISR_FPDS_SHIFT   0UL
+#define XFPD_SLCR_ERR_ATB_ISR_FPDS_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_ISR_FPDS_MASK    0x00000001UL
+#define XFPD_SLCR_ERR_ATB_ISR_FPDS_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrErrAtbImr
+ */
+#define XFPD_SLCR_ERR_ATB_IMR    ( ( XFPD_SLCR_BASEADDR ) + 0x00006004UL )
+#define XFPD_SLCR_ERR_ATB_IMR_RSTVAL   0x00000007UL
+
+#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_SHIFT   2UL
+#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_MASK    0x00000004UL
+#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_DEFVAL  0x1UL
+
+#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_SHIFT   1UL
+#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_MASK    0x00000002UL
+#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_DEFVAL  0x1UL
+
+#define XFPD_SLCR_ERR_ATB_IMR_FPDS_SHIFT   0UL
+#define XFPD_SLCR_ERR_ATB_IMR_FPDS_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_IMR_FPDS_MASK    0x00000001UL
+#define XFPD_SLCR_ERR_ATB_IMR_FPDS_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdSlcrErrAtbIer
+ */
+#define XFPD_SLCR_ERR_ATB_IER    ( ( XFPD_SLCR_BASEADDR ) + 0x00006008UL )
+#define XFPD_SLCR_ERR_ATB_IER_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_SHIFT   2UL
+#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_MASK    0x00000004UL
+#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_DEFVAL  0x0UL
+
+#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_SHIFT   1UL
+#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_MASK    0x00000002UL
+#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_DEFVAL  0x0UL
+
+#define XFPD_SLCR_ERR_ATB_IER_FPDS_SHIFT   0UL
+#define XFPD_SLCR_ERR_ATB_IER_FPDS_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_IER_FPDS_MASK    0x00000001UL
+#define XFPD_SLCR_ERR_ATB_IER_FPDS_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrErrAtbIdr
+ */
+#define XFPD_SLCR_ERR_ATB_IDR    ( ( XFPD_SLCR_BASEADDR ) + 0x0000600CUL )
+#define XFPD_SLCR_ERR_ATB_IDR_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_SHIFT   2UL
+#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_MASK    0x00000004UL
+#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_DEFVAL  0x0UL
+
+#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_SHIFT   1UL
+#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_MASK    0x00000002UL
+#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_DEFVAL  0x0UL
+
+#define XFPD_SLCR_ERR_ATB_IDR_FPDS_SHIFT   0UL
+#define XFPD_SLCR_ERR_ATB_IDR_FPDS_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_IDR_FPDS_MASK    0x00000001UL
+#define XFPD_SLCR_ERR_ATB_IDR_FPDS_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrAtbCmdstore
+ */
+#define XFPD_SLCR_ATB_CMDSTORE    ( ( XFPD_SLCR_BASEADDR ) + 0x00006010UL )
+#define XFPD_SLCR_ATB_CMDSTORE_RSTVAL   0x00000007UL
+
+#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_SHIFT   2UL
+#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_WIDTH   1UL
+#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_MASK    0x00000004UL
+#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_DEFVAL  0x1UL
+
+#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_SHIFT   1UL
+#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_WIDTH   1UL
+#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_MASK    0x00000002UL
+#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_DEFVAL  0x1UL
+
+#define XFPD_SLCR_ATB_CMDSTORE_FPDS_SHIFT   0UL
+#define XFPD_SLCR_ATB_CMDSTORE_FPDS_WIDTH   1UL
+#define XFPD_SLCR_ATB_CMDSTORE_FPDS_MASK    0x00000001UL
+#define XFPD_SLCR_ATB_CMDSTORE_FPDS_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdSlcrAtbRespEn
+ */
+#define XFPD_SLCR_ATB_RESP_EN    ( ( XFPD_SLCR_BASEADDR ) + 0x00006014UL )
+#define XFPD_SLCR_ATB_RESP_EN_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_SHIFT   2UL
+#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_WIDTH   1UL
+#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_MASK    0x00000004UL
+#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_DEFVAL  0x0UL
+
+#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_SHIFT   1UL
+#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_WIDTH   1UL
+#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_MASK    0x00000002UL
+#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_DEFVAL  0x0UL
+
+#define XFPD_SLCR_ATB_RESP_EN_FPDS_SHIFT   0UL
+#define XFPD_SLCR_ATB_RESP_EN_FPDS_WIDTH   1UL
+#define XFPD_SLCR_ATB_RESP_EN_FPDS_MASK    0x00000001UL
+#define XFPD_SLCR_ATB_RESP_EN_FPDS_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrAtbResptype
+ */
+#define XFPD_SLCR_ATB_RESPTYPE    ( ( XFPD_SLCR_BASEADDR ) + 0x00006018UL )
+#define XFPD_SLCR_ATB_RESPTYPE_RSTVAL   0x00000007UL
+
+#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_SHIFT   2UL
+#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_WIDTH   1UL
+#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_MASK    0x00000004UL
+#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_DEFVAL  0x1UL
+
+#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_SHIFT   1UL
+#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_WIDTH   1UL
+#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_MASK    0x00000002UL
+#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_DEFVAL  0x1UL
+
+#define XFPD_SLCR_ATB_RESPTYPE_FPDS_SHIFT   0UL
+#define XFPD_SLCR_ATB_RESPTYPE_FPDS_WIDTH   1UL
+#define XFPD_SLCR_ATB_RESPTYPE_FPDS_MASK    0x00000001UL
+#define XFPD_SLCR_ATB_RESPTYPE_FPDS_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdSlcrAtbPrescale
+ */
+#define XFPD_SLCR_ATB_PRESCALE    ( ( XFPD_SLCR_BASEADDR ) + 0x00006020UL )
+#define XFPD_SLCR_ATB_PRESCALE_RSTVAL   0x0000ffffUL
+
+#define XFPD_SLCR_ATB_PRESCALE_EN_SHIFT   16UL
+#define XFPD_SLCR_ATB_PRESCALE_EN_WIDTH   1UL
+#define XFPD_SLCR_ATB_PRESCALE_EN_MASK    0x00010000UL
+#define XFPD_SLCR_ATB_PRESCALE_EN_DEFVAL  0x0UL
+
+#define XFPD_SLCR_ATB_PRESCALE_VAL_SHIFT   0UL
+#define XFPD_SLCR_ATB_PRESCALE_VAL_WIDTH   16UL
+#define XFPD_SLCR_ATB_PRESCALE_VAL_MASK    0x0000ffffUL
+#define XFPD_SLCR_ATB_PRESCALE_VAL_DEFVAL  0xffffUL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XFPD_SLCR_H__ */

lib/bsp/standalone/src/cortexa53/xfpd_slcr_secure.h

@@ -0,0 +1,277 @@
+/* ### HEADER ### */
+
+#ifndef __XFPD_SLCR_SECURE_H__
+#define __XFPD_SLCR_SECURE_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XfpdSlcrSecure Base Address
+ */
+#define XFPD_SLCR_SECURE_BASEADDR      0xFD690000UL
+
+/**
+ * Register: XfpdSlcrSecCtrl
+ */
+#define XFPD_SLCR_SEC_CTRL    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000004UL )
+#define XFPD_SLCR_SEC_CTRL_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_SHIFT   0UL
+#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_WIDTH   1UL
+#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_MASK    0x00000001UL
+#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrSecIsr
+ */
+#define XFPD_SLCR_SEC_ISR    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000008UL )
+#define XFPD_SLCR_SEC_ISR_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_SHIFT   0UL
+#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_WIDTH   1UL
+#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrSecImr
+ */
+#define XFPD_SLCR_SEC_IMR    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x0000000CUL )
+#define XFPD_SLCR_SEC_IMR_RSTVAL   0x00000001UL
+
+#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_SHIFT   0UL
+#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_WIDTH   1UL
+#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdSlcrSecIer
+ */
+#define XFPD_SLCR_SEC_IER    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000010UL )
+#define XFPD_SLCR_SEC_IER_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_SHIFT   0UL
+#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_WIDTH   1UL
+#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrSecIdr
+ */
+#define XFPD_SLCR_SEC_IDR    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000014UL )
+#define XFPD_SLCR_SEC_IDR_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_SHIFT   0UL
+#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_WIDTH   1UL
+#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrSecItr
+ */
+#define XFPD_SLCR_SEC_ITR    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000018UL )
+#define XFPD_SLCR_SEC_ITR_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_SHIFT   0UL
+#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_WIDTH   1UL
+#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrSecSata
+ */
+#define XFPD_SLCR_SEC_SATA    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000020UL )
+#define XFPD_SLCR_SEC_SATA_RSTVAL   0x0000000eUL
+
+#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_SHIFT   3UL
+#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_WIDTH   1UL
+#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_MASK    0x00000008UL
+#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_SHIFT   2UL
+#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_WIDTH   1UL
+#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_MASK    0x00000004UL
+#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_SATA_TZ_AXIS_SHIFT   1UL
+#define XFPD_SLCR_SEC_SATA_TZ_AXIS_WIDTH   1UL
+#define XFPD_SLCR_SEC_SATA_TZ_AXIS_MASK    0x00000002UL
+#define XFPD_SLCR_SEC_SATA_TZ_AXIS_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_SATA_TZ_EN_SHIFT   0UL
+#define XFPD_SLCR_SEC_SATA_TZ_EN_WIDTH   1UL
+#define XFPD_SLCR_SEC_SATA_TZ_EN_MASK    0x00000001UL
+#define XFPD_SLCR_SEC_SATA_TZ_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrSecPcie
+ */
+#define XFPD_SLCR_SEC_PCIE    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000030UL )
+#define XFPD_SLCR_SEC_PCIE_RSTVAL   0x01ffffffUL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_SHIFT   24UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_MASK    0x01000000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_SHIFT   23UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_MASK    0x00800000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_SHIFT   22UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_MASK    0x00400000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_SHIFT   21UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_MASK    0x00200000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_SHIFT   20UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_MASK    0x00100000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_SHIFT   19UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_MASK    0x00080000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_SHIFT   18UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_MASK    0x00040000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_SHIFT   17UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_MASK    0x00020000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_SHIFT   16UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_MASK    0x00010000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_SHIFT   15UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_MASK    0x00008000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_SHIFT   14UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_MASK    0x00004000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_SHIFT   13UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_MASK    0x00002000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_SHIFT   12UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_MASK    0x00001000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_SHIFT   11UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_MASK    0x00000800UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_SHIFT   10UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_MASK    0x00000400UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_SHIFT   9UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_MASK    0x00000200UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_SHIFT   8UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_MASK    0x00000100UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_SHIFT   7UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_MASK    0x00000080UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_SHIFT   6UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_MASK    0x00000040UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_SHIFT   5UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_MASK    0x00000020UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_SHIFT   4UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_MASK    0x00000010UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_SHIFT   3UL
+#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_MASK    0x00000008UL
+#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_SHIFT   2UL
+#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_MASK    0x00000004UL
+#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_SHIFT   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_MASK    0x00000002UL
+#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_SHIFT   0UL
+#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_MASK    0x00000001UL
+#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdSlcrSecDpdma
+ */
+#define XFPD_SLCR_SEC_DPDMA    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000040UL )
+#define XFPD_SLCR_SEC_DPDMA_RSTVAL   0x00000001UL
+
+#define XFPD_SLCR_SEC_DPDMA_TZ_SHIFT   0UL
+#define XFPD_SLCR_SEC_DPDMA_TZ_WIDTH   1UL
+#define XFPD_SLCR_SEC_DPDMA_TZ_MASK    0x00000001UL
+#define XFPD_SLCR_SEC_DPDMA_TZ_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdSlcrSecGdma
+ */
+#define XFPD_SLCR_SEC_GDMA    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000050UL )
+#define XFPD_SLCR_SEC_GDMA_RSTVAL   0x000000ffUL
+
+#define XFPD_SLCR_SEC_GDMA_TZ_SHIFT   0UL
+#define XFPD_SLCR_SEC_GDMA_TZ_WIDTH   8UL
+#define XFPD_SLCR_SEC_GDMA_TZ_MASK    0x000000ffUL
+#define XFPD_SLCR_SEC_GDMA_TZ_DEFVAL  0xffUL
+
+/**
+ * Register: XfpdSlcrSecGic
+ */
+#define XFPD_SLCR_SEC_GIC    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000060UL )
+#define XFPD_SLCR_SEC_GIC_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_SEC_GIC_CFG_DIS_SHIFT   0UL
+#define XFPD_SLCR_SEC_GIC_CFG_DIS_WIDTH   1UL
+#define XFPD_SLCR_SEC_GIC_CFG_DIS_MASK    0x00000001UL
+#define XFPD_SLCR_SEC_GIC_CFG_DIS_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XFPD_SLCR_SECURE_H__ */

lib/bsp/standalone/src/cortexa53/xfpd_xmpu_sink.h

@@ -0,0 +1,81 @@
+/* ### HEADER ### */
+
+#ifndef __XFPD_XMPU_SINK_H__
+#define __XFPD_XMPU_SINK_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XfpdXmpuSink Base Address
+ */
+#define XFPD_XMPU_SINK_BASEADDR      0xFD4F0000UL
+
+/**
+ * Register: XfpdXmpuSinkErrSts
+ */
+#define XFPD_XMPU_SINK_ERR_STS    ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF00UL )
+#define XFPD_XMPU_SINK_ERR_STS_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_SINK_ERR_STS_RDWR_SHIFT   31UL
+#define XFPD_XMPU_SINK_ERR_STS_RDWR_WIDTH   1UL
+#define XFPD_XMPU_SINK_ERR_STS_RDWR_MASK    0x80000000UL
+#define XFPD_XMPU_SINK_ERR_STS_RDWR_DEFVAL  0x0UL
+
+#define XFPD_XMPU_SINK_ERR_STS_ADDR_SHIFT   0UL
+#define XFPD_XMPU_SINK_ERR_STS_ADDR_WIDTH   12UL
+#define XFPD_XMPU_SINK_ERR_STS_ADDR_MASK    0x00000fffUL
+#define XFPD_XMPU_SINK_ERR_STS_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuSinkIsr
+ */
+#define XFPD_XMPU_SINK_ISR    ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF10UL )
+#define XFPD_XMPU_SINK_ISR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_SINK_ISRADDRDECDERR_SHIFT   0UL
+#define XFPD_XMPU_SINK_ISRADDRDECDERR_WIDTH   1UL
+#define XFPD_XMPU_SINK_ISRADDRDECDERR_MASK    0x00000001UL
+#define XFPD_XMPU_SINK_ISRADDRDECDERR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuSinkImr
+ */
+#define XFPD_XMPU_SINK_IMR    ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF14UL )
+#define XFPD_XMPU_SINK_IMR_RSTVAL   0x00000001UL
+
+#define XFPD_XMPU_SINK_IMRADDRDECDERR_SHIFT   0UL
+#define XFPD_XMPU_SINK_IMRADDRDECDERR_WIDTH   1UL
+#define XFPD_XMPU_SINK_IMRADDRDECDERR_MASK    0x00000001UL
+#define XFPD_XMPU_SINK_IMRADDRDECDERR_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdXmpuSinkIer
+ */
+#define XFPD_XMPU_SINK_IER    ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF18UL )
+#define XFPD_XMPU_SINK_IER_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_SINK_IERADDRDECDERR_SHIFT   0UL
+#define XFPD_XMPU_SINK_IERADDRDECDERR_WIDTH   1UL
+#define XFPD_XMPU_SINK_IERADDRDECDERR_MASK    0x00000001UL
+#define XFPD_XMPU_SINK_IERADDRDECDERR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuSinkIdr
+ */
+#define XFPD_XMPU_SINK_IDR    ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF1CUL )
+#define XFPD_XMPU_SINK_IDR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_SINK_IDRADDRDECDERR_SHIFT   0UL
+#define XFPD_XMPU_SINK_IDRADDRDECDERR_WIDTH   1UL
+#define XFPD_XMPU_SINK_IDRADDRDECDERR_MASK    0x00000001UL
+#define XFPD_XMPU_SINK_IDRADDRDECDERR_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XFPD_XMPU_SINK_H__ */

lib/bsp/standalone/src/cortexa53/xil_cache.c

@@ -468,13 +468,13 @@ void Xil_DCacheFlushRange(INTPTR  adr, u32 len)
 	if (len != 0x00000000U) {
 		end = tempadr + len;
 		tempend = end;
-		if (tempadr & (cacheline - 0x00000001U) != 0x00000000U) {
-			tempadr &= ~(cacheline - 0x00000001U);
+		if ((tempadr & (0x3F)) != 0) {
+			tempadr &= ~(0x3F);
 			Xil_DCacheFlushLine(tempadr);
 			tempadr += cacheline;
 		}
-		if (tempend & (cacheline-0x00000001U) != 0x00000000U) {
-			tempend &= ~(cacheline - 0x00000001U);
+		if ((tempend & (0x3F)) != 0) {
+			tempend &= ~(0x3F);
 			Xil_DCacheFlushLine(tempend);
 		}
 

lib/bsp/standalone/src/cortexa53/xil_io.h

@@ -67,15 +67,10 @@ extern "C" {
 
 /***************** Macros (Inline Functions) Definitions *********************/
 
-#if defined __GNUC__
 #  define SYNCHRONIZE_IO	dmb()
 #  define INST_SYNC		isb()
 #  define DATA_SYNC		dsb()
-#else
-#  define SYNCHRONIZE_IO
-#  define INST_SYNC
-#  define DATA_SYNC
-#endif /* __GNUC__ */
+
 
 /*****************************************************************************/
 /**

lib/bsp/standalone/src/cortexa53/xil_mmu.c

@@ -108,53 +108,3 @@ void Xil_SetTlbAttributes(INTPTR Addr, u64 attrib)
     isb(); /* synchronize context on this processor */
 
 }
-
-/*****************************************************************************
-*
-* Invalidate the caches and then enable MMU for Cortex A53 processor.
-*
-* @param	None.
-* @return	None.
-*
-******************************************************************************/
-void Xil_EnableMMU(void)
-{
-	u32 Reg;
-	Xil_DCacheInvalidate();
-	Xil_ICacheInvalidate();
-
-	Reg = mfcp(SCTLR_EL1);
-
-	Reg |= 0x00000001U;
-	/* Enable MMU */
-	mtcp(SCTLR_EL1, Reg);
-
-	dsb(); /* ensure completion of the BP and TLB invalidation */
-    isb(); /* synchronize context on this processor */
-}
-
-/*****************************************************************************
-*
-* Disable MMU for Cortex A53 processors. This function invalidates the TLBs
-* and flushed the D Caches before disabling the MMU and D cache.
-*
-* @param	None.
-*
-* @return	None.
-*
-******************************************************************************/
-void Xil_DisableMMU(void)
-{
-
-	u32 Reg;
-
-	mtcptlbi(ALLE3);
-	Xil_DCacheFlush();
-
-	Reg = mfcp(SCTLR_EL1);
-	Reg &= ~(0x00000001U);
-	/*Disable mmu*/
-	mtcp(SCTLR_EL1, Reg);
-	dsb(); /* ensure completion of the BP and TLB invalidation */
-    isb(); /* synchronize context on this processor */
-}

lib/bsp/standalone/src/cortexa53/xil_mmu.h

@@ -71,8 +71,6 @@ extern "C" {
 /************************** Function Prototypes ******************************/
 
 void Xil_SetTlbAttributes(INTPTR Addr, u64 attrib);
-void Xil_EnableMMU(void);
-void Xil_DisableMMU(void);
 
 #ifdef __cplusplus
 }

lib/bsp/standalone/src/cortexa53/xiou_secure_slcr.h

@@ -0,0 +1,174 @@
+/* ### HEADER ### */
+
+#ifndef __XIOU_SECURE_SLCR_H__
+#define __XIOU_SECURE_SLCR_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XiouSecureSlcr Base Address
+ */
+#define XIOU_SECURE_SLCR_BASEADDR      0xFF240000UL
+
+/**
+ * Register: XiouSecSlcrAxiWprtcn
+ */
+#define XIOU_SEC_SLCR_AXI_WPRTCN    ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000000UL )
+#define XIOU_SEC_SLCR_AXI_WPRTCN_RSTVAL   0x00000000UL
+
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_SHIFT   25UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_MASK    0x0e000000UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_SHIFT   22UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_MASK    0x01c00000UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_SHIFT   19UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_MASK    0x00380000UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_SHIFT   16UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_MASK    0x00070000UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT   9UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK    0x00000e00UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT   6UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK    0x000001c0UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT   3UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK    0x00000038UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT   0UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK    0x00000007UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSecSlcrAxiRprtcn
+ */
+#define XIOU_SEC_SLCR_AXI_RPRTCN    ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000004UL )
+#define XIOU_SEC_SLCR_AXI_RPRTCN_RSTVAL   0x00000000UL
+
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_SHIFT   22UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_MASK    0x01c00000UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_SHIFT   19UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_MASK    0x00380000UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_SHIFT   16UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_MASK    0x00070000UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT   9UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK    0x00000e00UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT   6UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK    0x000001c0UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT   3UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK    0x00000038UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT   0UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK    0x00000007UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSecSlcrCtrl
+ */
+#define XIOU_SEC_SLCR_CTRL    ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000040UL )
+#define XIOU_SEC_SLCR_CTRL_RSTVAL   0x00000000UL
+
+#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_SHIFT   0UL
+#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_WIDTH   1UL
+#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_MASK    0x00000001UL
+#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSecSlcrIsr
+ */
+#define XIOU_SEC_SLCR_ISR    ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000044UL )
+#define XIOU_SEC_SLCR_ISR_RSTVAL   0x00000000UL
+
+#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_SHIFT   0UL
+#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_WIDTH   1UL
+#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSecSlcrImr
+ */
+#define XIOU_SEC_SLCR_IMR    ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000048UL )
+#define XIOU_SEC_SLCR_IMR_RSTVAL   0x00000001UL
+
+#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_SHIFT   0UL
+#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_WIDTH   1UL
+#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_DEFVAL  0x1UL
+
+/**
+ * Register: XiouSecSlcrIer
+ */
+#define XIOU_SEC_SLCR_IER    ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x0000004CUL )
+#define XIOU_SEC_SLCR_IER_RSTVAL   0x00000000UL
+
+#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_SHIFT   0UL
+#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_WIDTH   1UL
+#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSecSlcrIdr
+ */
+#define XIOU_SEC_SLCR_IDR    ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000050UL )
+#define XIOU_SEC_SLCR_IDR_RSTVAL   0x00000000UL
+
+#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_SHIFT   0UL
+#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_WIDTH   1UL
+#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSecSlcrItr
+ */
+#define XIOU_SEC_SLCR_ITR    ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000054UL )
+#define XIOU_SEC_SLCR_ITR_RSTVAL   0x00000000UL
+
+#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_SHIFT   0UL
+#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_WIDTH   1UL
+#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XIOU_SECURE_SLCR_H__ */

lib/bsp/standalone/src/cortexa53/xlpd_slcr_secure.h

@@ -0,0 +1,141 @@
+/* ### HEADER ### */
+
+#ifndef __XLPD_SLCR_SECURE_H__
+#define __XLPD_SLCR_SECURE_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XlpdSlcrSecure Base Address
+ */
+#define XLPD_SLCR_SECURE_BASEADDR      0xFF4B0000UL
+
+/**
+ * Register: XlpdSlcrSecCtrl
+ */
+#define XLPD_SLCR_SEC_CTRL    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000004UL )
+#define XLPD_SLCR_SEC_CTRL_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_SHIFT   0UL
+#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_WIDTH   1UL
+#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_MASK    0x00000001UL
+#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSecIsr
+ */
+#define XLPD_SLCR_SEC_ISR    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000008UL )
+#define XLPD_SLCR_SEC_ISR_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_SHIFT   0UL
+#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_WIDTH   1UL
+#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSecImr
+ */
+#define XLPD_SLCR_SEC_IMR    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x0000000CUL )
+#define XLPD_SLCR_SEC_IMR_RSTVAL   0x00000001UL
+
+#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_SHIFT   0UL
+#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_WIDTH   1UL
+#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrSecIer
+ */
+#define XLPD_SLCR_SEC_IER    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000010UL )
+#define XLPD_SLCR_SEC_IER_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_SHIFT   0UL
+#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_WIDTH   1UL
+#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSecIdr
+ */
+#define XLPD_SLCR_SEC_IDR    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000014UL )
+#define XLPD_SLCR_SEC_IDR_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_SHIFT   0UL
+#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_WIDTH   1UL
+#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSecItr
+ */
+#define XLPD_SLCR_SEC_ITR    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000018UL )
+#define XLPD_SLCR_SEC_ITR_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_SHIFT   0UL
+#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_WIDTH   1UL
+#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSecRpu
+ */
+#define XLPD_SLCR_SEC_RPU    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000020UL )
+#define XLPD_SLCR_SEC_RPU_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SEC_RPU_TZ_R5_1_SHIFT   1UL
+#define XLPD_SLCR_SEC_RPU_TZ_R5_1_WIDTH   1UL
+#define XLPD_SLCR_SEC_RPU_TZ_R5_1_MASK    0x00000002UL
+#define XLPD_SLCR_SEC_RPU_TZ_R5_1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_SEC_RPU_TZ_R5_0_SHIFT   0UL
+#define XLPD_SLCR_SEC_RPU_TZ_R5_0_WIDTH   1UL
+#define XLPD_SLCR_SEC_RPU_TZ_R5_0_MASK    0x00000001UL
+#define XLPD_SLCR_SEC_RPU_TZ_R5_0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSecAdma
+ */
+#define XLPD_SLCR_SEC_ADMA    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000024UL )
+#define XLPD_SLCR_SEC_ADMA_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SEC_ADMA_TZ_SHIFT   0UL
+#define XLPD_SLCR_SEC_ADMA_TZ_WIDTH   8UL
+#define XLPD_SLCR_SEC_ADMA_TZ_MASK    0x000000ffUL
+#define XLPD_SLCR_SEC_ADMA_TZ_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSecSafetyChk
+ */
+#define XLPD_SLCR_SEC_SAFETY_CHK    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000030UL )
+#define XLPD_SLCR_SEC_SAFETY_CHK_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_SHIFT   0UL
+#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_WIDTH   32UL
+#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_MASK    0xffffffffUL
+#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSecUsb
+ */
+#define XLPD_SLCR_SEC_USB    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000034UL )
+#define XLPD_SLCR_SEC_USB_RSTVAL   0x00000003UL
+
+#define XLPD_SLCR_SEC_USB_TZ_USB3_1_SHIFT   1UL
+#define XLPD_SLCR_SEC_USB_TZ_USB3_1_WIDTH   1UL
+#define XLPD_SLCR_SEC_USB_TZ_USB3_1_MASK    0x00000002UL
+#define XLPD_SLCR_SEC_USB_TZ_USB3_1_DEFVAL  0x1UL
+
+#define XLPD_SLCR_SEC_USB_TZ_USB3_0_SHIFT   0UL
+#define XLPD_SLCR_SEC_USB_TZ_USB3_0_WIDTH   1UL
+#define XLPD_SLCR_SEC_USB_TZ_USB3_0_MASK    0x00000001UL
+#define XLPD_SLCR_SEC_USB_TZ_USB3_0_DEFVAL  0x1UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XLPD_SLCR_SECURE_H__ */

lib/bsp/standalone/src/cortexa53/xlpd_xppu.h

@@ -0,0 +1,858 @@
+/* ### HEADER ### */
+
+#ifndef __XLPD_XPPU_H__
+#define __XLPD_XPPU_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XlpdXppu Base Address
+ */
+#define XLPD_XPPU_BASEADDR      0xFF980000UL
+
+/**
+ * Register: XlpdXppuCtrl
+ */
+#define XLPD_XPPU_CTRL    ( ( XLPD_XPPU_BASEADDR ) + 0x00000000UL )
+#define XLPD_XPPU_CTRL_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_CTRL_APER_PARITY_EN_SHIFT   2UL
+#define XLPD_XPPU_CTRL_APER_PARITY_EN_WIDTH   1UL
+#define XLPD_XPPU_CTRL_APER_PARITY_EN_MASK    0x00000004UL
+#define XLPD_XPPU_CTRL_APER_PARITY_EN_DEFVAL  0x0UL
+
+#define XLPD_XPPU_CTRL_MID_PARITY_EN_SHIFT   1UL
+#define XLPD_XPPU_CTRL_MID_PARITY_EN_WIDTH   1UL
+#define XLPD_XPPU_CTRL_MID_PARITY_EN_MASK    0x00000002UL
+#define XLPD_XPPU_CTRL_MID_PARITY_EN_DEFVAL  0x0UL
+
+#define XLPD_XPPU_CTRL_EN_SHIFT   0UL
+#define XLPD_XPPU_CTRL_EN_WIDTH   1UL
+#define XLPD_XPPU_CTRL_EN_MASK    0x00000001UL
+#define XLPD_XPPU_CTRL_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuErrSts1
+ */
+#define XLPD_XPPU_ERR_STS1    ( ( XLPD_XPPU_BASEADDR ) + 0x00000004UL )
+#define XLPD_XPPU_ERR_STS1_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_ERR_STS1_AXI_ADDR_SHIFT   0UL
+#define XLPD_XPPU_ERR_STS1_AXI_ADDR_WIDTH   32UL
+#define XLPD_XPPU_ERR_STS1_AXI_ADDR_MASK    0xffffffffUL
+#define XLPD_XPPU_ERR_STS1_AXI_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuErrSts2
+ */
+#define XLPD_XPPU_ERR_STS2    ( ( XLPD_XPPU_BASEADDR ) + 0x00000008UL )
+#define XLPD_XPPU_ERR_STS2_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_ERR_STS2_AXI_ID_SHIFT   0UL
+#define XLPD_XPPU_ERR_STS2_AXI_ID_WIDTH   16UL
+#define XLPD_XPPU_ERR_STS2_AXI_ID_MASK    0x0000ffffUL
+#define XLPD_XPPU_ERR_STS2_AXI_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuPoison
+ */
+#define XLPD_XPPU_POISON    ( ( XLPD_XPPU_BASEADDR ) + 0x0000000CUL )
+#define XLPD_XPPU_POISON_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_POISON_BASE_SHIFT   0UL
+#define XLPD_XPPU_POISON_BASE_WIDTH   20UL
+#define XLPD_XPPU_POISON_BASE_MASK    0x000fffffUL
+#define XLPD_XPPU_POISON_BASE_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuIsr
+ */
+#define XLPD_XPPU_ISR    ( ( XLPD_XPPU_BASEADDR ) + 0x00000010UL )
+#define XLPD_XPPU_ISR_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_ISR_APER_PARITY_SHIFT   7UL
+#define XLPD_XPPU_ISR_APER_PARITY_WIDTH   1UL
+#define XLPD_XPPU_ISR_APER_PARITY_MASK    0x00000080UL
+#define XLPD_XPPU_ISR_APER_PARITY_DEFVAL  0x0UL
+
+#define XLPD_XPPU_ISR_APER_TZ_SHIFT   6UL
+#define XLPD_XPPU_ISR_APER_TZ_WIDTH   1UL
+#define XLPD_XPPU_ISR_APER_TZ_MASK    0x00000040UL
+#define XLPD_XPPU_ISR_APER_TZ_DEFVAL  0x0UL
+
+#define XLPD_XPPU_ISR_APER_PERM_SHIFT   5UL
+#define XLPD_XPPU_ISR_APER_PERM_WIDTH   1UL
+#define XLPD_XPPU_ISR_APER_PERM_MASK    0x00000020UL
+#define XLPD_XPPU_ISR_APER_PERM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_ISR_MID_PARITY_SHIFT   3UL
+#define XLPD_XPPU_ISR_MID_PARITY_WIDTH   1UL
+#define XLPD_XPPU_ISR_MID_PARITY_MASK    0x00000008UL
+#define XLPD_XPPU_ISR_MID_PARITY_DEFVAL  0x0UL
+
+#define XLPD_XPPU_ISR_MID_RO_SHIFT   2UL
+#define XLPD_XPPU_ISR_MID_RO_WIDTH   1UL
+#define XLPD_XPPU_ISR_MID_RO_MASK    0x00000004UL
+#define XLPD_XPPU_ISR_MID_RO_DEFVAL  0x0UL
+
+#define XLPD_XPPU_ISR_MID_MISS_SHIFT   1UL
+#define XLPD_XPPU_ISR_MID_MISS_WIDTH   1UL
+#define XLPD_XPPU_ISR_MID_MISS_MASK    0x00000002UL
+#define XLPD_XPPU_ISR_MID_MISS_DEFVAL  0x0UL
+
+#define XLPD_XPPU_ISR_INV_APB_SHIFT   0UL
+#define XLPD_XPPU_ISR_INV_APB_WIDTH   1UL
+#define XLPD_XPPU_ISR_INV_APB_MASK    0x00000001UL
+#define XLPD_XPPU_ISR_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuImr
+ */
+#define XLPD_XPPU_IMR    ( ( XLPD_XPPU_BASEADDR ) + 0x00000014UL )
+#define XLPD_XPPU_IMR_RSTVAL   0x000000efUL
+
+#define XLPD_XPPU_IMR_APER_PARITY_SHIFT   7UL
+#define XLPD_XPPU_IMR_APER_PARITY_WIDTH   1UL
+#define XLPD_XPPU_IMR_APER_PARITY_MASK    0x00000080UL
+#define XLPD_XPPU_IMR_APER_PARITY_DEFVAL  0x1UL
+
+#define XLPD_XPPU_IMR_APER_TZ_SHIFT   6UL
+#define XLPD_XPPU_IMR_APER_TZ_WIDTH   1UL
+#define XLPD_XPPU_IMR_APER_TZ_MASK    0x00000040UL
+#define XLPD_XPPU_IMR_APER_TZ_DEFVAL  0x1UL
+
+#define XLPD_XPPU_IMR_APER_PERM_SHIFT   5UL
+#define XLPD_XPPU_IMR_APER_PERM_WIDTH   1UL
+#define XLPD_XPPU_IMR_APER_PERM_MASK    0x00000020UL
+#define XLPD_XPPU_IMR_APER_PERM_DEFVAL  0x1UL
+
+#define XLPD_XPPU_IMR_MID_PARITY_SHIFT   3UL
+#define XLPD_XPPU_IMR_MID_PARITY_WIDTH   1UL
+#define XLPD_XPPU_IMR_MID_PARITY_MASK    0x00000008UL
+#define XLPD_XPPU_IMR_MID_PARITY_DEFVAL  0x1UL
+
+#define XLPD_XPPU_IMR_MID_RO_SHIFT   2UL
+#define XLPD_XPPU_IMR_MID_RO_WIDTH   1UL
+#define XLPD_XPPU_IMR_MID_RO_MASK    0x00000004UL
+#define XLPD_XPPU_IMR_MID_RO_DEFVAL  0x1UL
+
+#define XLPD_XPPU_IMR_MID_MISS_SHIFT   1UL
+#define XLPD_XPPU_IMR_MID_MISS_WIDTH   1UL
+#define XLPD_XPPU_IMR_MID_MISS_MASK    0x00000002UL
+#define XLPD_XPPU_IMR_MID_MISS_DEFVAL  0x1UL
+
+#define XLPD_XPPU_IMR_INV_APB_SHIFT   0UL
+#define XLPD_XPPU_IMR_INV_APB_WIDTH   1UL
+#define XLPD_XPPU_IMR_INV_APB_MASK    0x00000001UL
+#define XLPD_XPPU_IMR_INV_APB_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdXppuIen
+ */
+#define XLPD_XPPU_IEN    ( ( XLPD_XPPU_BASEADDR ) + 0x00000018UL )
+#define XLPD_XPPU_IEN_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_IEN_APER_PARITY_SHIFT   7UL
+#define XLPD_XPPU_IEN_APER_PARITY_WIDTH   1UL
+#define XLPD_XPPU_IEN_APER_PARITY_MASK    0x00000080UL
+#define XLPD_XPPU_IEN_APER_PARITY_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IEN_APER_TZ_SHIFT   6UL
+#define XLPD_XPPU_IEN_APER_TZ_WIDTH   1UL
+#define XLPD_XPPU_IEN_APER_TZ_MASK    0x00000040UL
+#define XLPD_XPPU_IEN_APER_TZ_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IEN_APER_PERM_SHIFT   5UL
+#define XLPD_XPPU_IEN_APER_PERM_WIDTH   1UL
+#define XLPD_XPPU_IEN_APER_PERM_MASK    0x00000020UL
+#define XLPD_XPPU_IEN_APER_PERM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IEN_MID_PARITY_SHIFT   3UL
+#define XLPD_XPPU_IEN_MID_PARITY_WIDTH   1UL
+#define XLPD_XPPU_IEN_MID_PARITY_MASK    0x00000008UL
+#define XLPD_XPPU_IEN_MID_PARITY_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IEN_MID_RO_SHIFT   2UL
+#define XLPD_XPPU_IEN_MID_RO_WIDTH   1UL
+#define XLPD_XPPU_IEN_MID_RO_MASK    0x00000004UL
+#define XLPD_XPPU_IEN_MID_RO_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IEN_MID_MISS_SHIFT   1UL
+#define XLPD_XPPU_IEN_MID_MISS_WIDTH   1UL
+#define XLPD_XPPU_IEN_MID_MISS_MASK    0x00000002UL
+#define XLPD_XPPU_IEN_MID_MISS_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IEN_INV_APB_SHIFT   0UL
+#define XLPD_XPPU_IEN_INV_APB_WIDTH   1UL
+#define XLPD_XPPU_IEN_INV_APB_MASK    0x00000001UL
+#define XLPD_XPPU_IEN_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuIds
+ */
+#define XLPD_XPPU_IDS    ( ( XLPD_XPPU_BASEADDR ) + 0x0000001CUL )
+#define XLPD_XPPU_IDS_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_IDS_APER_PARITY_SHIFT   7UL
+#define XLPD_XPPU_IDS_APER_PARITY_WIDTH   1UL
+#define XLPD_XPPU_IDS_APER_PARITY_MASK    0x00000080UL
+#define XLPD_XPPU_IDS_APER_PARITY_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IDS_APER_TZ_SHIFT   6UL
+#define XLPD_XPPU_IDS_APER_TZ_WIDTH   1UL
+#define XLPD_XPPU_IDS_APER_TZ_MASK    0x00000040UL
+#define XLPD_XPPU_IDS_APER_TZ_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IDS_APER_PERM_SHIFT   5UL
+#define XLPD_XPPU_IDS_APER_PERM_WIDTH   1UL
+#define XLPD_XPPU_IDS_APER_PERM_MASK    0x00000020UL
+#define XLPD_XPPU_IDS_APER_PERM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IDS_MID_PARITY_SHIFT   3UL
+#define XLPD_XPPU_IDS_MID_PARITY_WIDTH   1UL
+#define XLPD_XPPU_IDS_MID_PARITY_MASK    0x00000008UL
+#define XLPD_XPPU_IDS_MID_PARITY_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IDS_MID_RO_SHIFT   2UL
+#define XLPD_XPPU_IDS_MID_RO_WIDTH   1UL
+#define XLPD_XPPU_IDS_MID_RO_MASK    0x00000004UL
+#define XLPD_XPPU_IDS_MID_RO_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IDS_MID_MISS_SHIFT   1UL
+#define XLPD_XPPU_IDS_MID_MISS_WIDTH   1UL
+#define XLPD_XPPU_IDS_MID_MISS_MASK    0x00000002UL
+#define XLPD_XPPU_IDS_MID_MISS_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IDS_INV_APB_SHIFT   0UL
+#define XLPD_XPPU_IDS_INV_APB_WIDTH   1UL
+#define XLPD_XPPU_IDS_INV_APB_MASK    0x00000001UL
+#define XLPD_XPPU_IDS_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMMstrIds
+ */
+#define XLPD_XPPU_M_MSTR_IDS    ( ( XLPD_XPPU_BASEADDR ) + 0x0000003CUL )
+#define XLPD_XPPU_M_MSTR_IDS_RSTVAL   0x00000014UL
+
+#define XLPD_XPPU_M_MSTR_IDS_NO_SHIFT   0UL
+#define XLPD_XPPU_M_MSTR_IDS_NO_WIDTH   32UL
+#define XLPD_XPPU_M_MSTR_IDS_NO_MASK    0xffffffffUL
+#define XLPD_XPPU_M_MSTR_IDS_NO_DEFVAL  0x14UL
+
+/**
+ * Register: XlpdXppuMAperture32b
+ */
+#define XLPD_XPPU_M_APERTURE_32B    ( ( XLPD_XPPU_BASEADDR ) + 0x00000040UL )
+#define XLPD_XPPU_M_APERTURE_32B_RSTVAL   0x00000080UL
+
+#define XLPD_XPPU_M_APERTURE_32B_NO_SHIFT   0UL
+#define XLPD_XPPU_M_APERTURE_32B_NO_WIDTH   32UL
+#define XLPD_XPPU_M_APERTURE_32B_NO_MASK    0xffffffffUL
+#define XLPD_XPPU_M_APERTURE_32B_NO_DEFVAL  0x80UL
+
+/**
+ * Register: XlpdXppuMAperture64kb
+ */
+#define XLPD_XPPU_M_APERTURE_64KB    ( ( XLPD_XPPU_BASEADDR ) + 0x00000044UL )
+#define XLPD_XPPU_M_APERTURE_64KB_RSTVAL   0x00000100UL
+
+#define XLPD_XPPU_M_APERTURE_64KB_NO_SHIFT   0UL
+#define XLPD_XPPU_M_APERTURE_64KB_NO_WIDTH   32UL
+#define XLPD_XPPU_M_APERTURE_64KB_NO_MASK    0xffffffffUL
+#define XLPD_XPPU_M_APERTURE_64KB_NO_DEFVAL  0x100UL
+
+/**
+ * Register: XlpdXppuMAperture1mb
+ */
+#define XLPD_XPPU_M_APERTURE_1MB    ( ( XLPD_XPPU_BASEADDR ) + 0x00000048UL )
+#define XLPD_XPPU_M_APERTURE_1MB_RSTVAL   0x00000010UL
+
+#define XLPD_XPPU_M_APERTURE_1MB_NO_SHIFT   0UL
+#define XLPD_XPPU_M_APERTURE_1MB_NO_WIDTH   32UL
+#define XLPD_XPPU_M_APERTURE_1MB_NO_MASK    0xffffffffUL
+#define XLPD_XPPU_M_APERTURE_1MB_NO_DEFVAL  0x10UL
+
+/**
+ * Register: XlpdXppuMAperture512mb
+ */
+#define XLPD_XPPU_M_APERTURE_512MB    ( ( XLPD_XPPU_BASEADDR ) + 0x0000004CUL )
+#define XLPD_XPPU_M_APERTURE_512MB_RSTVAL   0x00000001UL
+
+#define XLPD_XPPU_M_APERTURE_512MB_NO_SHIFT   0UL
+#define XLPD_XPPU_M_APERTURE_512MB_NO_WIDTH   32UL
+#define XLPD_XPPU_M_APERTURE_512MB_NO_MASK    0xffffffffUL
+#define XLPD_XPPU_M_APERTURE_512MB_NO_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdXppuBase32b
+ */
+#define XLPD_XPPU_BASE_32B    ( ( XLPD_XPPU_BASEADDR ) + 0x00000050UL )
+#define XLPD_XPPU_BASE_32B_RSTVAL   0xff990000UL
+
+#define XLPD_XPPU_BASE_32B_ADDR_SHIFT   0UL
+#define XLPD_XPPU_BASE_32B_ADDR_WIDTH   32UL
+#define XLPD_XPPU_BASE_32B_ADDR_MASK    0xffffffffUL
+#define XLPD_XPPU_BASE_32B_ADDR_DEFVAL  0xff990000UL
+
+/**
+ * Register: XlpdXppuBase64kb
+ */
+#define XLPD_XPPU_BASE_64KB    ( ( XLPD_XPPU_BASEADDR ) + 0x00000054UL )
+#define XLPD_XPPU_BASE_64KB_RSTVAL   0xff000000UL
+
+#define XLPD_XPPU_BASE_64KB_ADDR_SHIFT   0UL
+#define XLPD_XPPU_BASE_64KB_ADDR_WIDTH   32UL
+#define XLPD_XPPU_BASE_64KB_ADDR_MASK    0xffffffffUL
+#define XLPD_XPPU_BASE_64KB_ADDR_DEFVAL  0xff000000UL
+
+/**
+ * Register: XlpdXppuBase1mb
+ */
+#define XLPD_XPPU_BASE_1MB    ( ( XLPD_XPPU_BASEADDR ) + 0x00000058UL )
+#define XLPD_XPPU_BASE_1MB_RSTVAL   0xfe000000UL
+
+#define XLPD_XPPU_BASE_1MB_ADDR_SHIFT   0UL
+#define XLPD_XPPU_BASE_1MB_ADDR_WIDTH   32UL
+#define XLPD_XPPU_BASE_1MB_ADDR_MASK    0xffffffffUL
+#define XLPD_XPPU_BASE_1MB_ADDR_DEFVAL  0xfe000000UL
+
+/**
+ * Register: XlpdXppuBase512mb
+ */
+#define XLPD_XPPU_BASE_512MB    ( ( XLPD_XPPU_BASEADDR ) + 0x0000005CUL )
+#define XLPD_XPPU_BASE_512MB_RSTVAL   0xc0000000UL
+
+#define XLPD_XPPU_BASE_512MB_ADDR_SHIFT   0UL
+#define XLPD_XPPU_BASE_512MB_ADDR_WIDTH   32UL
+#define XLPD_XPPU_BASE_512MB_ADDR_MASK    0xffffffffUL
+#define XLPD_XPPU_BASE_512MB_ADDR_DEFVAL  0xc0000000UL
+
+/**
+ * Register: XlpdXppuMstrId00
+ */
+#define XLPD_XPPU_MSTR_ID00    ( ( XLPD_XPPU_BASEADDR ) + 0x00000100UL )
+#define XLPD_XPPU_MSTR_ID00_RSTVAL   0x83ff0040UL
+
+#define XLPD_XPPU_MSTR_ID00_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID00_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID00_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID00_MIDP_DEFVAL  0x1UL
+
+#define XLPD_XPPU_MSTR_ID00_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID00_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID00_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID00_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID00_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID00_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID00_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID00_MIDM_DEFVAL  0x3ffUL
+
+#define XLPD_XPPU_MSTR_ID00_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID00_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID00_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID00_MID_DEFVAL  0x40UL
+
+/**
+ * Register: XlpdXppuMstrId01
+ */
+#define XLPD_XPPU_MSTR_ID01    ( ( XLPD_XPPU_BASEADDR ) + 0x00000104UL )
+#define XLPD_XPPU_MSTR_ID01_RSTVAL   0x03f00000UL
+
+#define XLPD_XPPU_MSTR_ID01_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID01_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID01_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID01_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID01_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID01_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID01_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID01_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID01_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID01_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID01_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID01_MIDM_DEFVAL  0x3f0UL
+
+#define XLPD_XPPU_MSTR_ID01_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID01_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID01_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID01_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId02
+ */
+#define XLPD_XPPU_MSTR_ID02    ( ( XLPD_XPPU_BASEADDR ) + 0x00000108UL )
+#define XLPD_XPPU_MSTR_ID02_RSTVAL   0x83f00010UL
+
+#define XLPD_XPPU_MSTR_ID02_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID02_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID02_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID02_MIDP_DEFVAL  0x1UL
+
+#define XLPD_XPPU_MSTR_ID02_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID02_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID02_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID02_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID02_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID02_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID02_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID02_MIDM_DEFVAL  0x3f0UL
+
+#define XLPD_XPPU_MSTR_ID02_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID02_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID02_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID02_MID_DEFVAL  0x10UL
+
+/**
+ * Register: XlpdXppuMstrId03
+ */
+#define XLPD_XPPU_MSTR_ID03    ( ( XLPD_XPPU_BASEADDR ) + 0x0000010CUL )
+#define XLPD_XPPU_MSTR_ID03_RSTVAL   0x83c00080UL
+
+#define XLPD_XPPU_MSTR_ID03_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID03_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID03_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID03_MIDP_DEFVAL  0x1UL
+
+#define XLPD_XPPU_MSTR_ID03_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID03_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID03_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID03_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID03_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID03_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID03_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID03_MIDM_DEFVAL  0x3c0UL
+
+#define XLPD_XPPU_MSTR_ID03_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID03_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID03_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID03_MID_DEFVAL  0x80UL
+
+/**
+ * Register: XlpdXppuMstrId04
+ */
+#define XLPD_XPPU_MSTR_ID04    ( ( XLPD_XPPU_BASEADDR ) + 0x00000110UL )
+#define XLPD_XPPU_MSTR_ID04_RSTVAL   0x83c30080UL
+
+#define XLPD_XPPU_MSTR_ID04_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID04_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID04_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID04_MIDP_DEFVAL  0x1UL
+
+#define XLPD_XPPU_MSTR_ID04_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID04_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID04_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID04_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID04_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID04_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID04_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID04_MIDM_DEFVAL  0x3c3UL
+
+#define XLPD_XPPU_MSTR_ID04_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID04_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID04_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID04_MID_DEFVAL  0x80UL
+
+/**
+ * Register: XlpdXppuMstrId05
+ */
+#define XLPD_XPPU_MSTR_ID05    ( ( XLPD_XPPU_BASEADDR ) + 0x00000114UL )
+#define XLPD_XPPU_MSTR_ID05_RSTVAL   0x03c30081UL
+
+#define XLPD_XPPU_MSTR_ID05_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID05_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID05_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID05_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID05_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID05_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID05_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID05_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID05_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID05_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID05_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID05_MIDM_DEFVAL  0x3c3UL
+
+#define XLPD_XPPU_MSTR_ID05_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID05_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID05_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID05_MID_DEFVAL  0x81UL
+
+/**
+ * Register: XlpdXppuMstrId06
+ */
+#define XLPD_XPPU_MSTR_ID06    ( ( XLPD_XPPU_BASEADDR ) + 0x00000118UL )
+#define XLPD_XPPU_MSTR_ID06_RSTVAL   0x03c30082UL
+
+#define XLPD_XPPU_MSTR_ID06_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID06_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID06_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID06_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID06_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID06_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID06_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID06_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID06_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID06_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID06_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID06_MIDM_DEFVAL  0x3c3UL
+
+#define XLPD_XPPU_MSTR_ID06_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID06_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID06_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID06_MID_DEFVAL  0x82UL
+
+/**
+ * Register: XlpdXppuMstrId07
+ */
+#define XLPD_XPPU_MSTR_ID07    ( ( XLPD_XPPU_BASEADDR ) + 0x0000011CUL )
+#define XLPD_XPPU_MSTR_ID07_RSTVAL   0x83c30083UL
+
+#define XLPD_XPPU_MSTR_ID07_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID07_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID07_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID07_MIDP_DEFVAL  0x1UL
+
+#define XLPD_XPPU_MSTR_ID07_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID07_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID07_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID07_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID07_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID07_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID07_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID07_MIDM_DEFVAL  0x3c3UL
+
+#define XLPD_XPPU_MSTR_ID07_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID07_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID07_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID07_MID_DEFVAL  0x83UL
+
+/**
+ * Register: XlpdXppuMstrId08
+ */
+#define XLPD_XPPU_MSTR_ID08    ( ( XLPD_XPPU_BASEADDR ) + 0x00000120UL )
+#define XLPD_XPPU_MSTR_ID08_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID08_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID08_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID08_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID08_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID08_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID08_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID08_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID08_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID08_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID08_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID08_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID08_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID08_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID08_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID08_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID08_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId09
+ */
+#define XLPD_XPPU_MSTR_ID09    ( ( XLPD_XPPU_BASEADDR ) + 0x00000124UL )
+#define XLPD_XPPU_MSTR_ID09_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID09_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID09_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID09_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID09_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID09_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID09_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID09_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID09_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID09_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID09_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID09_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID09_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID09_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID09_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID09_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID09_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId10
+ */
+#define XLPD_XPPU_MSTR_ID10    ( ( XLPD_XPPU_BASEADDR ) + 0x00000128UL )
+#define XLPD_XPPU_MSTR_ID10_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID10_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID10_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID10_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID10_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID10_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID10_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID10_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID10_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID10_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID10_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID10_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID10_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID10_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID10_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID10_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID10_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId11
+ */
+#define XLPD_XPPU_MSTR_ID11    ( ( XLPD_XPPU_BASEADDR ) + 0x0000012CUL )
+#define XLPD_XPPU_MSTR_ID11_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID11_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID11_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID11_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID11_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID11_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID11_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID11_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID11_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID11_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID11_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID11_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID11_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID11_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID11_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID11_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID11_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId12
+ */
+#define XLPD_XPPU_MSTR_ID12    ( ( XLPD_XPPU_BASEADDR ) + 0x00000130UL )
+#define XLPD_XPPU_MSTR_ID12_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID12_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID12_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID12_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID12_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID12_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID12_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID12_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID12_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID12_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID12_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID12_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID12_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID12_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID12_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID12_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID12_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId13
+ */
+#define XLPD_XPPU_MSTR_ID13    ( ( XLPD_XPPU_BASEADDR ) + 0x00000134UL )
+#define XLPD_XPPU_MSTR_ID13_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID13_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID13_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID13_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID13_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID13_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID13_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID13_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID13_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID13_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID13_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID13_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID13_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID13_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID13_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID13_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID13_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId14
+ */
+#define XLPD_XPPU_MSTR_ID14    ( ( XLPD_XPPU_BASEADDR ) + 0x00000138UL )
+#define XLPD_XPPU_MSTR_ID14_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID14_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID14_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID14_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID14_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID14_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID14_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID14_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID14_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID14_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID14_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID14_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID14_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID14_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID14_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID14_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID14_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId15
+ */
+#define XLPD_XPPU_MSTR_ID15    ( ( XLPD_XPPU_BASEADDR ) + 0x0000013CUL )
+#define XLPD_XPPU_MSTR_ID15_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID15_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID15_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID15_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID15_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID15_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID15_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID15_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID15_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID15_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID15_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID15_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID15_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID15_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID15_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID15_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID15_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId16
+ */
+#define XLPD_XPPU_MSTR_ID16    ( ( XLPD_XPPU_BASEADDR ) + 0x00000140UL )
+#define XLPD_XPPU_MSTR_ID16_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID16_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID16_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID16_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID16_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID16_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID16_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID16_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID16_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID16_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID16_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID16_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID16_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID16_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID16_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID16_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID16_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId17
+ */
+#define XLPD_XPPU_MSTR_ID17    ( ( XLPD_XPPU_BASEADDR ) + 0x00000144UL )
+#define XLPD_XPPU_MSTR_ID17_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID17_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID17_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID17_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID17_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID17_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID17_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID17_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID17_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID17_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID17_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID17_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID17_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID17_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID17_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID17_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID17_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId18
+ */
+#define XLPD_XPPU_MSTR_ID18    ( ( XLPD_XPPU_BASEADDR ) + 0x00000148UL )
+#define XLPD_XPPU_MSTR_ID18_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID18_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID18_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID18_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID18_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID18_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID18_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID18_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID18_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID18_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID18_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID18_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID18_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID18_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID18_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID18_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID18_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId19
+ */
+#define XLPD_XPPU_MSTR_ID19    ( ( XLPD_XPPU_BASEADDR ) + 0x0000014CUL )
+#define XLPD_XPPU_MSTR_ID19_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID19_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID19_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID19_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID19_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID19_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID19_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID19_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID19_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID19_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID19_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID19_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID19_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID19_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID19_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID19_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID19_MID_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XLPD_XPPU_H__ */

lib/bsp/standalone/src/cortexa53/xlpd_xppu_sink.h

@@ -0,0 +1,81 @@
+/* ### HEADER ### */
+
+#ifndef __XLPD_XPPU_SINK_H__
+#define __XLPD_XPPU_SINK_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XlpdXppuSink Base Address
+ */
+#define XLPD_XPPU_SINK_BASEADDR      0xFF9C0000UL
+
+/**
+ * Register: XlpdXppuSinkErrSts
+ */
+#define XLPD_XPPU_SINK_ERR_STS    ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF00UL )
+#define XLPD_XPPU_SINK_ERR_STS_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_SINK_ERR_STS_RDWR_SHIFT   31UL
+#define XLPD_XPPU_SINK_ERR_STS_RDWR_WIDTH   1UL
+#define XLPD_XPPU_SINK_ERR_STS_RDWR_MASK    0x80000000UL
+#define XLPD_XPPU_SINK_ERR_STS_RDWR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_SINK_ERR_STS_ADDR_SHIFT   0UL
+#define XLPD_XPPU_SINK_ERR_STS_ADDR_WIDTH   12UL
+#define XLPD_XPPU_SINK_ERR_STS_ADDR_MASK    0x00000fffUL
+#define XLPD_XPPU_SINK_ERR_STS_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuSinkIsr
+ */
+#define XLPD_XPPU_SINK_ISR    ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF10UL )
+#define XLPD_XPPU_SINK_ISR_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_SINK_ISRADDRDECDERR_SHIFT   0UL
+#define XLPD_XPPU_SINK_ISRADDRDECDERR_WIDTH   1UL
+#define XLPD_XPPU_SINK_ISRADDRDECDERR_MASK    0x00000001UL
+#define XLPD_XPPU_SINK_ISRADDRDECDERR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuSinkImr
+ */
+#define XLPD_XPPU_SINK_IMR    ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF14UL )
+#define XLPD_XPPU_SINK_IMR_RSTVAL   0x00000001UL
+
+#define XLPD_XPPU_SINK_IMRADDRDECDERR_SHIFT   0UL
+#define XLPD_XPPU_SINK_IMRADDRDECDERR_WIDTH   1UL
+#define XLPD_XPPU_SINK_IMRADDRDECDERR_MASK    0x00000001UL
+#define XLPD_XPPU_SINK_IMRADDRDECDERR_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdXppuSinkIer
+ */
+#define XLPD_XPPU_SINK_IER    ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF18UL )
+#define XLPD_XPPU_SINK_IER_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_SINK_IERADDRDECDERR_SHIFT   0UL
+#define XLPD_XPPU_SINK_IERADDRDECDERR_WIDTH   1UL
+#define XLPD_XPPU_SINK_IERADDRDECDERR_MASK    0x00000001UL
+#define XLPD_XPPU_SINK_IERADDRDECDERR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuSinkIdr
+ */
+#define XLPD_XPPU_SINK_IDR    ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF1CUL )
+#define XLPD_XPPU_SINK_IDR_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_SINK_IDRADDRDECDERR_SHIFT   0UL
+#define XLPD_XPPU_SINK_IDRADDRDECDERR_WIDTH   1UL
+#define XLPD_XPPU_SINK_IDRADDRDECDERR_MASK    0x00000001UL
+#define XLPD_XPPU_SINK_IDRADDRDECDERR_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XLPD_XPPU_SINK_H__ */

lib/bsp/standalone/src/cortexa53/xparameters_ps.h

@@ -116,7 +116,28 @@ extern "C" {
 #define XPAR_XDMAPS_0_DONE_INTR_5	XPS_DMA5_INT_ID
 #define XPAR_XDMAPS_0_DONE_INTR_6	XPS_DMA6_INT_ID
 #define XPAR_XDMAPS_0_DONE_INTR_7	XPS_DMA7_INT_ID
-#define XPAR_XNANDPS8_0_INTR        XPS_NAND_INT_ID
+#define XPAR_XNANDPS8_0_INTR        	XPS_NAND_INT_ID
+#define XPAR_XADMAPS_0_INTR 		XPS_ADMA_CH0_INT_ID
+#define XPAR_XADMAPS_1_INTR 		XPS_ADMA_CH1_INT_ID
+#define XPAR_XADMAPS_2_INTR		XPS_ADMA_CH2_INT_ID
+#define XPAR_XADMAPS_3_INTR 		XPS_ADMA_CH3_INT_ID
+#define XPAR_XADMAPS_4_INTR		XPS_ADMA_CH4_INT_ID
+#define XPAR_XADMAPS_5_INTR 		XPS_ADMA_CH5_INT_ID
+#define XPAR_XADMAPS_6_INTR 		XPS_ADMA_CH6_INT_ID
+#define XPAR_XADMAPS_7_INTR 		XPS_ADMA_CH7_INT_ID
+#define XPAR_XCSUDMA_INTR 		XPS_CSU_DMA_INT_ID
+#define XPAR_XMPU_LPD_INTR 		XPS_XMPU_LPD_INT_ID
+#define XPAR_XZDMAPS_0_INTR		XPS_ZDMA_CH0_INT_ID
+#define XPAR_XZDMAPS_1_INTR		XPS_ZDMA_CH1_INT_ID
+#define XPAR_XZDMAPS_2_INTR 		XPS_ZDMA_CH2_INT_ID
+#define XPAR_XZDMAPS_3_INTR 		XPS_ZDMA_CH3_INT_ID
+#define XPAR_XZDMAPS_4_INTR		XPS_ZDMA_CH4_INT_ID
+#define XPAR_XZDMAPS_5_INTR 		XPS_ZDMA_CH5_INT_ID
+#define XPAR_XZDMAPS_6_INTR 		XPS_ZDMA_CH6_INT_ID
+#define XPAR_XZDMAPS_7_INTR 		XPS_ZDMA_CH7_INT_ID
+#define XPAR_XMPU_FPD_INTR 		XPS_XMPU_FPD_INT_ID
+#define XPAR_XCCI_FPD_INTR 		XPS_FPD_CCI_INT_ID
+#define XPAR_XSMMU_FPD_INTR 		XPS_FPD_SMMU_INT_ID
 
 /* Canonical definitions for SCU GIC */
 #define XPAR_SCUGIC_NUM_INSTANCES	1U
@@ -141,11 +162,10 @@ extern "C" {
 
 /* Shared Peripheral Interrupts (SPI) */
 
+/* FIXME */
+/*#define XPS_FPGA0_INT_ID		100U */
 #define XPS_USB1_INT_ID			76U
 #define XPS_USB0_INT_ID			53U
-
-#define XPS_NAND_INT_ID        (32U + 32U)
-
 #define XPS_FPGA1_INT_ID		62U
 #define XPS_FPGA2_INT_ID		63U
 #define XPS_FPGA3_INT_ID		64U
@@ -166,46 +186,64 @@ extern "C" {
 #define XPS_FPGA14_INT_ID		90U
 #define XPS_FPGA15_INT_ID		91U
 
-
-#define XPS_OCMINTR_INT_ID		(28U + 32U)
-#define XPS_QSPI_INT_ID			(33U + 32U)
-#define XPS_GPIO_INT_ID			(34U + 32U)
-#define XPS_WDT_INT_ID			(106U + 32U)
-#define XPS_LP_WDT_INT_ID			(69U + 32U)
-#define XPS_TTC0_0_INT_ID		(53U + 32U)
-#define XPS_TTC0_1_INT_ID		(54U + 32U)
-#define XPS_TTC0_2_INT_ID 		(55U + 32U)
-#define XPS_SDIO0_INT_ID		(65U + 32U)
-#define XPS_I2C0_INT_ID			(35U + 32U)
-#define XPS_SPI0_INT_ID			(37U + 32U)
-#define XPS_UART0_INT_ID		(39U + 32U)
-#define XPS_CAN0_INT_ID			(41U + 32U)
-
-/* FIXME */
-/*#define XPS_FPGA0_INT_ID		100U */
-
-#define XPS_TTC1_0_INT_ID		(56U + 32U)
-#define XPS_TTC1_1_INT_ID		(57U + 32U)
-#define XPS_TTC1_2_INT_ID		(58U + 32U)
-#define XPS_TTC2_0_INT_ID		(59U + 32U)
-#define XPS_TTC2_1_INT_ID		(60U + 32U)
-#define XPS_TTC2_2_INT_ID		(61U + 32U)
-#define XPS_TTC3_0_INT_ID		(62U + 32U)
-#define XPS_TTC3_1_INT_ID		(63U + 32U)
-#define XPS_TTC3_2_INT_ID		(64U + 32U)
-#define XPS_SDIO1_INT_ID		(66U + 32U)
-#define XPS_I2C1_INT_ID			(36U + 32U)
-#define XPS_SPI1_INT_ID			(38U + 32U)
-#define XPS_UART1_INT_ID		(40U + 32U)
-#define XPS_CAN1_INT_ID			(42U + 32U)
-#define XPS_GEM0_INT_ID			(73U + 32U)
-#define XPS_GEM0_WAKE_INT_ID		(74U + 32U)
-#define XPS_GEM1_INT_ID			(75U + 32U)
-#define XPS_GEM1_WAKE_INT_ID		(76U + 32U)
-#define XPS_GEM2_INT_ID			(77U + 32U)
-#define XPS_GEM2_WAKE_INT_ID		(78U + 32U)
-#define XPS_GEM3_INT_ID			(79U + 32U)
-#define XPS_GEM3_WAKE_INT_ID		(80U + 32U)
+/* Updated Interrupt-IDs */
+#define XPS_OCMINTR_INT_ID		(10U + 32U)
+#define XPS_NAND_INT_ID        (14U + 32U)
+#define XPS_QSPI_INT_ID			(15U + 32U)
+#define XPS_GPIO_INT_ID			(16U + 32U)
+#define XPS_I2C0_INT_ID			(17U + 32U)
+#define XPS_I2C1_INT_ID			(18U + 32U)
+#define XPS_SPI0_INT_ID			(19U + 32U)
+#define XPS_SPI1_INT_ID			(20U + 32U)
+#define XPS_UART0_INT_ID		(21U + 32U)
+#define XPS_UART1_INT_ID		(22U + 32U)
+#define XPS_CAN0_INT_ID			(23U + 32U)
+#define XPS_CAN1_INT_ID			(24U + 32U)
+#define XPS_WDT_INT_ID			(113U + 32U)
+#define XPS_LP_WDT_INT_ID			(52U + 32U)
+#define XPS_TTC0_0_INT_ID		(36U + 32U)
+#define XPS_TTC0_1_INT_ID		(37U + 32U)
+#define XPS_TTC0_2_INT_ID 		(38U + 32U)
+#define XPS_TTC1_0_INT_ID		(39U + 32U)
+#define XPS_TTC1_1_INT_ID		(40U + 32U)
+#define XPS_TTC1_2_INT_ID		(41U + 32U)
+#define XPS_TTC2_0_INT_ID		(42U + 32U)
+#define XPS_TTC2_1_INT_ID		(43U + 32U)
+#define XPS_TTC2_2_INT_ID		(44U + 32U)
+#define XPS_TTC3_0_INT_ID		(45U + 32U)
+#define XPS_TTC3_1_INT_ID		(46U + 32U)
+#define XPS_TTC3_2_INT_ID		(47U + 32U)
+#define XPS_SDIO0_INT_ID		(48U + 32U)
+#define XPS_SDIO1_INT_ID		(49U + 32U)
+#define XPS_GEM0_INT_ID			(57U + 32U)
+#define XPS_GEM0_WAKE_INT_ID		(58U + 32U)
+#define XPS_GEM1_INT_ID			(59U + 32U)
+#define XPS_GEM1_WAKE_INT_ID		(60U + 32U)
+#define XPS_GEM2_INT_ID			(61U + 32U)
+#define XPS_GEM2_WAKE_INT_ID		(62U + 32U)
+#define XPS_GEM3_INT_ID			(63U + 32U)
+#define XPS_GEM3_WAKE_INT_ID		(64U + 32U)
+#define XPS_ADMA_CH0_INT_ID		(77U + 32U)
+#define XPS_ADMA_CH1_INT_ID		(78U + 32U)
+#define XPS_ADMA_CH2_INT_ID		(79U + 32U)
+#define XPS_ADMA_CH3_INT_ID		(80U + 32U)
+#define XPS_ADMA_CH4_INT_ID		(81U + 32U)
+#define XPS_ADMA_CH5_INT_ID		(82U + 32U)
+#define XPS_ADMA_CH6_INT_ID		(83U + 32U)
+#define XPS_ADMA_CH7_INT_ID		(84U + 32U)
+#define XPS_CSU_DMA_INT_ID		(86U + 32U)
+#define XPS_XMPU_LPD_INT_ID		(88U + 32U)
+#define XPS_ZDMA_CH0_INT_ID		(124U + 32U)
+#define XPS_ZDMA_CH1_INT_ID		(125U + 32U)
+#define XPS_ZDMA_CH2_INT_ID		(126U + 32U)
+#define XPS_ZDMA_CH3_INT_ID		(127U + 32U)
+#define XPS_ZDMA_CH4_INT_ID		(128U + 32U)
+#define XPS_ZDMA_CH5_INT_ID		(129U + 32U)
+#define XPS_ZDMA_CH6_INT_ID		(130U + 32U)
+#define XPS_ZDMA_CH7_INT_ID		(131U + 32U)
+#define XPS_XMPU_FPD_INT_ID		(134U + 32U)
+#define XPS_FPD_CCI_INT_ID		(154U + 32U)
+#define XPS_FPD_SMMU_INT_ID		(155U + 32U)
 
 /* Private Peripheral Interrupts (PPI) */
 /*#define XPS_GLOBAL_TMR_INT_ID		27U	 SCU Global Timer interrupt */

lib/bsp/standalone/src/cortexa53/xpseudo_asm.h

@@ -48,10 +48,6 @@
 #ifndef XPSEUDO_ASM_H
 #define XPSEUDO_ASM_H
 #include "xreg_cortexa53.h"
-#ifdef __GNUC__
- #include "xpseudo_asm_gcc.h"
-#else
- #include "xpseudo_asm_rvct.h"
-#endif
+#include "xpseudo_asm_gcc.h"
 
 #endif /* XPSEUDO_ASM_H */

lib/bsp/standalone/src/cortexa53/xreg_cortexa53.h

@@ -58,90 +58,57 @@ extern "C" {
 
 
 /* GPRs */
-#define XREG_GPR0				r0
-#define XREG_GPR1				r1
-#define XREG_GPR2				r2
-#define XREG_GPR3				r3
-#define XREG_GPR4				r4
-#define XREG_GPR5				r5
-#define XREG_GPR6				r6
-#define XREG_GPR7				r7
-#define XREG_GPR8				r8
-#define XREG_GPR9				r9
-#define XREG_GPR10				r10
-#define XREG_GPR11				r11
-#define XREG_GPR12				r12
-#define XREG_GPR13				r13
-#define XREG_GPR14				r14
-#define XREG_GPR15				r15
+#define XREG_GPR0				x0
+#define XREG_GPR1				x1
+#define XREG_GPR2				x2
+#define XREG_GPR3				x3
+#define XREG_GPR4				x4
+#define XREG_GPR5				x5
+#define XREG_GPR6				x6
+#define XREG_GPR7				x7
+#define XREG_GPR8				x8
+#define XREG_GPR9				x9
+#define XREG_GPR10				x10
+#define XREG_GPR11				x11
+#define XREG_GPR12				x12
+#define XREG_GPR13				x13
+#define XREG_GPR14				x14
+#define XREG_GPR15				x15
+#define XREG_GPR16				x16
+#define XREG_GPR17				x17
+#define XREG_GPR18				x18
+#define XREG_GPR19				x19
+#define XREG_GPR20				x20
+#define XREG_GPR21				x21
+#define XREG_GPR22				x22
+#define XREG_GPR23				x23
+#define XREG_GPR24				x24
+#define XREG_GPR25				x25
+#define XREG_GPR26				x26
+#define XREG_GPR27				x27
+#define XREG_GPR28				x28
+#define XREG_GPR29				x29
+#define XREG_GPR30				x30
 #define XREG_CPSR				cpsr
 
-/* Coprocessor number defines */
-#define XREG_CP0				0
-#define XREG_CP1				1
-#define XREG_CP2				2
-#define XREG_CP3				3
-#define XREG_CP4				4
-#define XREG_CP5				5
-#define XREG_CP6				6
-#define XREG_CP7				7
-#define XREG_CP8				8
-#define XREG_CP9				9
-#define XREG_CP10				10
-#define XREG_CP11				11
-#define XREG_CP12				12
-#define XREG_CP13				13
-#define XREG_CP14				14
-#define XREG_CP15				15
-
-/* Coprocessor control register defines */
-#define XREG_CR0				cr0
-#define XREG_CR1				cr1
-#define XREG_CR2				cr2
-#define XREG_CR3				cr3
-#define XREG_CR4				cr4
-#define XREG_CR5				cr5
-#define XREG_CR6				cr6
-#define XREG_CR7				cr7
-#define XREG_CR8				cr8
-#define XREG_CR9				cr9
-#define XREG_CR10				cr10
-#define XREG_CR11				cr11
-#define XREG_CR12				cr12
-#define XREG_CR13				cr13
-#define XREG_CR14				cr14
-#define XREG_CR15				cr15
-
 /* Current Processor Status Register (CPSR) Bits */
-#define XREG_CPSR_THUMB_MODE			0x20
 #define XREG_CPSR_MODE_BITS			0x1F
-#define XREG_CPSR_SYSTEM_MODE			0x1F
-#define XREG_CPSR_UNDEFINED_MODE		0x1B
-#define XREG_CPSR_DATA_ABORT_MODE		0x17
-#define XREG_CPSR_SVC_MODE			0x13
-#define XREG_CPSR_IRQ_MODE			0x12
-#define XREG_CPSR_FIQ_MODE			0x11
-#define XREG_CPSR_USER_MODE			0x10
+#define XREG_CPSR_EL3h_MODE			0xD
+#define XREG_CPSR_EL3t_MODE			0xC
+#define XREG_CPSR_EL2h_MODE			0x9
+#define XREG_CPSR_EL2t_MODE			0x8
+#define XREG_CPSR_EL1h_MODE			0x5
+#define XREG_CPSR_EL1t_MODE			0x4
+#define XREG_CPSR_EL0t_MODE			0x0
 
-#define XREG_CPSR_IRQ_ENABLE			0x80
-#define XREG_CPSR_FIQ_ENABLE			0x40
+#define XREG_CPSR_IRQ_ENABLE		0x80
+#define XREG_CPSR_FIQ_ENABLE		0x40
 
 #define XREG_CPSR_N_BIT				0x80000000U
 #define XREG_CPSR_Z_BIT				0x40000000U
 #define XREG_CPSR_C_BIT				0x20000000U
 #define XREG_CPSR_V_BIT				0x10000000U
 
-
-
-/* MPE register definitions */
-#define XREG_FPSID				c0
-#define XREG_FPSCR				c1
-#define XREG_MVFR1				c6
-#define XREG_MVFR0				c7
-#define XREG_FPEXC				c8
-#define XREG_FPINST				c9
-#define XREG_FPINST2				c10
-
 /* FPSID bits */
 #define XREG_FPSID_IMPLEMENTER_BIT	(24U)
 #define XREG_FPSID_IMPLEMENTER_MASK	(0x000000FFU << FPSID_IMPLEMENTER_BIT)

lib/bsp/standalone/src/cortexr5/gcc/boot.S

@@ -162,12 +162,19 @@ OKToRun:
 
 	bl 	Init_MPU		/* Initialize MPU */
 
+/*
+ * Currently OpenAMP is supported only with HIVEC
+ * exception vectors are set to LOVEC if BSP is not built
+ * for OpenAMP as the default state is HIVEC
+ */
+
+#if USEAMP != 1
 /*set exception vector to LOVEC */
 	mrc	p15, 0, r0, c1, c0, 0
 	mvn	r1, #0x2000
 	and	r0, r0, r1
 	mcr	p15, 0, r0, c1, c0, 0
-
+#endif
 
 /* Enable icahce and dcache */
 	mrc 	p15,0,r1,c1,c0,0

lib/bsp/standalone/src/cortexr5/gcc/open.c

@@ -30,6 +30,10 @@
 *
 ******************************************************************************/
 
+/* Use toolchain function for openamp applications*/
+
+#ifndef USEAMP
+
 #include <errno.h>
 #include "xil_types.h"
 
@@ -50,3 +54,4 @@ __attribute__((weak)) s32 open(char8 *buf, s32 flags, s32 mode)
   errno = EIO;
   return (-1);
 }
+#endif

lib/bsp/standalone/src/cortexr5/gcc/read.c

@@ -29,6 +29,9 @@
 * this Software without prior written authorization from Xilinx.
 *
 ******************************************************************************/
+/* Use toolchain function for openamp applications*/
+
+#ifndef USEAMP
 
 /* read.c -- read bytes from a input device.
  */
@@ -109,3 +112,4 @@ _read (s32 fd, char8* buf, s32 nbytes)
   return 0;
 #endif
 }
+#endif

lib/bsp/standalone/src/cortexr5/gcc/write.c

@@ -30,6 +30,10 @@
 *
 ******************************************************************************/
 
+/* Use toolchain function for openamp applications*/
+
+#ifndef USEAMP
+
 /* write.c -- write bytes to an output device.
  */
 
@@ -109,3 +113,4 @@ _write (s32 fd, char8* buf, s32 nbytes)
   return 0;
 #endif
 }
+#endif

lib/bsp/standalone/src/cortexr5/gcc/xil-crt0.S

@@ -101,8 +101,13 @@ _startup:
 	/* set stack pointer */
 	ldr	r13,.Lstack		/* stack address */
 
+/*
+ * Uart is not initialized for OpenAMP applications
+ * as master processor would be controlling and using the Uart
+ */
+#if USEAMP != 1
 	bl 	Init_Uart		/* Initialize UART */
-
+#endif
 	bl	main			/* Jump to main C code */
 
 	bl	_exit

lib/bsp/standalone/src/cortexr5/xfpd_slcr.h

@@ -0,0 +1,382 @@
+/* ### HEADER ### */
+
+#ifndef __XFPD_SLCR_H__
+#define __XFPD_SLCR_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XfpdSlcr Base Address
+ */
+#define XFPD_SLCR_BASEADDR      0xFD610000UL
+
+/**
+ * Register: XfpdSlcrWprot0
+ */
+#define XFPD_SLCR_WPROT0    ( ( XFPD_SLCR_BASEADDR ) + 0x00000000UL )
+#define XFPD_SLCR_WPROT0_RSTVAL   0x00000001UL
+
+#define XFPD_SLCR_WPROT0_ACT_SHIFT   0UL
+#define XFPD_SLCR_WPROT0_ACT_WIDTH   1UL
+#define XFPD_SLCR_WPROT0_ACT_MASK    0x00000001UL
+#define XFPD_SLCR_WPROT0_ACT_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdSlcrCtrl
+ */
+#define XFPD_SLCR_CTRL    ( ( XFPD_SLCR_BASEADDR ) + 0x00000004UL )
+#define XFPD_SLCR_CTRL_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_CTRL_SLVERR_EN_SHIFT   0UL
+#define XFPD_SLCR_CTRL_SLVERR_EN_WIDTH   1UL
+#define XFPD_SLCR_CTRL_SLVERR_EN_MASK    0x00000001UL
+#define XFPD_SLCR_CTRL_SLVERR_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrIsr
+ */
+#define XFPD_SLCR_ISR    ( ( XFPD_SLCR_BASEADDR ) + 0x00000008UL )
+#define XFPD_SLCR_ISR_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_ISR_ADDR_DECD_ERR_SHIFT   0UL
+#define XFPD_SLCR_ISR_ADDR_DECD_ERR_WIDTH   1UL
+#define XFPD_SLCR_ISR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XFPD_SLCR_ISR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrImr
+ */
+#define XFPD_SLCR_IMR    ( ( XFPD_SLCR_BASEADDR ) + 0x0000000CUL )
+#define XFPD_SLCR_IMR_RSTVAL   0x00000001UL
+
+#define XFPD_SLCR_IMR_ADDR_DECD_ERR_SHIFT   0UL
+#define XFPD_SLCR_IMR_ADDR_DECD_ERR_WIDTH   1UL
+#define XFPD_SLCR_IMR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XFPD_SLCR_IMR_ADDR_DECD_ERR_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdSlcrIer
+ */
+#define XFPD_SLCR_IER    ( ( XFPD_SLCR_BASEADDR ) + 0x00000010UL )
+#define XFPD_SLCR_IER_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_IER_ADDR_DECD_ERR_SHIFT   0UL
+#define XFPD_SLCR_IER_ADDR_DECD_ERR_WIDTH   1UL
+#define XFPD_SLCR_IER_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XFPD_SLCR_IER_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrIdr
+ */
+#define XFPD_SLCR_IDR    ( ( XFPD_SLCR_BASEADDR ) + 0x00000014UL )
+#define XFPD_SLCR_IDR_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_IDR_ADDR_DECD_ERR_SHIFT   0UL
+#define XFPD_SLCR_IDR_ADDR_DECD_ERR_WIDTH   1UL
+#define XFPD_SLCR_IDR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XFPD_SLCR_IDR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrItr
+ */
+#define XFPD_SLCR_ITR    ( ( XFPD_SLCR_BASEADDR ) + 0x00000018UL )
+#define XFPD_SLCR_ITR_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_ITR_ADDR_DECD_ERR_SHIFT   0UL
+#define XFPD_SLCR_ITR_ADDR_DECD_ERR_WIDTH   1UL
+#define XFPD_SLCR_ITR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XFPD_SLCR_ITR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrWdtClkSel
+ */
+#define XFPD_SLCR_WDT_CLK_SEL    ( ( XFPD_SLCR_BASEADDR ) + 0x00000100UL )
+#define XFPD_SLCR_WDT_CLK_SEL_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_WDT_CLK_SEL_SHIFT   0UL
+#define XFPD_SLCR_WDT_CLK_SEL_WIDTH   1UL
+#define XFPD_SLCR_WDT_CLK_SEL_MASK    0x00000001UL
+#define XFPD_SLCR_WDT_CLK_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrIntFpd
+ */
+#define XFPD_SLCR_INT_FPD    ( ( XFPD_SLCR_BASEADDR ) + 0x00000200UL )
+#define XFPD_SLCR_INT_FPD_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_INT_FPD_GFM_SEL_SHIFT   0UL
+#define XFPD_SLCR_INT_FPD_GFM_SEL_WIDTH   1UL
+#define XFPD_SLCR_INT_FPD_GFM_SEL_MASK    0x00000001UL
+#define XFPD_SLCR_INT_FPD_GFM_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrGpu
+ */
+#define XFPD_SLCR_GPU    ( ( XFPD_SLCR_BASEADDR ) + 0x0000100CUL )
+#define XFPD_SLCR_GPU_RSTVAL   0x00000007UL
+
+#define XFPD_SLCR_GPU_ARCACHE_SHIFT   7UL
+#define XFPD_SLCR_GPU_ARCACHE_WIDTH   4UL
+#define XFPD_SLCR_GPU_ARCACHE_MASK    0x00000780UL
+#define XFPD_SLCR_GPU_ARCACHE_DEFVAL  0x0UL
+
+#define XFPD_SLCR_GPU_AWCACHE_SHIFT   3UL
+#define XFPD_SLCR_GPU_AWCACHE_WIDTH   4UL
+#define XFPD_SLCR_GPU_AWCACHE_MASK    0x00000078UL
+#define XFPD_SLCR_GPU_AWCACHE_DEFVAL  0x0UL
+
+#define XFPD_SLCR_GPU_PP1_IDLE_SHIFT   2UL
+#define XFPD_SLCR_GPU_PP1_IDLE_WIDTH   1UL
+#define XFPD_SLCR_GPU_PP1_IDLE_MASK    0x00000004UL
+#define XFPD_SLCR_GPU_PP1_IDLE_DEFVAL  0x1UL
+
+#define XFPD_SLCR_GPU_PP0_IDLE_SHIFT   1UL
+#define XFPD_SLCR_GPU_PP0_IDLE_WIDTH   1UL
+#define XFPD_SLCR_GPU_PP0_IDLE_MASK    0x00000002UL
+#define XFPD_SLCR_GPU_PP0_IDLE_DEFVAL  0x1UL
+
+#define XFPD_SLCR_GPU_IDLE_SHIFT   0UL
+#define XFPD_SLCR_GPU_IDLE_WIDTH   1UL
+#define XFPD_SLCR_GPU_IDLE_MASK    0x00000001UL
+#define XFPD_SLCR_GPU_IDLE_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdSlcrGdmaCfg
+ */
+#define XFPD_SLCR_GDMA_CFG    ( ( XFPD_SLCR_BASEADDR ) + 0x00003000UL )
+#define XFPD_SLCR_GDMA_CFG_RSTVAL   0x00000048UL
+
+#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_SHIFT   5UL
+#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_WIDTH   2UL
+#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_MASK    0x00000060UL
+#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_DEFVAL  0x2UL
+
+#define XFPD_SLCR_GDMA_CFG_NUM_CH_SHIFT   0UL
+#define XFPD_SLCR_GDMA_CFG_NUM_CH_WIDTH   5UL
+#define XFPD_SLCR_GDMA_CFG_NUM_CH_MASK    0x0000001fUL
+#define XFPD_SLCR_GDMA_CFG_NUM_CH_DEFVAL  0x8UL
+
+/**
+ * Register: XfpdSlcrGdma
+ */
+#define XFPD_SLCR_GDMA    ( ( XFPD_SLCR_BASEADDR ) + 0x00003010UL )
+#define XFPD_SLCR_GDMA_RSTVAL   0x00003b3bUL
+
+#define XFPD_SLCR_GDMA_RAM1_EMAB_SHIFT   12UL
+#define XFPD_SLCR_GDMA_RAM1_EMAB_WIDTH   3UL
+#define XFPD_SLCR_GDMA_RAM1_EMAB_MASK    0x00007000UL
+#define XFPD_SLCR_GDMA_RAM1_EMAB_DEFVAL  0x3UL
+
+#define XFPD_SLCR_GDMA_RAM1_EMASA_SHIFT   11UL
+#define XFPD_SLCR_GDMA_RAM1_EMASA_WIDTH   1UL
+#define XFPD_SLCR_GDMA_RAM1_EMASA_MASK    0x00000800UL
+#define XFPD_SLCR_GDMA_RAM1_EMASA_DEFVAL  0x1UL
+
+#define XFPD_SLCR_GDMA_RAM1_EMAA_SHIFT   8UL
+#define XFPD_SLCR_GDMA_RAM1_EMAA_WIDTH   3UL
+#define XFPD_SLCR_GDMA_RAM1_EMAA_MASK    0x00000700UL
+#define XFPD_SLCR_GDMA_RAM1_EMAA_DEFVAL  0x3UL
+
+#define XFPD_SLCR_GDMA_RAM0_EMAB_SHIFT   4UL
+#define XFPD_SLCR_GDMA_RAM0_EMAB_WIDTH   3UL
+#define XFPD_SLCR_GDMA_RAM0_EMAB_MASK    0x00000070UL
+#define XFPD_SLCR_GDMA_RAM0_EMAB_DEFVAL  0x3UL
+
+#define XFPD_SLCR_GDMA_RAM0_EMASA_SHIFT   3UL
+#define XFPD_SLCR_GDMA_RAM0_EMASA_WIDTH   1UL
+#define XFPD_SLCR_GDMA_RAM0_EMASA_MASK    0x00000008UL
+#define XFPD_SLCR_GDMA_RAM0_EMASA_DEFVAL  0x1UL
+
+#define XFPD_SLCR_GDMA_RAM0_EMAA_SHIFT   0UL
+#define XFPD_SLCR_GDMA_RAM0_EMAA_WIDTH   3UL
+#define XFPD_SLCR_GDMA_RAM0_EMAA_MASK    0x00000007UL
+#define XFPD_SLCR_GDMA_RAM0_EMAA_DEFVAL  0x3UL
+
+/**
+ * Register: XfpdSlcrAfiFs
+ */
+#define XFPD_SLCR_AFI_FS    ( ( XFPD_SLCR_BASEADDR ) + 0x00005000UL )
+#define XFPD_SLCR_AFI_FS_RSTVAL   0x00000a00UL
+
+#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_SHIFT   10UL
+#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_WIDTH   2UL
+#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_MASK    0x00000c00UL
+#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_DEFVAL  0x2UL
+
+#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_SHIFT   8UL
+#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_WIDTH   2UL
+#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_MASK    0x00000300UL
+#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_DEFVAL  0x2UL
+
+/**
+ * Register: XfpdSlcrErrAtbIsr
+ */
+#define XFPD_SLCR_ERR_ATB_ISR    ( ( XFPD_SLCR_BASEADDR ) + 0x00006000UL )
+#define XFPD_SLCR_ERR_ATB_ISR_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_SHIFT   2UL
+#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_MASK    0x00000004UL
+#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_DEFVAL  0x0UL
+
+#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_SHIFT   1UL
+#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_MASK    0x00000002UL
+#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_DEFVAL  0x0UL
+
+#define XFPD_SLCR_ERR_ATB_ISR_FPDS_SHIFT   0UL
+#define XFPD_SLCR_ERR_ATB_ISR_FPDS_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_ISR_FPDS_MASK    0x00000001UL
+#define XFPD_SLCR_ERR_ATB_ISR_FPDS_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrErrAtbImr
+ */
+#define XFPD_SLCR_ERR_ATB_IMR    ( ( XFPD_SLCR_BASEADDR ) + 0x00006004UL )
+#define XFPD_SLCR_ERR_ATB_IMR_RSTVAL   0x00000007UL
+
+#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_SHIFT   2UL
+#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_MASK    0x00000004UL
+#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_DEFVAL  0x1UL
+
+#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_SHIFT   1UL
+#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_MASK    0x00000002UL
+#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_DEFVAL  0x1UL
+
+#define XFPD_SLCR_ERR_ATB_IMR_FPDS_SHIFT   0UL
+#define XFPD_SLCR_ERR_ATB_IMR_FPDS_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_IMR_FPDS_MASK    0x00000001UL
+#define XFPD_SLCR_ERR_ATB_IMR_FPDS_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdSlcrErrAtbIer
+ */
+#define XFPD_SLCR_ERR_ATB_IER    ( ( XFPD_SLCR_BASEADDR ) + 0x00006008UL )
+#define XFPD_SLCR_ERR_ATB_IER_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_SHIFT   2UL
+#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_MASK    0x00000004UL
+#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_DEFVAL  0x0UL
+
+#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_SHIFT   1UL
+#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_MASK    0x00000002UL
+#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_DEFVAL  0x0UL
+
+#define XFPD_SLCR_ERR_ATB_IER_FPDS_SHIFT   0UL
+#define XFPD_SLCR_ERR_ATB_IER_FPDS_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_IER_FPDS_MASK    0x00000001UL
+#define XFPD_SLCR_ERR_ATB_IER_FPDS_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrErrAtbIdr
+ */
+#define XFPD_SLCR_ERR_ATB_IDR    ( ( XFPD_SLCR_BASEADDR ) + 0x0000600CUL )
+#define XFPD_SLCR_ERR_ATB_IDR_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_SHIFT   2UL
+#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_MASK    0x00000004UL
+#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_DEFVAL  0x0UL
+
+#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_SHIFT   1UL
+#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_MASK    0x00000002UL
+#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_DEFVAL  0x0UL
+
+#define XFPD_SLCR_ERR_ATB_IDR_FPDS_SHIFT   0UL
+#define XFPD_SLCR_ERR_ATB_IDR_FPDS_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_IDR_FPDS_MASK    0x00000001UL
+#define XFPD_SLCR_ERR_ATB_IDR_FPDS_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrAtbCmdstore
+ */
+#define XFPD_SLCR_ATB_CMDSTORE    ( ( XFPD_SLCR_BASEADDR ) + 0x00006010UL )
+#define XFPD_SLCR_ATB_CMDSTORE_RSTVAL   0x00000007UL
+
+#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_SHIFT   2UL
+#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_WIDTH   1UL
+#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_MASK    0x00000004UL
+#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_DEFVAL  0x1UL
+
+#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_SHIFT   1UL
+#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_WIDTH   1UL
+#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_MASK    0x00000002UL
+#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_DEFVAL  0x1UL
+
+#define XFPD_SLCR_ATB_CMDSTORE_FPDS_SHIFT   0UL
+#define XFPD_SLCR_ATB_CMDSTORE_FPDS_WIDTH   1UL
+#define XFPD_SLCR_ATB_CMDSTORE_FPDS_MASK    0x00000001UL
+#define XFPD_SLCR_ATB_CMDSTORE_FPDS_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdSlcrAtbRespEn
+ */
+#define XFPD_SLCR_ATB_RESP_EN    ( ( XFPD_SLCR_BASEADDR ) + 0x00006014UL )
+#define XFPD_SLCR_ATB_RESP_EN_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_SHIFT   2UL
+#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_WIDTH   1UL
+#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_MASK    0x00000004UL
+#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_DEFVAL  0x0UL
+
+#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_SHIFT   1UL
+#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_WIDTH   1UL
+#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_MASK    0x00000002UL
+#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_DEFVAL  0x0UL
+
+#define XFPD_SLCR_ATB_RESP_EN_FPDS_SHIFT   0UL
+#define XFPD_SLCR_ATB_RESP_EN_FPDS_WIDTH   1UL
+#define XFPD_SLCR_ATB_RESP_EN_FPDS_MASK    0x00000001UL
+#define XFPD_SLCR_ATB_RESP_EN_FPDS_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrAtbResptype
+ */
+#define XFPD_SLCR_ATB_RESPTYPE    ( ( XFPD_SLCR_BASEADDR ) + 0x00006018UL )
+#define XFPD_SLCR_ATB_RESPTYPE_RSTVAL   0x00000007UL
+
+#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_SHIFT   2UL
+#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_WIDTH   1UL
+#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_MASK    0x00000004UL
+#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_DEFVAL  0x1UL
+
+#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_SHIFT   1UL
+#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_WIDTH   1UL
+#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_MASK    0x00000002UL
+#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_DEFVAL  0x1UL
+
+#define XFPD_SLCR_ATB_RESPTYPE_FPDS_SHIFT   0UL
+#define XFPD_SLCR_ATB_RESPTYPE_FPDS_WIDTH   1UL
+#define XFPD_SLCR_ATB_RESPTYPE_FPDS_MASK    0x00000001UL
+#define XFPD_SLCR_ATB_RESPTYPE_FPDS_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdSlcrAtbPrescale
+ */
+#define XFPD_SLCR_ATB_PRESCALE    ( ( XFPD_SLCR_BASEADDR ) + 0x00006020UL )
+#define XFPD_SLCR_ATB_PRESCALE_RSTVAL   0x0000ffffUL
+
+#define XFPD_SLCR_ATB_PRESCALE_EN_SHIFT   16UL
+#define XFPD_SLCR_ATB_PRESCALE_EN_WIDTH   1UL
+#define XFPD_SLCR_ATB_PRESCALE_EN_MASK    0x00010000UL
+#define XFPD_SLCR_ATB_PRESCALE_EN_DEFVAL  0x0UL
+
+#define XFPD_SLCR_ATB_PRESCALE_VAL_SHIFT   0UL
+#define XFPD_SLCR_ATB_PRESCALE_VAL_WIDTH   16UL
+#define XFPD_SLCR_ATB_PRESCALE_VAL_MASK    0x0000ffffUL
+#define XFPD_SLCR_ATB_PRESCALE_VAL_DEFVAL  0xffffUL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XFPD_SLCR_H__ */

lib/bsp/standalone/src/cortexr5/xfpd_slcr_secure.h

@@ -0,0 +1,277 @@
+/* ### HEADER ### */
+
+#ifndef __XFPD_SLCR_SECURE_H__
+#define __XFPD_SLCR_SECURE_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XfpdSlcrSecure Base Address
+ */
+#define XFPD_SLCR_SECURE_BASEADDR      0xFD690000UL
+
+/**
+ * Register: XfpdSlcrSecCtrl
+ */
+#define XFPD_SLCR_SEC_CTRL    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000004UL )
+#define XFPD_SLCR_SEC_CTRL_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_SHIFT   0UL
+#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_WIDTH   1UL
+#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_MASK    0x00000001UL
+#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrSecIsr
+ */
+#define XFPD_SLCR_SEC_ISR    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000008UL )
+#define XFPD_SLCR_SEC_ISR_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_SHIFT   0UL
+#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_WIDTH   1UL
+#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrSecImr
+ */
+#define XFPD_SLCR_SEC_IMR    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x0000000CUL )
+#define XFPD_SLCR_SEC_IMR_RSTVAL   0x00000001UL
+
+#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_SHIFT   0UL
+#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_WIDTH   1UL
+#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdSlcrSecIer
+ */
+#define XFPD_SLCR_SEC_IER    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000010UL )
+#define XFPD_SLCR_SEC_IER_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_SHIFT   0UL
+#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_WIDTH   1UL
+#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrSecIdr
+ */
+#define XFPD_SLCR_SEC_IDR    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000014UL )
+#define XFPD_SLCR_SEC_IDR_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_SHIFT   0UL
+#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_WIDTH   1UL
+#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrSecItr
+ */
+#define XFPD_SLCR_SEC_ITR    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000018UL )
+#define XFPD_SLCR_SEC_ITR_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_SHIFT   0UL
+#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_WIDTH   1UL
+#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrSecSata
+ */
+#define XFPD_SLCR_SEC_SATA    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000020UL )
+#define XFPD_SLCR_SEC_SATA_RSTVAL   0x0000000eUL
+
+#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_SHIFT   3UL
+#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_WIDTH   1UL
+#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_MASK    0x00000008UL
+#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_SHIFT   2UL
+#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_WIDTH   1UL
+#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_MASK    0x00000004UL
+#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_SATA_TZ_AXIS_SHIFT   1UL
+#define XFPD_SLCR_SEC_SATA_TZ_AXIS_WIDTH   1UL
+#define XFPD_SLCR_SEC_SATA_TZ_AXIS_MASK    0x00000002UL
+#define XFPD_SLCR_SEC_SATA_TZ_AXIS_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_SATA_TZ_EN_SHIFT   0UL
+#define XFPD_SLCR_SEC_SATA_TZ_EN_WIDTH   1UL
+#define XFPD_SLCR_SEC_SATA_TZ_EN_MASK    0x00000001UL
+#define XFPD_SLCR_SEC_SATA_TZ_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrSecPcie
+ */
+#define XFPD_SLCR_SEC_PCIE    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000030UL )
+#define XFPD_SLCR_SEC_PCIE_RSTVAL   0x01ffffffUL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_SHIFT   24UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_MASK    0x01000000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_SHIFT   23UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_MASK    0x00800000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_SHIFT   22UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_MASK    0x00400000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_SHIFT   21UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_MASK    0x00200000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_SHIFT   20UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_MASK    0x00100000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_SHIFT   19UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_MASK    0x00080000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_SHIFT   18UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_MASK    0x00040000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_SHIFT   17UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_MASK    0x00020000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_SHIFT   16UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_MASK    0x00010000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_SHIFT   15UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_MASK    0x00008000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_SHIFT   14UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_MASK    0x00004000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_SHIFT   13UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_MASK    0x00002000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_SHIFT   12UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_MASK    0x00001000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_SHIFT   11UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_MASK    0x00000800UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_SHIFT   10UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_MASK    0x00000400UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_SHIFT   9UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_MASK    0x00000200UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_SHIFT   8UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_MASK    0x00000100UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_SHIFT   7UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_MASK    0x00000080UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_SHIFT   6UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_MASK    0x00000040UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_SHIFT   5UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_MASK    0x00000020UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_SHIFT   4UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_MASK    0x00000010UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_SHIFT   3UL
+#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_MASK    0x00000008UL
+#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_SHIFT   2UL
+#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_MASK    0x00000004UL
+#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_SHIFT   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_MASK    0x00000002UL
+#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_SHIFT   0UL
+#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_MASK    0x00000001UL
+#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdSlcrSecDpdma
+ */
+#define XFPD_SLCR_SEC_DPDMA    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000040UL )
+#define XFPD_SLCR_SEC_DPDMA_RSTVAL   0x00000001UL
+
+#define XFPD_SLCR_SEC_DPDMA_TZ_SHIFT   0UL
+#define XFPD_SLCR_SEC_DPDMA_TZ_WIDTH   1UL
+#define XFPD_SLCR_SEC_DPDMA_TZ_MASK    0x00000001UL
+#define XFPD_SLCR_SEC_DPDMA_TZ_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdSlcrSecGdma
+ */
+#define XFPD_SLCR_SEC_GDMA    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000050UL )
+#define XFPD_SLCR_SEC_GDMA_RSTVAL   0x000000ffUL
+
+#define XFPD_SLCR_SEC_GDMA_TZ_SHIFT   0UL
+#define XFPD_SLCR_SEC_GDMA_TZ_WIDTH   8UL
+#define XFPD_SLCR_SEC_GDMA_TZ_MASK    0x000000ffUL
+#define XFPD_SLCR_SEC_GDMA_TZ_DEFVAL  0xffUL
+
+/**
+ * Register: XfpdSlcrSecGic
+ */
+#define XFPD_SLCR_SEC_GIC    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000060UL )
+#define XFPD_SLCR_SEC_GIC_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_SEC_GIC_CFG_DIS_SHIFT   0UL
+#define XFPD_SLCR_SEC_GIC_CFG_DIS_WIDTH   1UL
+#define XFPD_SLCR_SEC_GIC_CFG_DIS_MASK    0x00000001UL
+#define XFPD_SLCR_SEC_GIC_CFG_DIS_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XFPD_SLCR_SECURE_H__ */

lib/bsp/standalone/src/cortexr5/xfpd_xmpu_sink.h

@@ -0,0 +1,81 @@
+/* ### HEADER ### */
+
+#ifndef __XFPD_XMPU_SINK_H__
+#define __XFPD_XMPU_SINK_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XfpdXmpuSink Base Address
+ */
+#define XFPD_XMPU_SINK_BASEADDR      0xFD4F0000UL
+
+/**
+ * Register: XfpdXmpuSinkErrSts
+ */
+#define XFPD_XMPU_SINK_ERR_STS    ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF00UL )
+#define XFPD_XMPU_SINK_ERR_STS_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_SINK_ERR_STS_RDWR_SHIFT   31UL
+#define XFPD_XMPU_SINK_ERR_STS_RDWR_WIDTH   1UL
+#define XFPD_XMPU_SINK_ERR_STS_RDWR_MASK    0x80000000UL
+#define XFPD_XMPU_SINK_ERR_STS_RDWR_DEFVAL  0x0UL
+
+#define XFPD_XMPU_SINK_ERR_STS_ADDR_SHIFT   0UL
+#define XFPD_XMPU_SINK_ERR_STS_ADDR_WIDTH   12UL
+#define XFPD_XMPU_SINK_ERR_STS_ADDR_MASK    0x00000fffUL
+#define XFPD_XMPU_SINK_ERR_STS_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuSinkIsr
+ */
+#define XFPD_XMPU_SINK_ISR    ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF10UL )
+#define XFPD_XMPU_SINK_ISR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_SINK_ISRADDRDECDERR_SHIFT   0UL
+#define XFPD_XMPU_SINK_ISRADDRDECDERR_WIDTH   1UL
+#define XFPD_XMPU_SINK_ISRADDRDECDERR_MASK    0x00000001UL
+#define XFPD_XMPU_SINK_ISRADDRDECDERR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuSinkImr
+ */
+#define XFPD_XMPU_SINK_IMR    ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF14UL )
+#define XFPD_XMPU_SINK_IMR_RSTVAL   0x00000001UL
+
+#define XFPD_XMPU_SINK_IMRADDRDECDERR_SHIFT   0UL
+#define XFPD_XMPU_SINK_IMRADDRDECDERR_WIDTH   1UL
+#define XFPD_XMPU_SINK_IMRADDRDECDERR_MASK    0x00000001UL
+#define XFPD_XMPU_SINK_IMRADDRDECDERR_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdXmpuSinkIer
+ */
+#define XFPD_XMPU_SINK_IER    ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF18UL )
+#define XFPD_XMPU_SINK_IER_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_SINK_IERADDRDECDERR_SHIFT   0UL
+#define XFPD_XMPU_SINK_IERADDRDECDERR_WIDTH   1UL
+#define XFPD_XMPU_SINK_IERADDRDECDERR_MASK    0x00000001UL
+#define XFPD_XMPU_SINK_IERADDRDECDERR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuSinkIdr
+ */
+#define XFPD_XMPU_SINK_IDR    ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF1CUL )
+#define XFPD_XMPU_SINK_IDR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_SINK_IDRADDRDECDERR_SHIFT   0UL
+#define XFPD_XMPU_SINK_IDRADDRDECDERR_WIDTH   1UL
+#define XFPD_XMPU_SINK_IDRADDRDECDERR_MASK    0x00000001UL
+#define XFPD_XMPU_SINK_IDRADDRDECDERR_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XFPD_XMPU_SINK_H__ */

lib/bsp/standalone/src/cortexr5/xil_cache.c

@@ -62,7 +62,7 @@
 
 
 extern s32  _stack_end;
-extern s32  _stack;
+extern s32  __undef_stack;
 
 /****************************************************************************/
 /************************** Function Prototypes ******************************/
@@ -143,10 +143,10 @@ void Xil_DCacheInvalidate(void)
 
 
 	stack_end = (u32 )&_stack_end;
-	stack_start = (u32 )&_stack;
-	stack_size=stack_start-stack_end;
+	stack_start = (u32 )&__undef_stack;
+	stack_size = stack_start-stack_end;
 
-	/*Flush stack memory to save return address*/
+	/* Flush stack memory to save return address */
 	Xil_DCacheFlushRange(stack_end, stack_size);
 
 	mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);

lib/bsp/standalone/src/cortexr5/xiou_secure_slcr.h

@@ -0,0 +1,174 @@
+/* ### HEADER ### */
+
+#ifndef __XIOU_SECURE_SLCR_H__
+#define __XIOU_SECURE_SLCR_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XiouSecureSlcr Base Address
+ */
+#define XIOU_SECURE_SLCR_BASEADDR      0xFF240000UL
+
+/**
+ * Register: XiouSecSlcrAxiWprtcn
+ */
+#define XIOU_SEC_SLCR_AXI_WPRTCN    ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000000UL )
+#define XIOU_SEC_SLCR_AXI_WPRTCN_RSTVAL   0x00000000UL
+
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_SHIFT   25UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_MASK    0x0e000000UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_SHIFT   22UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_MASK    0x01c00000UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_SHIFT   19UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_MASK    0x00380000UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_SHIFT   16UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_MASK    0x00070000UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT   9UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK    0x00000e00UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT   6UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK    0x000001c0UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT   3UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK    0x00000038UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT   0UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK    0x00000007UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSecSlcrAxiRprtcn
+ */
+#define XIOU_SEC_SLCR_AXI_RPRTCN    ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000004UL )
+#define XIOU_SEC_SLCR_AXI_RPRTCN_RSTVAL   0x00000000UL
+
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_SHIFT   22UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_MASK    0x01c00000UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_SHIFT   19UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_MASK    0x00380000UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_SHIFT   16UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_MASK    0x00070000UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT   9UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK    0x00000e00UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT   6UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK    0x000001c0UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT   3UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK    0x00000038UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT   0UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK    0x00000007UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSecSlcrCtrl
+ */
+#define XIOU_SEC_SLCR_CTRL    ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000040UL )
+#define XIOU_SEC_SLCR_CTRL_RSTVAL   0x00000000UL
+
+#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_SHIFT   0UL
+#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_WIDTH   1UL
+#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_MASK    0x00000001UL
+#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSecSlcrIsr
+ */
+#define XIOU_SEC_SLCR_ISR    ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000044UL )
+#define XIOU_SEC_SLCR_ISR_RSTVAL   0x00000000UL
+
+#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_SHIFT   0UL
+#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_WIDTH   1UL
+#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSecSlcrImr
+ */
+#define XIOU_SEC_SLCR_IMR    ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000048UL )
+#define XIOU_SEC_SLCR_IMR_RSTVAL   0x00000001UL
+
+#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_SHIFT   0UL
+#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_WIDTH   1UL
+#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_DEFVAL  0x1UL
+
+/**
+ * Register: XiouSecSlcrIer
+ */
+#define XIOU_SEC_SLCR_IER    ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x0000004CUL )
+#define XIOU_SEC_SLCR_IER_RSTVAL   0x00000000UL
+
+#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_SHIFT   0UL
+#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_WIDTH   1UL
+#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSecSlcrIdr
+ */
+#define XIOU_SEC_SLCR_IDR    ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000050UL )
+#define XIOU_SEC_SLCR_IDR_RSTVAL   0x00000000UL
+
+#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_SHIFT   0UL
+#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_WIDTH   1UL
+#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSecSlcrItr
+ */
+#define XIOU_SEC_SLCR_ITR    ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000054UL )
+#define XIOU_SEC_SLCR_ITR_RSTVAL   0x00000000UL
+
+#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_SHIFT   0UL
+#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_WIDTH   1UL
+#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XIOU_SECURE_SLCR_H__ */

lib/bsp/standalone/src/cortexr5/xlpd_slcr_secure.h

@@ -0,0 +1,141 @@
+/* ### HEADER ### */
+
+#ifndef __XLPD_SLCR_SECURE_H__
+#define __XLPD_SLCR_SECURE_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XlpdSlcrSecure Base Address
+ */
+#define XLPD_SLCR_SECURE_BASEADDR      0xFF4B0000UL
+
+/**
+ * Register: XlpdSlcrSecCtrl
+ */
+#define XLPD_SLCR_SEC_CTRL    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000004UL )
+#define XLPD_SLCR_SEC_CTRL_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_SHIFT   0UL
+#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_WIDTH   1UL
+#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_MASK    0x00000001UL
+#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSecIsr
+ */
+#define XLPD_SLCR_SEC_ISR    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000008UL )
+#define XLPD_SLCR_SEC_ISR_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_SHIFT   0UL
+#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_WIDTH   1UL
+#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSecImr
+ */
+#define XLPD_SLCR_SEC_IMR    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x0000000CUL )
+#define XLPD_SLCR_SEC_IMR_RSTVAL   0x00000001UL
+
+#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_SHIFT   0UL
+#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_WIDTH   1UL
+#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrSecIer
+ */
+#define XLPD_SLCR_SEC_IER    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000010UL )
+#define XLPD_SLCR_SEC_IER_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_SHIFT   0UL
+#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_WIDTH   1UL
+#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSecIdr
+ */
+#define XLPD_SLCR_SEC_IDR    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000014UL )
+#define XLPD_SLCR_SEC_IDR_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_SHIFT   0UL
+#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_WIDTH   1UL
+#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSecItr
+ */
+#define XLPD_SLCR_SEC_ITR    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000018UL )
+#define XLPD_SLCR_SEC_ITR_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_SHIFT   0UL
+#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_WIDTH   1UL
+#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSecRpu
+ */
+#define XLPD_SLCR_SEC_RPU    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000020UL )
+#define XLPD_SLCR_SEC_RPU_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SEC_RPU_TZ_R5_1_SHIFT   1UL
+#define XLPD_SLCR_SEC_RPU_TZ_R5_1_WIDTH   1UL
+#define XLPD_SLCR_SEC_RPU_TZ_R5_1_MASK    0x00000002UL
+#define XLPD_SLCR_SEC_RPU_TZ_R5_1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_SEC_RPU_TZ_R5_0_SHIFT   0UL
+#define XLPD_SLCR_SEC_RPU_TZ_R5_0_WIDTH   1UL
+#define XLPD_SLCR_SEC_RPU_TZ_R5_0_MASK    0x00000001UL
+#define XLPD_SLCR_SEC_RPU_TZ_R5_0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSecAdma
+ */
+#define XLPD_SLCR_SEC_ADMA    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000024UL )
+#define XLPD_SLCR_SEC_ADMA_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SEC_ADMA_TZ_SHIFT   0UL
+#define XLPD_SLCR_SEC_ADMA_TZ_WIDTH   8UL
+#define XLPD_SLCR_SEC_ADMA_TZ_MASK    0x000000ffUL
+#define XLPD_SLCR_SEC_ADMA_TZ_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSecSafetyChk
+ */
+#define XLPD_SLCR_SEC_SAFETY_CHK    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000030UL )
+#define XLPD_SLCR_SEC_SAFETY_CHK_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_SHIFT   0UL
+#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_WIDTH   32UL
+#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_MASK    0xffffffffUL
+#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSecUsb
+ */
+#define XLPD_SLCR_SEC_USB    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000034UL )
+#define XLPD_SLCR_SEC_USB_RSTVAL   0x00000003UL
+
+#define XLPD_SLCR_SEC_USB_TZ_USB3_1_SHIFT   1UL
+#define XLPD_SLCR_SEC_USB_TZ_USB3_1_WIDTH   1UL
+#define XLPD_SLCR_SEC_USB_TZ_USB3_1_MASK    0x00000002UL
+#define XLPD_SLCR_SEC_USB_TZ_USB3_1_DEFVAL  0x1UL
+
+#define XLPD_SLCR_SEC_USB_TZ_USB3_0_SHIFT   0UL
+#define XLPD_SLCR_SEC_USB_TZ_USB3_0_WIDTH   1UL
+#define XLPD_SLCR_SEC_USB_TZ_USB3_0_MASK    0x00000001UL
+#define XLPD_SLCR_SEC_USB_TZ_USB3_0_DEFVAL  0x1UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XLPD_SLCR_SECURE_H__ */

lib/bsp/standalone/src/cortexr5/xlpd_xppu.h

@@ -0,0 +1,858 @@
+/* ### HEADER ### */
+
+#ifndef __XLPD_XPPU_H__
+#define __XLPD_XPPU_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XlpdXppu Base Address
+ */
+#define XLPD_XPPU_BASEADDR      0xFF980000UL
+
+/**
+ * Register: XlpdXppuCtrl
+ */
+#define XLPD_XPPU_CTRL    ( ( XLPD_XPPU_BASEADDR ) + 0x00000000UL )
+#define XLPD_XPPU_CTRL_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_CTRL_APER_PARITY_EN_SHIFT   2UL
+#define XLPD_XPPU_CTRL_APER_PARITY_EN_WIDTH   1UL
+#define XLPD_XPPU_CTRL_APER_PARITY_EN_MASK    0x00000004UL
+#define XLPD_XPPU_CTRL_APER_PARITY_EN_DEFVAL  0x0UL
+
+#define XLPD_XPPU_CTRL_MID_PARITY_EN_SHIFT   1UL
+#define XLPD_XPPU_CTRL_MID_PARITY_EN_WIDTH   1UL
+#define XLPD_XPPU_CTRL_MID_PARITY_EN_MASK    0x00000002UL
+#define XLPD_XPPU_CTRL_MID_PARITY_EN_DEFVAL  0x0UL
+
+#define XLPD_XPPU_CTRL_EN_SHIFT   0UL
+#define XLPD_XPPU_CTRL_EN_WIDTH   1UL
+#define XLPD_XPPU_CTRL_EN_MASK    0x00000001UL
+#define XLPD_XPPU_CTRL_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuErrSts1
+ */
+#define XLPD_XPPU_ERR_STS1    ( ( XLPD_XPPU_BASEADDR ) + 0x00000004UL )
+#define XLPD_XPPU_ERR_STS1_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_ERR_STS1_AXI_ADDR_SHIFT   0UL
+#define XLPD_XPPU_ERR_STS1_AXI_ADDR_WIDTH   32UL
+#define XLPD_XPPU_ERR_STS1_AXI_ADDR_MASK    0xffffffffUL
+#define XLPD_XPPU_ERR_STS1_AXI_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuErrSts2
+ */
+#define XLPD_XPPU_ERR_STS2    ( ( XLPD_XPPU_BASEADDR ) + 0x00000008UL )
+#define XLPD_XPPU_ERR_STS2_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_ERR_STS2_AXI_ID_SHIFT   0UL
+#define XLPD_XPPU_ERR_STS2_AXI_ID_WIDTH   16UL
+#define XLPD_XPPU_ERR_STS2_AXI_ID_MASK    0x0000ffffUL
+#define XLPD_XPPU_ERR_STS2_AXI_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuPoison
+ */
+#define XLPD_XPPU_POISON    ( ( XLPD_XPPU_BASEADDR ) + 0x0000000CUL )
+#define XLPD_XPPU_POISON_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_POISON_BASE_SHIFT   0UL
+#define XLPD_XPPU_POISON_BASE_WIDTH   20UL
+#define XLPD_XPPU_POISON_BASE_MASK    0x000fffffUL
+#define XLPD_XPPU_POISON_BASE_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuIsr
+ */
+#define XLPD_XPPU_ISR    ( ( XLPD_XPPU_BASEADDR ) + 0x00000010UL )
+#define XLPD_XPPU_ISR_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_ISR_APER_PARITY_SHIFT   7UL
+#define XLPD_XPPU_ISR_APER_PARITY_WIDTH   1UL
+#define XLPD_XPPU_ISR_APER_PARITY_MASK    0x00000080UL
+#define XLPD_XPPU_ISR_APER_PARITY_DEFVAL  0x0UL
+
+#define XLPD_XPPU_ISR_APER_TZ_SHIFT   6UL
+#define XLPD_XPPU_ISR_APER_TZ_WIDTH   1UL
+#define XLPD_XPPU_ISR_APER_TZ_MASK    0x00000040UL
+#define XLPD_XPPU_ISR_APER_TZ_DEFVAL  0x0UL
+
+#define XLPD_XPPU_ISR_APER_PERM_SHIFT   5UL
+#define XLPD_XPPU_ISR_APER_PERM_WIDTH   1UL
+#define XLPD_XPPU_ISR_APER_PERM_MASK    0x00000020UL
+#define XLPD_XPPU_ISR_APER_PERM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_ISR_MID_PARITY_SHIFT   3UL
+#define XLPD_XPPU_ISR_MID_PARITY_WIDTH   1UL
+#define XLPD_XPPU_ISR_MID_PARITY_MASK    0x00000008UL
+#define XLPD_XPPU_ISR_MID_PARITY_DEFVAL  0x0UL
+
+#define XLPD_XPPU_ISR_MID_RO_SHIFT   2UL
+#define XLPD_XPPU_ISR_MID_RO_WIDTH   1UL
+#define XLPD_XPPU_ISR_MID_RO_MASK    0x00000004UL
+#define XLPD_XPPU_ISR_MID_RO_DEFVAL  0x0UL
+
+#define XLPD_XPPU_ISR_MID_MISS_SHIFT   1UL
+#define XLPD_XPPU_ISR_MID_MISS_WIDTH   1UL
+#define XLPD_XPPU_ISR_MID_MISS_MASK    0x00000002UL
+#define XLPD_XPPU_ISR_MID_MISS_DEFVAL  0x0UL
+
+#define XLPD_XPPU_ISR_INV_APB_SHIFT   0UL
+#define XLPD_XPPU_ISR_INV_APB_WIDTH   1UL
+#define XLPD_XPPU_ISR_INV_APB_MASK    0x00000001UL
+#define XLPD_XPPU_ISR_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuImr
+ */
+#define XLPD_XPPU_IMR    ( ( XLPD_XPPU_BASEADDR ) + 0x00000014UL )
+#define XLPD_XPPU_IMR_RSTVAL   0x000000efUL
+
+#define XLPD_XPPU_IMR_APER_PARITY_SHIFT   7UL
+#define XLPD_XPPU_IMR_APER_PARITY_WIDTH   1UL
+#define XLPD_XPPU_IMR_APER_PARITY_MASK    0x00000080UL
+#define XLPD_XPPU_IMR_APER_PARITY_DEFVAL  0x1UL
+
+#define XLPD_XPPU_IMR_APER_TZ_SHIFT   6UL
+#define XLPD_XPPU_IMR_APER_TZ_WIDTH   1UL
+#define XLPD_XPPU_IMR_APER_TZ_MASK    0x00000040UL
+#define XLPD_XPPU_IMR_APER_TZ_DEFVAL  0x1UL
+
+#define XLPD_XPPU_IMR_APER_PERM_SHIFT   5UL
+#define XLPD_XPPU_IMR_APER_PERM_WIDTH   1UL
+#define XLPD_XPPU_IMR_APER_PERM_MASK    0x00000020UL
+#define XLPD_XPPU_IMR_APER_PERM_DEFVAL  0x1UL
+
+#define XLPD_XPPU_IMR_MID_PARITY_SHIFT   3UL
+#define XLPD_XPPU_IMR_MID_PARITY_WIDTH   1UL
+#define XLPD_XPPU_IMR_MID_PARITY_MASK    0x00000008UL
+#define XLPD_XPPU_IMR_MID_PARITY_DEFVAL  0x1UL
+
+#define XLPD_XPPU_IMR_MID_RO_SHIFT   2UL
+#define XLPD_XPPU_IMR_MID_RO_WIDTH   1UL
+#define XLPD_XPPU_IMR_MID_RO_MASK    0x00000004UL
+#define XLPD_XPPU_IMR_MID_RO_DEFVAL  0x1UL
+
+#define XLPD_XPPU_IMR_MID_MISS_SHIFT   1UL
+#define XLPD_XPPU_IMR_MID_MISS_WIDTH   1UL
+#define XLPD_XPPU_IMR_MID_MISS_MASK    0x00000002UL
+#define XLPD_XPPU_IMR_MID_MISS_DEFVAL  0x1UL
+
+#define XLPD_XPPU_IMR_INV_APB_SHIFT   0UL
+#define XLPD_XPPU_IMR_INV_APB_WIDTH   1UL
+#define XLPD_XPPU_IMR_INV_APB_MASK    0x00000001UL
+#define XLPD_XPPU_IMR_INV_APB_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdXppuIen
+ */
+#define XLPD_XPPU_IEN    ( ( XLPD_XPPU_BASEADDR ) + 0x00000018UL )
+#define XLPD_XPPU_IEN_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_IEN_APER_PARITY_SHIFT   7UL
+#define XLPD_XPPU_IEN_APER_PARITY_WIDTH   1UL
+#define XLPD_XPPU_IEN_APER_PARITY_MASK    0x00000080UL
+#define XLPD_XPPU_IEN_APER_PARITY_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IEN_APER_TZ_SHIFT   6UL
+#define XLPD_XPPU_IEN_APER_TZ_WIDTH   1UL
+#define XLPD_XPPU_IEN_APER_TZ_MASK    0x00000040UL
+#define XLPD_XPPU_IEN_APER_TZ_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IEN_APER_PERM_SHIFT   5UL
+#define XLPD_XPPU_IEN_APER_PERM_WIDTH   1UL
+#define XLPD_XPPU_IEN_APER_PERM_MASK    0x00000020UL
+#define XLPD_XPPU_IEN_APER_PERM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IEN_MID_PARITY_SHIFT   3UL
+#define XLPD_XPPU_IEN_MID_PARITY_WIDTH   1UL
+#define XLPD_XPPU_IEN_MID_PARITY_MASK    0x00000008UL
+#define XLPD_XPPU_IEN_MID_PARITY_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IEN_MID_RO_SHIFT   2UL
+#define XLPD_XPPU_IEN_MID_RO_WIDTH   1UL
+#define XLPD_XPPU_IEN_MID_RO_MASK    0x00000004UL
+#define XLPD_XPPU_IEN_MID_RO_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IEN_MID_MISS_SHIFT   1UL
+#define XLPD_XPPU_IEN_MID_MISS_WIDTH   1UL
+#define XLPD_XPPU_IEN_MID_MISS_MASK    0x00000002UL
+#define XLPD_XPPU_IEN_MID_MISS_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IEN_INV_APB_SHIFT   0UL
+#define XLPD_XPPU_IEN_INV_APB_WIDTH   1UL
+#define XLPD_XPPU_IEN_INV_APB_MASK    0x00000001UL
+#define XLPD_XPPU_IEN_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuIds
+ */
+#define XLPD_XPPU_IDS    ( ( XLPD_XPPU_BASEADDR ) + 0x0000001CUL )
+#define XLPD_XPPU_IDS_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_IDS_APER_PARITY_SHIFT   7UL
+#define XLPD_XPPU_IDS_APER_PARITY_WIDTH   1UL
+#define XLPD_XPPU_IDS_APER_PARITY_MASK    0x00000080UL
+#define XLPD_XPPU_IDS_APER_PARITY_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IDS_APER_TZ_SHIFT   6UL
+#define XLPD_XPPU_IDS_APER_TZ_WIDTH   1UL
+#define XLPD_XPPU_IDS_APER_TZ_MASK    0x00000040UL
+#define XLPD_XPPU_IDS_APER_TZ_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IDS_APER_PERM_SHIFT   5UL
+#define XLPD_XPPU_IDS_APER_PERM_WIDTH   1UL
+#define XLPD_XPPU_IDS_APER_PERM_MASK    0x00000020UL
+#define XLPD_XPPU_IDS_APER_PERM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IDS_MID_PARITY_SHIFT   3UL
+#define XLPD_XPPU_IDS_MID_PARITY_WIDTH   1UL
+#define XLPD_XPPU_IDS_MID_PARITY_MASK    0x00000008UL
+#define XLPD_XPPU_IDS_MID_PARITY_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IDS_MID_RO_SHIFT   2UL
+#define XLPD_XPPU_IDS_MID_RO_WIDTH   1UL
+#define XLPD_XPPU_IDS_MID_RO_MASK    0x00000004UL
+#define XLPD_XPPU_IDS_MID_RO_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IDS_MID_MISS_SHIFT   1UL
+#define XLPD_XPPU_IDS_MID_MISS_WIDTH   1UL
+#define XLPD_XPPU_IDS_MID_MISS_MASK    0x00000002UL
+#define XLPD_XPPU_IDS_MID_MISS_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IDS_INV_APB_SHIFT   0UL
+#define XLPD_XPPU_IDS_INV_APB_WIDTH   1UL
+#define XLPD_XPPU_IDS_INV_APB_MASK    0x00000001UL
+#define XLPD_XPPU_IDS_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMMstrIds
+ */
+#define XLPD_XPPU_M_MSTR_IDS    ( ( XLPD_XPPU_BASEADDR ) + 0x0000003CUL )
+#define XLPD_XPPU_M_MSTR_IDS_RSTVAL   0x00000014UL
+
+#define XLPD_XPPU_M_MSTR_IDS_NO_SHIFT   0UL
+#define XLPD_XPPU_M_MSTR_IDS_NO_WIDTH   32UL
+#define XLPD_XPPU_M_MSTR_IDS_NO_MASK    0xffffffffUL
+#define XLPD_XPPU_M_MSTR_IDS_NO_DEFVAL  0x14UL
+
+/**
+ * Register: XlpdXppuMAperture32b
+ */
+#define XLPD_XPPU_M_APERTURE_32B    ( ( XLPD_XPPU_BASEADDR ) + 0x00000040UL )
+#define XLPD_XPPU_M_APERTURE_32B_RSTVAL   0x00000080UL
+
+#define XLPD_XPPU_M_APERTURE_32B_NO_SHIFT   0UL
+#define XLPD_XPPU_M_APERTURE_32B_NO_WIDTH   32UL
+#define XLPD_XPPU_M_APERTURE_32B_NO_MASK    0xffffffffUL
+#define XLPD_XPPU_M_APERTURE_32B_NO_DEFVAL  0x80UL
+
+/**
+ * Register: XlpdXppuMAperture64kb
+ */
+#define XLPD_XPPU_M_APERTURE_64KB    ( ( XLPD_XPPU_BASEADDR ) + 0x00000044UL )
+#define XLPD_XPPU_M_APERTURE_64KB_RSTVAL   0x00000100UL
+
+#define XLPD_XPPU_M_APERTURE_64KB_NO_SHIFT   0UL
+#define XLPD_XPPU_M_APERTURE_64KB_NO_WIDTH   32UL
+#define XLPD_XPPU_M_APERTURE_64KB_NO_MASK    0xffffffffUL
+#define XLPD_XPPU_M_APERTURE_64KB_NO_DEFVAL  0x100UL
+
+/**
+ * Register: XlpdXppuMAperture1mb
+ */
+#define XLPD_XPPU_M_APERTURE_1MB    ( ( XLPD_XPPU_BASEADDR ) + 0x00000048UL )
+#define XLPD_XPPU_M_APERTURE_1MB_RSTVAL   0x00000010UL
+
+#define XLPD_XPPU_M_APERTURE_1MB_NO_SHIFT   0UL
+#define XLPD_XPPU_M_APERTURE_1MB_NO_WIDTH   32UL
+#define XLPD_XPPU_M_APERTURE_1MB_NO_MASK    0xffffffffUL
+#define XLPD_XPPU_M_APERTURE_1MB_NO_DEFVAL  0x10UL
+
+/**
+ * Register: XlpdXppuMAperture512mb
+ */
+#define XLPD_XPPU_M_APERTURE_512MB    ( ( XLPD_XPPU_BASEADDR ) + 0x0000004CUL )
+#define XLPD_XPPU_M_APERTURE_512MB_RSTVAL   0x00000001UL
+
+#define XLPD_XPPU_M_APERTURE_512MB_NO_SHIFT   0UL
+#define XLPD_XPPU_M_APERTURE_512MB_NO_WIDTH   32UL
+#define XLPD_XPPU_M_APERTURE_512MB_NO_MASK    0xffffffffUL
+#define XLPD_XPPU_M_APERTURE_512MB_NO_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdXppuBase32b
+ */
+#define XLPD_XPPU_BASE_32B    ( ( XLPD_XPPU_BASEADDR ) + 0x00000050UL )
+#define XLPD_XPPU_BASE_32B_RSTVAL   0xff990000UL
+
+#define XLPD_XPPU_BASE_32B_ADDR_SHIFT   0UL
+#define XLPD_XPPU_BASE_32B_ADDR_WIDTH   32UL
+#define XLPD_XPPU_BASE_32B_ADDR_MASK    0xffffffffUL
+#define XLPD_XPPU_BASE_32B_ADDR_DEFVAL  0xff990000UL
+
+/**
+ * Register: XlpdXppuBase64kb
+ */
+#define XLPD_XPPU_BASE_64KB    ( ( XLPD_XPPU_BASEADDR ) + 0x00000054UL )
+#define XLPD_XPPU_BASE_64KB_RSTVAL   0xff000000UL
+
+#define XLPD_XPPU_BASE_64KB_ADDR_SHIFT   0UL
+#define XLPD_XPPU_BASE_64KB_ADDR_WIDTH   32UL
+#define XLPD_XPPU_BASE_64KB_ADDR_MASK    0xffffffffUL
+#define XLPD_XPPU_BASE_64KB_ADDR_DEFVAL  0xff000000UL
+
+/**
+ * Register: XlpdXppuBase1mb
+ */
+#define XLPD_XPPU_BASE_1MB    ( ( XLPD_XPPU_BASEADDR ) + 0x00000058UL )
+#define XLPD_XPPU_BASE_1MB_RSTVAL   0xfe000000UL
+
+#define XLPD_XPPU_BASE_1MB_ADDR_SHIFT   0UL
+#define XLPD_XPPU_BASE_1MB_ADDR_WIDTH   32UL
+#define XLPD_XPPU_BASE_1MB_ADDR_MASK    0xffffffffUL
+#define XLPD_XPPU_BASE_1MB_ADDR_DEFVAL  0xfe000000UL
+
+/**
+ * Register: XlpdXppuBase512mb
+ */
+#define XLPD_XPPU_BASE_512MB    ( ( XLPD_XPPU_BASEADDR ) + 0x0000005CUL )
+#define XLPD_XPPU_BASE_512MB_RSTVAL   0xc0000000UL
+
+#define XLPD_XPPU_BASE_512MB_ADDR_SHIFT   0UL
+#define XLPD_XPPU_BASE_512MB_ADDR_WIDTH   32UL
+#define XLPD_XPPU_BASE_512MB_ADDR_MASK    0xffffffffUL
+#define XLPD_XPPU_BASE_512MB_ADDR_DEFVAL  0xc0000000UL
+
+/**
+ * Register: XlpdXppuMstrId00
+ */
+#define XLPD_XPPU_MSTR_ID00    ( ( XLPD_XPPU_BASEADDR ) + 0x00000100UL )
+#define XLPD_XPPU_MSTR_ID00_RSTVAL   0x83ff0040UL
+
+#define XLPD_XPPU_MSTR_ID00_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID00_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID00_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID00_MIDP_DEFVAL  0x1UL
+
+#define XLPD_XPPU_MSTR_ID00_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID00_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID00_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID00_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID00_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID00_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID00_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID00_MIDM_DEFVAL  0x3ffUL
+
+#define XLPD_XPPU_MSTR_ID00_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID00_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID00_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID00_MID_DEFVAL  0x40UL
+
+/**
+ * Register: XlpdXppuMstrId01
+ */
+#define XLPD_XPPU_MSTR_ID01    ( ( XLPD_XPPU_BASEADDR ) + 0x00000104UL )
+#define XLPD_XPPU_MSTR_ID01_RSTVAL   0x03f00000UL
+
+#define XLPD_XPPU_MSTR_ID01_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID01_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID01_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID01_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID01_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID01_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID01_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID01_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID01_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID01_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID01_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID01_MIDM_DEFVAL  0x3f0UL
+
+#define XLPD_XPPU_MSTR_ID01_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID01_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID01_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID01_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId02
+ */
+#define XLPD_XPPU_MSTR_ID02    ( ( XLPD_XPPU_BASEADDR ) + 0x00000108UL )
+#define XLPD_XPPU_MSTR_ID02_RSTVAL   0x83f00010UL
+
+#define XLPD_XPPU_MSTR_ID02_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID02_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID02_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID02_MIDP_DEFVAL  0x1UL
+
+#define XLPD_XPPU_MSTR_ID02_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID02_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID02_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID02_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID02_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID02_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID02_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID02_MIDM_DEFVAL  0x3f0UL
+
+#define XLPD_XPPU_MSTR_ID02_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID02_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID02_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID02_MID_DEFVAL  0x10UL
+
+/**
+ * Register: XlpdXppuMstrId03
+ */
+#define XLPD_XPPU_MSTR_ID03    ( ( XLPD_XPPU_BASEADDR ) + 0x0000010CUL )
+#define XLPD_XPPU_MSTR_ID03_RSTVAL   0x83c00080UL
+
+#define XLPD_XPPU_MSTR_ID03_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID03_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID03_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID03_MIDP_DEFVAL  0x1UL
+
+#define XLPD_XPPU_MSTR_ID03_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID03_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID03_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID03_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID03_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID03_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID03_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID03_MIDM_DEFVAL  0x3c0UL
+
+#define XLPD_XPPU_MSTR_ID03_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID03_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID03_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID03_MID_DEFVAL  0x80UL
+
+/**
+ * Register: XlpdXppuMstrId04
+ */
+#define XLPD_XPPU_MSTR_ID04    ( ( XLPD_XPPU_BASEADDR ) + 0x00000110UL )
+#define XLPD_XPPU_MSTR_ID04_RSTVAL   0x83c30080UL
+
+#define XLPD_XPPU_MSTR_ID04_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID04_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID04_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID04_MIDP_DEFVAL  0x1UL
+
+#define XLPD_XPPU_MSTR_ID04_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID04_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID04_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID04_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID04_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID04_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID04_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID04_MIDM_DEFVAL  0x3c3UL
+
+#define XLPD_XPPU_MSTR_ID04_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID04_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID04_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID04_MID_DEFVAL  0x80UL
+
+/**
+ * Register: XlpdXppuMstrId05
+ */
+#define XLPD_XPPU_MSTR_ID05    ( ( XLPD_XPPU_BASEADDR ) + 0x00000114UL )
+#define XLPD_XPPU_MSTR_ID05_RSTVAL   0x03c30081UL
+
+#define XLPD_XPPU_MSTR_ID05_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID05_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID05_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID05_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID05_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID05_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID05_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID05_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID05_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID05_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID05_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID05_MIDM_DEFVAL  0x3c3UL
+
+#define XLPD_XPPU_MSTR_ID05_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID05_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID05_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID05_MID_DEFVAL  0x81UL
+
+/**
+ * Register: XlpdXppuMstrId06
+ */
+#define XLPD_XPPU_MSTR_ID06    ( ( XLPD_XPPU_BASEADDR ) + 0x00000118UL )
+#define XLPD_XPPU_MSTR_ID06_RSTVAL   0x03c30082UL
+
+#define XLPD_XPPU_MSTR_ID06_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID06_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID06_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID06_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID06_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID06_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID06_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID06_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID06_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID06_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID06_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID06_MIDM_DEFVAL  0x3c3UL
+
+#define XLPD_XPPU_MSTR_ID06_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID06_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID06_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID06_MID_DEFVAL  0x82UL
+
+/**
+ * Register: XlpdXppuMstrId07
+ */
+#define XLPD_XPPU_MSTR_ID07    ( ( XLPD_XPPU_BASEADDR ) + 0x0000011CUL )
+#define XLPD_XPPU_MSTR_ID07_RSTVAL   0x83c30083UL
+
+#define XLPD_XPPU_MSTR_ID07_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID07_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID07_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID07_MIDP_DEFVAL  0x1UL
+
+#define XLPD_XPPU_MSTR_ID07_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID07_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID07_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID07_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID07_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID07_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID07_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID07_MIDM_DEFVAL  0x3c3UL
+
+#define XLPD_XPPU_MSTR_ID07_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID07_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID07_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID07_MID_DEFVAL  0x83UL
+
+/**
+ * Register: XlpdXppuMstrId08
+ */
+#define XLPD_XPPU_MSTR_ID08    ( ( XLPD_XPPU_BASEADDR ) + 0x00000120UL )
+#define XLPD_XPPU_MSTR_ID08_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID08_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID08_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID08_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID08_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID08_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID08_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID08_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID08_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID08_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID08_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID08_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID08_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID08_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID08_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID08_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID08_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId09
+ */
+#define XLPD_XPPU_MSTR_ID09    ( ( XLPD_XPPU_BASEADDR ) + 0x00000124UL )
+#define XLPD_XPPU_MSTR_ID09_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID09_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID09_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID09_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID09_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID09_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID09_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID09_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID09_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID09_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID09_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID09_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID09_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID09_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID09_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID09_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID09_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId10
+ */
+#define XLPD_XPPU_MSTR_ID10    ( ( XLPD_XPPU_BASEADDR ) + 0x00000128UL )
+#define XLPD_XPPU_MSTR_ID10_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID10_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID10_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID10_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID10_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID10_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID10_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID10_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID10_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID10_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID10_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID10_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID10_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID10_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID10_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID10_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID10_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId11
+ */
+#define XLPD_XPPU_MSTR_ID11    ( ( XLPD_XPPU_BASEADDR ) + 0x0000012CUL )
+#define XLPD_XPPU_MSTR_ID11_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID11_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID11_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID11_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID11_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID11_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID11_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID11_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID11_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID11_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID11_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID11_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID11_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID11_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID11_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID11_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID11_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId12
+ */
+#define XLPD_XPPU_MSTR_ID12    ( ( XLPD_XPPU_BASEADDR ) + 0x00000130UL )
+#define XLPD_XPPU_MSTR_ID12_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID12_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID12_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID12_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID12_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID12_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID12_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID12_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID12_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID12_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID12_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID12_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID12_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID12_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID12_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID12_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID12_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId13
+ */
+#define XLPD_XPPU_MSTR_ID13    ( ( XLPD_XPPU_BASEADDR ) + 0x00000134UL )
+#define XLPD_XPPU_MSTR_ID13_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID13_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID13_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID13_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID13_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID13_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID13_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID13_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID13_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID13_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID13_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID13_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID13_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID13_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID13_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID13_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID13_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId14
+ */
+#define XLPD_XPPU_MSTR_ID14    ( ( XLPD_XPPU_BASEADDR ) + 0x00000138UL )
+#define XLPD_XPPU_MSTR_ID14_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID14_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID14_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID14_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID14_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID14_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID14_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID14_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID14_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID14_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID14_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID14_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID14_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID14_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID14_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID14_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID14_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId15
+ */
+#define XLPD_XPPU_MSTR_ID15    ( ( XLPD_XPPU_BASEADDR ) + 0x0000013CUL )
+#define XLPD_XPPU_MSTR_ID15_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID15_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID15_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID15_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID15_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID15_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID15_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID15_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID15_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID15_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID15_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID15_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID15_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID15_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID15_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID15_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID15_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId16
+ */
+#define XLPD_XPPU_MSTR_ID16    ( ( XLPD_XPPU_BASEADDR ) + 0x00000140UL )
+#define XLPD_XPPU_MSTR_ID16_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID16_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID16_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID16_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID16_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID16_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID16_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID16_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID16_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID16_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID16_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID16_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID16_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID16_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID16_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID16_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID16_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId17
+ */
+#define XLPD_XPPU_MSTR_ID17    ( ( XLPD_XPPU_BASEADDR ) + 0x00000144UL )
+#define XLPD_XPPU_MSTR_ID17_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID17_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID17_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID17_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID17_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID17_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID17_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID17_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID17_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID17_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID17_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID17_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID17_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID17_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID17_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID17_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID17_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId18
+ */
+#define XLPD_XPPU_MSTR_ID18    ( ( XLPD_XPPU_BASEADDR ) + 0x00000148UL )
+#define XLPD_XPPU_MSTR_ID18_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID18_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID18_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID18_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID18_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID18_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID18_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID18_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID18_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID18_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID18_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID18_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID18_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID18_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID18_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID18_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID18_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId19
+ */
+#define XLPD_XPPU_MSTR_ID19    ( ( XLPD_XPPU_BASEADDR ) + 0x0000014CUL )
+#define XLPD_XPPU_MSTR_ID19_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID19_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID19_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID19_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID19_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID19_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID19_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID19_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID19_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID19_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID19_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID19_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID19_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID19_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID19_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID19_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID19_MID_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XLPD_XPPU_H__ */

lib/bsp/standalone/src/cortexr5/xlpd_xppu_sink.h

@@ -0,0 +1,81 @@
+/* ### HEADER ### */
+
+#ifndef __XLPD_XPPU_SINK_H__
+#define __XLPD_XPPU_SINK_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XlpdXppuSink Base Address
+ */
+#define XLPD_XPPU_SINK_BASEADDR      0xFF9C0000UL
+
+/**
+ * Register: XlpdXppuSinkErrSts
+ */
+#define XLPD_XPPU_SINK_ERR_STS    ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF00UL )
+#define XLPD_XPPU_SINK_ERR_STS_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_SINK_ERR_STS_RDWR_SHIFT   31UL
+#define XLPD_XPPU_SINK_ERR_STS_RDWR_WIDTH   1UL
+#define XLPD_XPPU_SINK_ERR_STS_RDWR_MASK    0x80000000UL
+#define XLPD_XPPU_SINK_ERR_STS_RDWR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_SINK_ERR_STS_ADDR_SHIFT   0UL
+#define XLPD_XPPU_SINK_ERR_STS_ADDR_WIDTH   12UL
+#define XLPD_XPPU_SINK_ERR_STS_ADDR_MASK    0x00000fffUL
+#define XLPD_XPPU_SINK_ERR_STS_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuSinkIsr
+ */
+#define XLPD_XPPU_SINK_ISR    ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF10UL )
+#define XLPD_XPPU_SINK_ISR_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_SINK_ISRADDRDECDERR_SHIFT   0UL
+#define XLPD_XPPU_SINK_ISRADDRDECDERR_WIDTH   1UL
+#define XLPD_XPPU_SINK_ISRADDRDECDERR_MASK    0x00000001UL
+#define XLPD_XPPU_SINK_ISRADDRDECDERR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuSinkImr
+ */
+#define XLPD_XPPU_SINK_IMR    ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF14UL )
+#define XLPD_XPPU_SINK_IMR_RSTVAL   0x00000001UL
+
+#define XLPD_XPPU_SINK_IMRADDRDECDERR_SHIFT   0UL
+#define XLPD_XPPU_SINK_IMRADDRDECDERR_WIDTH   1UL
+#define XLPD_XPPU_SINK_IMRADDRDECDERR_MASK    0x00000001UL
+#define XLPD_XPPU_SINK_IMRADDRDECDERR_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdXppuSinkIer
+ */
+#define XLPD_XPPU_SINK_IER    ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF18UL )
+#define XLPD_XPPU_SINK_IER_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_SINK_IERADDRDECDERR_SHIFT   0UL
+#define XLPD_XPPU_SINK_IERADDRDECDERR_WIDTH   1UL
+#define XLPD_XPPU_SINK_IERADDRDECDERR_MASK    0x00000001UL
+#define XLPD_XPPU_SINK_IERADDRDECDERR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuSinkIdr
+ */
+#define XLPD_XPPU_SINK_IDR    ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF1CUL )
+#define XLPD_XPPU_SINK_IDR_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_SINK_IDRADDRDECDERR_SHIFT   0UL
+#define XLPD_XPPU_SINK_IDRADDRDECDERR_WIDTH   1UL
+#define XLPD_XPPU_SINK_IDRADDRDECDERR_MASK    0x00000001UL
+#define XLPD_XPPU_SINK_IDRADDRDECDERR_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XLPD_XPPU_SINK_H__ */

lib/bsp/standalone/src/cortexr5/xparameters_ps.h

@@ -116,7 +116,28 @@ extern "C" {
 #define XPAR_XDMAPS_0_DONE_INTR_5	XPS_DMA5_INT_ID
 #define XPAR_XDMAPS_0_DONE_INTR_6	XPS_DMA6_INT_ID
 #define XPAR_XDMAPS_0_DONE_INTR_7	XPS_DMA7_INT_ID
-#define XPAR_XNANDPS8_0_INTR        XPS_NAND_INT_ID
+#define XPAR_XNANDPS8_0_INTR	        XPS_NAND_INT_ID
+#define XPAR_XADMAPS_0_INTR 		XPS_ADMA_CH0_INT_ID
+#define XPAR_XADMAPS_1_INTR 		XPS_ADMA_CH1_INT_ID
+#define XPAR_XADMAPS_2_INTR		XPS_ADMA_CH2_INT_ID
+#define XPAR_XADMAPS_3_INTR 		XPS_ADMA_CH3_INT_ID
+#define XPAR_XADMAPS_4_INTR		XPS_ADMA_CH4_INT_ID
+#define XPAR_XADMAPS_5_INTR 		XPS_ADMA_CH5_INT_ID
+#define XPAR_XADMAPS_6_INTR 		XPS_ADMA_CH6_INT_ID
+#define XPAR_XADMAPS_7_INTR 		XPS_ADMA_CH7_INT_ID
+#define XPAR_XCSUDMA_INTR 		XPS_CSU_DMA_INT_ID
+#define XPAR_XMPU_LPD_INTR 		XPS_XMPU_LPD_INT_ID
+#define XPAR_XZDMAPS_0_INTR		XPS_ZDMA_CH0_INT_ID
+#define XPAR_XZDMAPS_1_INTR		XPS_ZDMA_CH1_INT_ID
+#define XPAR_XZDMAPS_2_INTR 		XPS_ZDMA_CH2_INT_ID
+#define XPAR_XZDMAPS_3_INTR 		XPS_ZDMA_CH3_INT_ID
+#define XPAR_XZDMAPS_4_INTR		XPS_ZDMA_CH4_INT_ID
+#define XPAR_XZDMAPS_5_INTR 		XPS_ZDMA_CH5_INT_ID
+#define XPAR_XZDMAPS_6_INTR 		XPS_ZDMA_CH6_INT_ID
+#define XPAR_XZDMAPS_7_INTR 		XPS_ZDMA_CH7_INT_ID
+#define XPAR_XMPU_FPD_INTR 		XPS_XMPU_FPD_INT_ID
+#define XPAR_XCCI_FPD_INTR 		XPS_FPD_CCI_INT_ID
+#define XPAR_XSMMU_FPD_INTR 		XPS_FPD_SMMU_INT_ID
 
 /* Canonical definitions for SCU GIC */
 #define XPAR_SCUGIC_NUM_INSTANCES	1U
@@ -137,14 +158,12 @@ extern "C" {
 #define XPS_SCU_PERIPH_BASE		0xF9000000U
 
 
-/* Shared Peripheral Interrupts (SPI) */
 /* Shared Peripheral Interrupts (SPI) */
 
+/* FIXME */
+/*#define XPS_FPGA0_INT_ID		100U */
 #define XPS_USB1_INT_ID			76U
 #define XPS_USB0_INT_ID			53U
-
-#define XPS_NAND_INT_ID        (32U + 32U)
-
 #define XPS_FPGA1_INT_ID		62U
 #define XPS_FPGA2_INT_ID		63U
 #define XPS_FPGA3_INT_ID		64U
@@ -165,46 +184,65 @@ extern "C" {
 #define XPS_FPGA14_INT_ID		90U
 #define XPS_FPGA15_INT_ID		91U
 
+/* Updated Interrupt-IDs */
+#define XPS_OCMINTR_INT_ID		(10U + 32U)
+#define XPS_NAND_INT_ID        (14U + 32U)
+#define XPS_QSPI_INT_ID			(15U + 32U)
+#define XPS_GPIO_INT_ID			(16U + 32U)
+#define XPS_I2C0_INT_ID			(17U + 32U)
+#define XPS_I2C1_INT_ID			(18U + 32U)
+#define XPS_SPI0_INT_ID			(19U + 32U)
+#define XPS_SPI1_INT_ID			(20U + 32U)
+#define XPS_UART0_INT_ID		(21U + 32U)
+#define XPS_UART1_INT_ID		(22U + 32U)
+#define XPS_CAN0_INT_ID			(23U + 32U)
+#define XPS_CAN1_INT_ID			(24U + 32U)
+#define XPS_WDT_INT_ID			(113U + 32U)
+#define XPS_LP_WDT_INT_ID			(52U + 32U)
+#define XPS_TTC0_0_INT_ID		(36U + 32U)
+#define XPS_TTC0_1_INT_ID		(37U + 32U)
+#define XPS_TTC0_2_INT_ID 		(38U + 32U)
+#define XPS_TTC1_0_INT_ID		(39U + 32U)
+#define XPS_TTC1_1_INT_ID		(40U + 32U)
+#define XPS_TTC1_2_INT_ID		(41U + 32U)
+#define XPS_TTC2_0_INT_ID		(42U + 32U)
+#define XPS_TTC2_1_INT_ID		(43U + 32U)
+#define XPS_TTC2_2_INT_ID		(44U + 32U)
+#define XPS_TTC3_0_INT_ID		(45U + 32U)
+#define XPS_TTC3_1_INT_ID		(46U + 32U)
+#define XPS_TTC3_2_INT_ID		(47U + 32U)
+#define XPS_SDIO0_INT_ID		(48U + 32U)
+#define XPS_SDIO1_INT_ID		(49U + 32U)
+#define XPS_GEM0_INT_ID			(57U + 32U)
+#define XPS_GEM0_WAKE_INT_ID		(58U + 32U)
+#define XPS_GEM1_INT_ID			(59U + 32U)
+#define XPS_GEM1_WAKE_INT_ID		(60U + 32U)
+#define XPS_GEM2_INT_ID			(61U + 32U)
+#define XPS_GEM2_WAKE_INT_ID		(62U + 32U)
+#define XPS_GEM3_INT_ID			(63U + 32U)
+#define XPS_GEM3_WAKE_INT_ID		(64U + 32U)
+#define XPS_ADMA_CH0_INT_ID		(77U + 32U)
+#define XPS_ADMA_CH1_INT_ID		(78U + 32U)
+#define XPS_ADMA_CH2_INT_ID		(79U + 32U)
+#define XPS_ADMA_CH3_INT_ID		(80U + 32U)
+#define XPS_ADMA_CH4_INT_ID		(81U + 32U)
+#define XPS_ADMA_CH5_INT_ID		(82U + 32U)
+#define XPS_ADMA_CH6_INT_ID		(83U + 32U)
+#define XPS_ADMA_CH7_INT_ID		(84U + 32U)
+#define XPS_CSU_DMA_INT_ID		(86U + 32U)
+#define XPS_XMPU_LPD_INT_ID		(88U + 32U)
+#define XPS_ZDMA_CH0_INT_ID		(124U + 32U)
+#define XPS_ZDMA_CH1_INT_ID		(125U + 32U)
+#define XPS_ZDMA_CH2_INT_ID		(126U + 32U)
+#define XPS_ZDMA_CH3_INT_ID		(127U + 32U)
+#define XPS_ZDMA_CH4_INT_ID		(128U + 32U)
+#define XPS_ZDMA_CH5_INT_ID		(129U + 32U)
+#define XPS_ZDMA_CH6_INT_ID		(130U + 32U)
+#define XPS_ZDMA_CH7_INT_ID		(131U + 32U)
+#define XPS_XMPU_FPD_INT_ID		(134U + 32U)
+#define XPS_FPD_CCI_INT_ID		(154U + 32U)
+#define XPS_FPD_SMMU_INT_ID		(155U + 32U)
 
-#define XPS_OCMINTR_INT_ID		(28U + 32U)
-#define XPS_QSPI_INT_ID			(33U + 32U)
-#define XPS_GPIO_INT_ID			(34U + 32U)
-#define XPS_WDT_INT_ID			(106U + 32U)
-#define XPS_LP_WDT_INT_ID			(69U + 32U)
-#define XPS_TTC0_0_INT_ID		(53U + 32U)
-#define XPS_TTC0_1_INT_ID		(54U + 32U)
-#define XPS_TTC0_2_INT_ID 		(55U + 32U)
-#define XPS_SDIO0_INT_ID		(65U + 32U)
-#define XPS_I2C0_INT_ID			(35U + 32U)
-#define XPS_SPI0_INT_ID			(37U + 32U)
-#define XPS_UART0_INT_ID		(39U + 32U)
-#define XPS_CAN0_INT_ID			(41U + 32U)
-
-/* FIXME */
-//#define XPS_FPGA0_INT_ID		100
-
-#define XPS_TTC1_0_INT_ID		(56U + 32U)
-#define XPS_TTC1_1_INT_ID		(57U + 32U)
-#define XPS_TTC1_2_INT_ID		(58U + 32U)
-#define XPS_TTC2_0_INT_ID		(59U + 32U)
-#define XPS_TTC2_1_INT_ID		(60U + 32U)
-#define XPS_TTC2_2_INT_ID		(61U + 32U)
-#define XPS_TTC3_0_INT_ID		(62U + 32U)
-#define XPS_TTC3_1_INT_ID		(63U + 32U)
-#define XPS_TTC3_2_INT_ID		(64U + 32U)
-#define XPS_SDIO1_INT_ID		(66U + 32U)
-#define XPS_I2C1_INT_ID			(36U + 32U)
-#define XPS_SPI1_INT_ID			(38U + 32U)
-#define XPS_UART1_INT_ID		(40U + 32U)
-#define XPS_CAN1_INT_ID			(42U + 32U)
-#define XPS_GEM0_INT_ID			(73U + 32U)
-#define XPS_GEM0_WAKE_INT_ID		(74U + 32U)
-#define XPS_GEM1_INT_ID			(75U + 32U)
-#define XPS_GEM1_WAKE_INT_ID		(76U + 32U)
-#define XPS_GEM2_INT_ID			(77U + 32U)
-#define XPS_GEM2_WAKE_INT_ID		(78U + 32U)
-#define XPS_GEM3_INT_ID			(79U + 32U)
-#define XPS_GEM3_WAKE_INT_ID		(80U + 32U)
 
 /* Private Peripheral Interrupts (PPI) */
 /*#define XPS_GLOBAL_TMR_INT_ID		27	 SCU Global Timer interrupt */