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nandpsu: Remove buswidth option

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Controller supports only 8 bit mode. So, no need to configure
this value as this is the only option supported.

Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Acked-by: Anirudha Sarangi   <anirudh@xilinx.com>
This commit is contained in:
Punnaiah Choudary Kalluri 2015-07-28 17:15:09 +05:30 • committed by Nava kishore Manne
parent 73e7150785
commit aeb988e08a
2 changed files with 1 additions and 58 deletions
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55
XilinxProcessorIPLib/drivers/nandpsu/src/xnandpsu.c
View file

@ -169,8 +169,6 @@ static void XNandPsu_SetPageColAddr(XNandPsu *InstancePtr, u32 Page, u16 Col);
static void XNandPsu_SetPageSize(XNandPsu *InstancePtr);
static void XNandPsu_SetBusWidth(XNandPsu *InstancePtr);
static void XNandPsu_SelectChip(XNandPsu *InstancePtr, u32 Target);
static s32 XNandPsu_OnfiReset(XNandPsu *InstancePtr, u32 Target);
@ -578,9 +576,6 @@ static void XNandPsu_InitFeatures(XNandPsu *InstancePtr, OnfiParamPage *Param)
*/
Xil_AssertVoid(Param != NULL);
InstancePtr->Features.BusWidth = ((Param->Features & (1U << 0U)) != 0U) ?
XNANDPSU_BUS_WIDTH_16 :
XNANDPSU_BUS_WIDTH_8;
InstancePtr->Features.NvDdr = ((Param->Features & (1U << 5)) != 0U) ?
1U : 0U;
InstancePtr->Features.EzNand = ((Param->Features & (1U << 9)) != 0U) ?
@ -1156,31 +1151,6 @@ static void XNandPsu_SetEccSpareCmd(XNandPsu *InstancePtr, u16 SpareCmd,
(u32)SpareCmd | ((u32)AddrCycles << 28U));
}
/*****************************************************************************/
/**
*
* This function sets the flash bus width in memory address2 register.
*
* @param InstancePtr is a pointer to the XNandPsu instance.
*
* @return
* None
*
* @note None
*
******************************************************************************/
static void XNandPsu_SetBusWidth(XNandPsu *InstancePtr)
{
/*
* Update Memory Address2 register with bus width
*/
XNandPsu_ReadModifyWrite(InstancePtr, XNANDPSU_MEM_ADDR2_OFFSET,
XNANDPSU_MEM_ADDR2_BUS_WIDTH_MASK,
(InstancePtr->Features.BusWidth <<
XNANDPSU_MEM_ADDR2_BUS_WIDTH_SHIFT));
}
/*****************************************************************************/
/**
*
@ -2178,10 +2148,6 @@ static s32 XNandPsu_ProgramPage(XNandPsu *InstancePtr, u32 Target, u32 Page,
* Program Column, Page, Block address
*/
XNandPsu_SetPageColAddr(InstancePtr, Page, (u16)Col);
/*
* Set Bus Width
*/
XNandPsu_SetBusWidth(InstancePtr);
/*
* Program Memory Address Register2 for chip select
*/
@ -2454,10 +2420,6 @@ s32 XNandPsu_WriteSpareBytes(XNandPsu *InstancePtr, u32 Page, u8 *Buf)
* Program Column, Page, Block address
*/
XNandPsu_SetPageColAddr(InstancePtr, PageVar, (u16)Col);
/*
* Set Bus Width
*/
XNandPsu_SetBusWidth(InstancePtr);
/*
* Program Memory Address Register2 for chip select
*/
@ -2701,10 +2663,6 @@ static s32 XNandPsu_ReadPage(XNandPsu *InstancePtr, u32 Target, u32 Page,
XNANDPSU_DMA_SYS_ADDR0_OFFSET,
(u32) ((INTPTR)(void *)Buf & 0xFFFFFFFFU));
}
/*
* Set Bus Width
*/
XNandPsu_SetBusWidth(InstancePtr);
/*
* Program Memory Address Register2 for chip select
*/
@ -2989,10 +2947,6 @@ s32 XNandPsu_ReadSpareBytes(XNandPsu *InstancePtr, u32 Page, u8 *Buf)
XNANDPSU_DMA_SYS_ADDR0_OFFSET,
(u32) ((INTPTR)(void *)Buf & 0xFFFFFFFFU));
}
/*
* Set Bus Width
*/
XNandPsu_SetBusWidth(InstancePtr);
/*
* Program Memory Address Register2 for chip select
*/
@ -3766,10 +3720,7 @@ static s32 XNandPsu_ChangeReadColumn(XNandPsu *InstancePtr, u32 Target,
XNANDPSU_DMA_SYS_ADDR0_OFFSET,
(u32) ((INTPTR)(void *)Buf & 0xFFFFFFFFU));
}
/*
* Set Bus Width
*/
XNandPsu_SetBusWidth(InstancePtr);
/*
* Program Memory Address Register2 for chip select
*/
@ -3976,10 +3927,6 @@ static s32 XNandPsu_ChangeWriteColumn(XNandPsu *InstancePtr, u32 Target,
XNANDPSU_DMA_SYS_ADDR0_OFFSET,
(u32) ((INTPTR)(void *)Buf & 0xFFFFFFFFU));
}
/*
* Set Bus Width
*/
XNandPsu_SetBusWidth(InstancePtr);
/*
* Program Memory Address Register2 for chip select
*/

4
XilinxProcessorIPLib/drivers/nandpsu/src/xnandpsu.h
View file

@ -192,9 +192,6 @@ extern "C" {
#define XNANDPSU_PAGE_SIZE_1K_16BIT 1024U /**< 16-bit 2K bytes page */
#define XNANDPSU_MAX_PAGE_SIZE 16384U /**< Max page size supported */
#define XNANDPSU_BUS_WIDTH_8 0U /**< 8-bit bus width */
#define XNANDPSU_BUS_WIDTH_16 1U /**< 16-bit bus width */
#define XNANDPSU_HAMMING 0x1U /**< Hamming Flash */
#define XNANDPSU_BCH 0x2U /**< BCH Flash */
@ -343,7 +340,6 @@ typedef struct {
* The XNandPsu_Features structure contains the ONFI features information.
*/
typedef struct {
u32 BusWidth;
u32 NvDdr;
u32 EzNand;
u32 OnDie;