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video_common: Added EDID parsing of the preferred timing mode (PTM).

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Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
This commit is contained in:
Andrei-Liviu Simion 2014-12-15 21:39:26 -08:00 • committed by Nava kishore Manne
parent bd41eea206
commit aec6a22d78
1 changed files with 53 additions and 1 deletions
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54
XilinxProcessorIPLib/drivers/video_common/src/xedid.h
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@ -104,6 +104,29 @@
/* Standard timings. */
#define XEDID_STD_TIMINGS_H(N) (0x26 + 2 * (N - 1))
#define XEDID_STD_TIMINGS_AR_FRR(N) (0x27 + 2 * (N - 1))
/* 18 byte descriptors. */
#define XEDID_18BYTE_DESCRIPTOR(N) (0x36 + 18 * (N - 1))
#define XEDID_PTM (XEDID_18BYTE_DESCRIPTOR(1))
/* - Detailed timing descriptor (DTD) / Preferred timing mode (PTM). */
#define XEDID_DTD_PTM_PIXEL_CLK_KHZ_LSB 0x00
#define XEDID_DTD_PTM_PIXEL_CLK_KHZ_MSB 0x01
#define XEDID_DTD_PTM_HRES_LSB 0x02
#define XEDID_DTD_PTM_HBLANK_LSB 0x03
#define XEDID_DTD_PTM_HRES_HBLANK_U4 0x04
#define XEDID_DTD_PTM_VRES_LSB 0x05
#define XEDID_DTD_PTM_VBLANK_LSB 0x06
#define XEDID_DTD_PTM_VRES_VBLANK_U4 0x07
#define XEDID_DTD_PTM_HFPORCH_LSB 0x08
#define XEDID_DTD_PTM_HSPW_LSB 0x09
#define XEDID_DTD_PTM_VFPORCH_VSPW_L4 0x0A
#define XEDID_DTD_PTM_XFPORCH_XSPW_U2 0x0B
#define XEDID_DTD_PTM_HIMGSIZE_MM_LSB 0x0C
#define XEDID_DTD_PTM_VIMGSIZE_MM_LSB 0x0D
#define XEDID_DTD_PTM_XIMGSIZE_MM_U4 0x0E
#define XEDID_DTD_PTM_HBORDER 0x0F
#define XEDID_DTD_PTM_VBORDER 0x10
#define XEDID_DTD_PTM_SIGNAL 0x11
/* Extension block count. */
#define XEDID_EXT_BLK_COUNT 0x7E
/* Checksum. */
@ -112,7 +135,7 @@
/******************************************************************************/
/** @name DPTX core masks, shifts, and register values.
/** @name Extended Display Identification Data: Masks, shifts, and values.
* @{
*/
#define XEDID_VPI_ID_MAN_NAME0_CHAR0_SHIFT 2
@ -210,6 +233,30 @@
#define XEDID_STD_TIMINGS_AR_5_4 0x2
#define XEDID_STD_TIMINGS_AR_16_9 0x3
#define XEDID_STD_TIMINGS_FRR_MASK (0x3F)
/* Detailed timing descriptor (DTD) / Preferred timing mode (PTM). */
#define XEDID_DTD_PTM_XRES_XBLANK_U4_XBLANK_MASK 0x0F
#define XEDID_DTD_PTM_XRES_XBLANK_U4_XRES_MASK 0xF0
#define XEDID_DTD_PTM_XRES_XBLANK_U4_XRES_SHIFT 4
#define XEDID_DTD_PTM_VFPORCH_VSPW_L4_VSPW_MASK 0x0F
#define XEDID_DTD_PTM_VFPORCH_VSPW_L4_VFPORCH_MASK 0xF0
#define XEDID_DTD_PTM_VFPORCH_VSPW_L4_VFPORCH_SHIFT 4
#define XEDID_DTD_PTM_XFPORCH_XSPW_U2_HFPORCH_MASK 0xC0
#define XEDID_DTD_PTM_XFPORCH_XSPW_U2_HSPW_MASK 0x30
#define XEDID_DTD_PTM_XFPORCH_XSPW_U2_VFPORCH_MASK 0x0C
#define XEDID_DTD_PTM_XFPORCH_XSPW_U2_VSPW_MASK 0x03
#define XEDID_DTD_PTM_XFPORCH_XSPW_U2_HFPORCH_SHIFT 6
#define XEDID_DTD_PTM_XFPORCH_XSPW_U2_HSPW_SHIFT 4
#define XEDID_DTD_PTM_XFPORCH_XSPW_U2_VFPORCH_SHIFT 2
#define XEDID_DTD_PTM_XIMGSIZE_MM_U4_VIMGSIZE_MM_MASK 0x0F
#define XEDID_DTD_PTM_XIMGSIZE_MM_U4_HIMGSIZE_MM_MASK 0xF0
#define XEDID_DTD_PTM_XIMGSIZE_MM_U4_HIMGSIZE_MM_SHIFT 4
#define XEDID_DTD_PTM_SIGNAL_INTERLACED_MASK 0x80
#define XEDID_DTD_PTM_SIGNAL_INTERLACED_SHIFT 7
#define XEDID_DTD_PTM_SIGNAL_HPOLARITY_MASK 0x02
#define XEDID_DTD_PTM_SIGNAL_VPOLARITY_MASK 0x04
#define XEDID_DTD_PTM_SIGNAL_HPOLARITY_SHIFT 1
#define XEDID_DTD_PTM_SIGNAL_VPOLARITY_SHIFT 2
/* @} */
/******************* Macros (Inline Functions) Definitions ********************/
@ -363,6 +410,11 @@ float XEDID_GET_CC_WHITEY(u8 *EdidRaw);
((E[XEDID_STD_TIMINGS_AR_FRR(N)] & XEDID_STD_TIMINGS_FRR_MASK) + 60)
u16 XEDID_GET_STD_TIMINGS_V(u8 *EdidRaw, u8 StdTimingsNum);
#define XEDID_IS_DTD_PTM_INTERLACED(E) \
((E[XEDID_PTM + XEDID_DTD_PTM_SIGNAL] & \
XEDID_DTD_PTM_SIGNAL_INTERLACED_MASK) >> \
XEDID_DTD_PTM_SIGNAL_INTERLACED_SHIFT)
/* Extension block count. */
#define XEDID_GET_EXT_BLK_COUNT(E) (E[XEDID_EXT_BLK_COUNT])