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nandps8_v2_0: Modified XNandPs8_EraseBlock API

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Removed clearing of packet register before erase.

Signed-off-by: Shakti Bhatnagar <shaktib@xilinx.com>
This commit is contained in:
Shakti Bhatnagar 2014-12-19 20:06:48 +05:30 • committed by Suneel Garapati
parent 1c24c9317d
commit af857bb2b2
2 changed files with 6 additions and 13 deletions
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14
XilinxProcessorIPLib/drivers/nandps8_v2_0/src/xnandps8.c
View file

@ -62,7 +62,7 @@
* Ver Who Date Changes
* ----- ---- ---------- -----------------------------------------------
* 1.0 nm 05/06/2014 First release
* 2.0 sb 11/04/2014 Removed Null checks for Buffer passed
* 2.0 sb 12/19/2014 Removed Null checks for Buffer passed
* as parameter to Read API's
* - XNandPs8_Read()
* - XNandPs8_ReadPage
@ -97,6 +97,8 @@
* - XNandPs8_SetEccAddrSize
* ECC address now is calculated based upon the
* size of spare area
* Modified Block Erase API, removed clearing of
* packet register before erase.
* </pre>
*
******************************************************************************/
@ -3082,16 +3084,6 @@ s32 XNandPs8_EraseBlock(XNandPs8 *InstancePtr, u32 Target, u32 Block)
ErasePage = (Page >> 16U) & 0xFFFFU;
EraseCol = Page & 0xFFFFU;
#ifdef RTL_3_1_DRIVER_WORKAROUND
/*
* The sequence read, {erase, read status}, {program, read status}
* fails if we don't clear packet register 0x00 before erase.
* The actual reason for the issue is not yet found.
* This issue still needs to be investigated.
*/
XNandPs8_WriteReg(InstancePtr->Config.BaseAddress, 0x00U, 0x0U);
#endif
/*
* Enable Transfer Complete Interrupt in Interrupt Status Enable
* Register

5
XilinxProcessorIPLib/drivers/nandps8_v2_0/src/xnandps8.h
View file

@ -118,7 +118,7 @@
* Ver Who Date Changes
* ----- ---- ---------- -----------------------------------------------
* 1.0 nm 05/06/2014 First release
* 2.0 sb 11/04/2014 Removed Null checks for Buffer passed
* 2.0 sb 12/19/2014 Removed Null checks for Buffer passed
* as parameter to Read API's
* - XNandPs8_Read()
* - XNandPs8_ReadPage
@ -155,6 +155,8 @@
* - XNandPs8_SetEccAddrSize
* ECC address now is calculated based upon the
* size of spare area
* Modified Block Erase API, removed clearing of
* packet register before erase.
* </pre>
*
******************************************************************************/
@ -178,7 +180,6 @@ extern "C" {
#define XNANDPS8_DEBUG
#define RTL_3_1_FIX
#define RTL_3_1_DRIVER_WORKAROUND
#define XNANDPS8_MAX_TARGETS 1U /**< ce_n0, ce_n1 */
#define XNANDPS8_MAX_PKT_SIZE 0x7FFU /**< Max packet size */