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iicps: Modified the i2c according to MISRAC 2012.

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This patch modifies the iicps driver according to MISRAC
2012 and it supports for both Zynq and Alto.

Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
This commit is contained in:
P L Sai Krishna 2015-01-31 19:56:20 +05:30 • committed by Nava kishore Manne
parent 2044e923b0
commit b0b442a12e
11 changed files with 502 additions and 456 deletions
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36
XilinxProcessorIPLib/drivers/iicps/src/xiicps.c
View file

@ -101,7 +101,7 @@ static void StubHandler(void *CallBackRef, u32 StatusEvent);
* @note None. * @note None.
* *
******************************************************************************/ ******************************************************************************/
int XIicPs_CfgInitialize(XIicPs *InstancePtr, XIicPs_Config *ConfigPtr, s32 XIicPs_CfgInitialize(XIicPs *InstancePtr, XIicPs_Config *ConfigPtr,
u32 EffectiveAddr) u32 EffectiveAddr)
{ {
/* /*
@ -119,7 +119,7 @@ int XIicPs_CfgInitialize(XIicPs *InstancePtr, XIicPs_Config *ConfigPtr,
InstancePtr->StatusHandler = StubHandler; InstancePtr->StatusHandler = StubHandler;
InstancePtr->CallBackRef = NULL; InstancePtr->CallBackRef = NULL;
InstancePtr->IsReady = XIL_COMPONENT_IS_READY; InstancePtr->IsReady = (u32)XIL_COMPONENT_IS_READY;
/* /*
* Reset the IIC device to get it into its initial state. It is expected * Reset the IIC device to get it into its initial state. It is expected
@ -136,7 +136,7 @@ int XIicPs_CfgInitialize(XIicPs *InstancePtr, XIicPs_Config *ConfigPtr,
/* Initialize repeated start flag to 0 */ /* Initialize repeated start flag to 0 */
InstancePtr->IsRepeatedStart = 0; InstancePtr->IsRepeatedStart = 0;
return XST_SUCCESS; return (s32)XST_SUCCESS;
} }
/*****************************************************************************/ /*****************************************************************************/
@ -152,17 +152,19 @@ int XIicPs_CfgInitialize(XIicPs *InstancePtr, XIicPs_Config *ConfigPtr,
* @note None. * @note None.
* *
******************************************************************************/ ******************************************************************************/
int XIicPs_BusIsBusy(XIicPs *InstancePtr) s32 XIicPs_BusIsBusy(XIicPs *InstancePtr)
{ {
u32 StatusReg; u32 StatusReg;
s32 Status;
StatusReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress, StatusReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
XIICPS_SR_OFFSET); XIICPS_SR_OFFSET);
if (StatusReg & XIICPS_SR_BA_MASK) { if ((StatusReg & XIICPS_SR_BA_MASK) != 0x0U) {
return TRUE; Status = (s32)TRUE;
}else { }else {
return FALSE; Status = (s32)FALSE;
} }
return Status;
} }
/*****************************************************************************/ /*****************************************************************************/
@ -183,7 +185,7 @@ int XIicPs_BusIsBusy(XIicPs *InstancePtr)
******************************************************************************/ ******************************************************************************/
static void StubHandler(void *CallBackRef, u32 StatusEvent) static void StubHandler(void *CallBackRef, u32 StatusEvent)
{ {
(void) CallBackRef; (void) ((void *)CallBackRef);
(void) StatusEvent; (void) StatusEvent;
Xil_AssertVoidAlways(); Xil_AssertVoidAlways();
} }
@ -208,7 +210,7 @@ void XIicPs_Abort(XIicPs *InstancePtr)
u32 IntrStatusReg; u32 IntrStatusReg;
Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
/* /*
* Enter a critical section, so disable the interrupts while we clear * Enter a critical section, so disable the interrupts while we clear
@ -265,7 +267,7 @@ void XIicPs_Reset(XIicPs *InstancePtr)
{ {
Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
/* /*
* Abort any transfer that is in progress. * Abort any transfer that is in progress.
@ -296,21 +298,21 @@ void XIicPs_Reset(XIicPs *InstancePtr)
* @note This is function is shared by master and slave. * @note This is function is shared by master and slave.
* *
******************************************************************************/ ******************************************************************************/
int TransmitFifoFill(XIicPs *InstancePtr) s32 TransmitFifoFill(XIicPs *InstancePtr)
{ {
u8 AvailBytes; u8 AvailBytes;
int LoopCnt; s32 LoopCnt;
int NumBytesToSend; s32 NumBytesToSend;
/* /*
* Determine number of bytes to write to FIFO. * Determine number of bytes to write to FIFO.
*/ */
AvailBytes = XIICPS_FIFO_DEPTH - AvailBytes = (u8)XIICPS_FIFO_DEPTH -
XIicPs_ReadReg(InstancePtr->Config.BaseAddress, (u8)XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
XIICPS_TRANS_SIZE_OFFSET); XIICPS_TRANS_SIZE_OFFSET);
if (InstancePtr->SendByteCount > AvailBytes) { if (InstancePtr->SendByteCount > (s32)AvailBytes) {
NumBytesToSend = AvailBytes; NumBytesToSend = (s32)AvailBytes;
} else { } else {
NumBytesToSend = InstancePtr->SendByteCount; NumBytesToSend = InstancePtr->SendByteCount;
} }

91
XilinxProcessorIPLib/drivers/iicps/src/xiicps.h
View file

@ -206,10 +206,10 @@ extern "C" {
* *
* @{ * @{
*/ */
#define XIICPS_7_BIT_ADDR_OPTION 0x01 /**< 7-bit address mode */ #define XIICPS_7_BIT_ADDR_OPTION 0x01U /**< 7-bit address mode */
#define XIICPS_10_BIT_ADDR_OPTION 0x02 /**< 10-bit address mode */ #define XIICPS_10_BIT_ADDR_OPTION 0x02U /**< 10-bit address mode */
#define XIICPS_SLAVE_MON_OPTION 0x04 /**< Slave monitor mode */ #define XIICPS_SLAVE_MON_OPTION 0x04U /**< Slave monitor mode */
#define XIICPS_REP_START_OPTION 0x08 /**< Repeated Start */ #define XIICPS_REP_START_OPTION 0x08U /**< Repeated Start */
/*@}*/ /*@}*/
/** @name Callback events /** @name Callback events
@ -220,16 +220,16 @@ extern "C" {
* *
* @{ * @{
*/ */
#define XIICPS_EVENT_COMPLETE_SEND 0x0001 /**< Transmit Complete Event*/ #define XIICPS_EVENT_COMPLETE_SEND 0x0001U /**< Transmit Complete Event*/
#define XIICPS_EVENT_COMPLETE_RECV 0x0002 /**< Receive Complete Event*/ #define XIICPS_EVENT_COMPLETE_RECV 0x0002U /**< Receive Complete Event*/
#define XIICPS_EVENT_TIME_OUT 0x0004 /**< Transfer timed out */ #define XIICPS_EVENT_TIME_OUT 0x0004U /**< Transfer timed out */
#define XIICPS_EVENT_ERROR 0x0008 /**< Receive error */ #define XIICPS_EVENT_ERROR 0x0008U /**< Receive error */
#define XIICPS_EVENT_ARB_LOST 0x0010 /**< Arbitration lost */ #define XIICPS_EVENT_ARB_LOST 0x0010U /**< Arbitration lost */
#define XIICPS_EVENT_NACK 0x0020 /**< NACK Received */ #define XIICPS_EVENT_NACK 0x0020U /**< NACK Received */
#define XIICPS_EVENT_SLAVE_RDY 0x0040 /**< Slave ready */ #define XIICPS_EVENT_SLAVE_RDY 0x0040U /**< Slave ready */
#define XIICPS_EVENT_RX_OVR 0x0080 /**< RX overflow */ #define XIICPS_EVENT_RX_OVR 0x0080U /**< RX overflow */
#define XIICPS_EVENT_TX_OVR 0x0100 /**< TX overflow */ #define XIICPS_EVENT_TX_OVR 0x0100U /**< TX overflow */
#define XIICPS_EVENT_RX_UNF 0x0200 /**< RX underflow */ #define XIICPS_EVENT_RX_UNF 0x0200U /**< RX underflow */
/*@}*/ /*@}*/
/** @name Role constants /** @name Role constants
@ -241,7 +241,7 @@ extern "C" {
#define RECVING_ROLE 0 /**< Transfer direction is receiving */ #define RECVING_ROLE 0 /**< Transfer direction is receiving */
/* Maximum transfer size */ /* Maximum transfer size */
#define XIICPS_MAX_TRANSFER_SIZE (255 - 3) #define XIICPS_MAX_TRANSFER_SIZE (u32)(255U - 3U)
/**************************** Type Definitions *******************************/ /**************************** Type Definitions *******************************/
@ -279,13 +279,13 @@ typedef struct {
u8 *SendBufferPtr; /* Pointer to send buffer */ u8 *SendBufferPtr; /* Pointer to send buffer */
u8 *RecvBufferPtr; /* Pointer to recv buffer */ u8 *RecvBufferPtr; /* Pointer to recv buffer */
int SendByteCount; /* Number of bytes still expected to send */ s32 SendByteCount; /* Number of bytes still expected to send */
int RecvByteCount; /* Number of bytes still expected to receive */ s32 RecvByteCount; /* Number of bytes still expected to receive */
int CurrByteCount; /* No. of bytes expected in current transfer */ s32 CurrByteCount; /* No. of bytes expected in current transfer */
int UpdateTxSize; /* If tx size register has to be updated */ s32 UpdateTxSize; /* If tx size register has to be updated */
int IsSend; /* Whether master is sending or receiving */ s32 IsSend; /* Whether master is sending or receiving */
int IsRepeatedStart; /* Indicates if user set repeated start */ s32 IsRepeatedStart; /* Indicates if user set repeated start */
XIicPs_IntrHandler StatusHandler; /* Event handler function */ XIicPs_IntrHandler StatusHandler; /* Event handler function */
void *CallBackRef; /* Callback reference for event handler */ void *CallBackRef; /* Callback reference for event handler */
@ -307,10 +307,13 @@ typedef struct {
*****************************************************************************/ *****************************************************************************/
#define XIicPs_SendByte(InstancePtr) \ #define XIicPs_SendByte(InstancePtr) \
{ \ { \
u8 Data; \
Data = *((InstancePtr)->SendBufferPtr); \
XIicPs_Out32((InstancePtr)->Config.BaseAddress \ XIicPs_Out32((InstancePtr)->Config.BaseAddress \
+ XIICPS_DATA_OFFSET, \ + (u32)(XIICPS_DATA_OFFSET), \
*(InstancePtr)->SendBufferPtr ++); \ (u32)(Data)); \
(InstancePtr)->SendByteCount --; \ (InstancePtr)->SendBufferPtr += 1; \
(InstancePtr)->SendByteCount -= 1;\
} }
/****************************************************************************/ /****************************************************************************/
@ -328,9 +331,12 @@ typedef struct {
*****************************************************************************/ *****************************************************************************/
#define XIicPs_RecvByte(InstancePtr) \ #define XIicPs_RecvByte(InstancePtr) \
{ \ { \
*(InstancePtr)->RecvBufferPtr ++ = \ u8 *Data, Value; \
(u8)XIicPs_In32((InstancePtr)->Config.BaseAddress \ Value = (u8)(XIicPs_In32((InstancePtr)->Config.BaseAddress \
+ XIICPS_DATA_OFFSET); \ + (u32)XIICPS_DATA_OFFSET)); \
Data = &Value; \
*(InstancePtr)->RecvBufferPtr = *Data; \
(InstancePtr)->RecvBufferPtr += 1; \
(InstancePtr)->RecvByteCount --; \ (InstancePtr)->RecvByteCount --; \
} }
@ -344,30 +350,31 @@ XIicPs_Config *XIicPs_LookupConfig(u16 DeviceId);
/* /*
* Functions for general setup, in xiicps.c * Functions for general setup, in xiicps.c
*/ */
int XIicPs_CfgInitialize(XIicPs *InstancePtr, XIicPs_Config * Config, s32 XIicPs_CfgInitialize(XIicPs *InstancePtr, XIicPs_Config * ConfigPtr,
u32 EffectiveAddr); u32 EffectiveAddr);
void XIicPs_Abort(XIicPs *InstancePtr); void XIicPs_Abort(XIicPs *InstancePtr);
void XIicPs_Reset(XIicPs *InstancePtr); void XIicPs_Reset(XIicPs *InstancePtr);
int XIicPs_BusIsBusy(XIicPs *InstancePtr); s32 XIicPs_BusIsBusy(XIicPs *InstancePtr);
s32 TransmitFifoFill(XIicPs *InstancePtr);
/* /*
* Functions for interrupts, in xiicps_intr.c * Functions for interrupts, in xiicps_intr.c
*/ */
void XIicPs_SetStatusHandler(XIicPs *InstancePtr, void *CallBackRef, void XIicPs_SetStatusHandler(XIicPs *InstancePtr, void *CallBackRef,
XIicPs_IntrHandler FuncPtr); XIicPs_IntrHandler FunctionPtr);
/* /*
* Functions for device as master, in xiicps_master.c * Functions for device as master, in xiicps_master.c
*/ */
void XIicPs_MasterSend(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount, void XIicPs_MasterSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
u16 SlaveAddr); u16 SlaveAddr);
void XIicPs_MasterRecv(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount, void XIicPs_MasterRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
u16 SlaveAddr); u16 SlaveAddr);
int XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount, s32 XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
u16 SlaveAddr); u16 SlaveAddr);
int XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount, s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
u16 SlaveAddr); u16 SlaveAddr);
void XIicPs_EnableSlaveMonitor(XIicPs *InstancePtr, u16 SlaveAddr); void XIicPs_EnableSlaveMonitor(XIicPs *InstancePtr, u16 SlaveAddr);
void XIicPs_DisableSlaveMonitor(XIicPs *InstancePtr); void XIicPs_DisableSlaveMonitor(XIicPs *InstancePtr);
@ -377,25 +384,25 @@ void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr);
* Functions for device as slave, in xiicps_slave.c * Functions for device as slave, in xiicps_slave.c
*/ */
void XIicPs_SetupSlave(XIicPs *InstancePtr, u16 SlaveAddr); void XIicPs_SetupSlave(XIicPs *InstancePtr, u16 SlaveAddr);
void XIicPs_SlaveSend(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount); void XIicPs_SlaveSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
void XIicPs_SlaveRecv(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount); void XIicPs_SlaveRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
int XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount); s32 XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
int XIicPs_SlaveRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount); s32 XIicPs_SlaveRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
void XIicPs_SlaveInterruptHandler(XIicPs *InstancePtr); void XIicPs_SlaveInterruptHandler(XIicPs *InstancePtr);
/* /*
* Functions for selftest, in xiicps_selftest.c * Functions for selftest, in xiicps_selftest.c
*/ */
int XIicPs_SelfTest(XIicPs *InstancePtr); s32 XIicPs_SelfTest(XIicPs *InstancePtr);
/* /*
* Functions for setting and getting data rate, in xiicps_options.c * Functions for setting and getting data rate, in xiicps_options.c
*/ */
int XIicPs_SetOptions(XIicPs *InstancePtr, u32 Options); s32 XIicPs_SetOptions(XIicPs *InstancePtr, u32 Options);
int XIicPs_ClearOptions(XIicPs *InstancePtr, u32 Options); s32 XIicPs_ClearOptions(XIicPs *InstancePtr, u32 Options);
u32 XIicPs_GetOptions(XIicPs *InstancePtr); u32 XIicPs_GetOptions(XIicPs *InstancePtr);
int XIicPs_SetSClk(XIicPs *InstancePtr, u32 FsclHz); s32 XIicPs_SetSClk(XIicPs *InstancePtr, u32 FsclHz);
u32 XIicPs_GetSClk(XIicPs *InstancePtr); u32 XIicPs_GetSClk(XIicPs *InstancePtr);
#ifdef __cplusplus #ifdef __cplusplus

15
XilinxProcessorIPLib/drivers/iicps/src/xiicps_g.c
View file

@ -49,8 +49,9 @@
******************************************************************************/ ******************************************************************************/
/***************************** Include Files *********************************/ /***************************** Include Files *********************************/
#include "xparameters.h"
#include "xiicps.h" #include "xiicps.h"
#include "xparameters.h"
/************************** Constant Definitions *****************************/ /************************** Constant Definitions *****************************/
@ -72,15 +73,15 @@
*/ */
XIicPs_Config XIicPs_ConfigTable[XPAR_XIICPS_NUM_INSTANCES] = { XIicPs_Config XIicPs_ConfigTable[XPAR_XIICPS_NUM_INSTANCES] = {
{ {
XPAR_XIICPS_0_DEVICE_ID, /* Device ID for instance */ (u16)XPAR_XIICPS_0_DEVICE_ID, /* Device ID for instance */
XPAR_XIICPS_0_BASEADDR, /* Device base address */ (u32)XPAR_XIICPS_0_BASEADDR, /* Device base address */
XPAR_XIICPS_0_I2C_CLK_FREQ_HZ /* Device input clock frequency */ (u32)XPAR_XIICPS_0_I2C_CLK_FREQ_HZ /* Device input clock frequency */
}, },
#ifdef XPAR_XIICPS_1_DEVICE_ID #ifdef XPAR_XIICPS_1_DEVICE_ID
{ {
XPAR_XIICPS_1_DEVICE_ID, /* Device ID for instance */ (u16)XPAR_XIICPS_1_DEVICE_ID, /* Device ID for instance */
XPAR_XIICPS_1_BASEADDR, /* Device base address */ (u32)XPAR_XIICPS_1_BASEADDR, /* Device base address */
XPAR_XIICPS_1_CLOCK_HZ /* Device input clock frequency */ (u32)XPAR_XIICPS_1_CLOCK_HZ /* Device input clock frequency */
} }
#endif #endif
}; };

4
XilinxProcessorIPLib/drivers/iicps/src/xiicps_hw.c
View file

@ -98,11 +98,11 @@ void XIicPs_ResetHw(u32 BaseAddress)
/* Clear the timeout register */ /* Clear the timeout register */
XIicPs_WriteReg(BaseAddress, XIICPS_TIME_OUT_OFFSET, XIICPS_TO_RESET_VALUE); XIicPs_WriteReg(BaseAddress, XIICPS_TIME_OUT_OFFSET, XIICPS_TO_RESET_VALUE);
/* Clear the transfer size register */ /* Clear the transfer size register */
XIicPs_WriteReg(BaseAddress, XIICPS_TRANS_SIZE_OFFSET, 0x0); XIicPs_WriteReg(BaseAddress, XIICPS_TRANS_SIZE_OFFSET, 0x0U);
/* Clear the status register */ /* Clear the status register */
RegVal = XIicPs_ReadReg(BaseAddress,XIICPS_SR_OFFSET); RegVal = XIicPs_ReadReg(BaseAddress,XIICPS_SR_OFFSET);
XIicPs_WriteReg(BaseAddress, XIICPS_SR_OFFSET, RegVal); XIicPs_WriteReg(BaseAddress, XIICPS_SR_OFFSET, RegVal);
/* Update the configuraqtion register with reset value */ /* Update the configuraqtion register with reset value */
XIicPs_WriteReg(BaseAddress, XIICPS_CR_OFFSET, 0x0); XIicPs_WriteReg(BaseAddress, XIICPS_CR_OFFSET, 0x0U);
} }

118
XilinxProcessorIPLib/drivers/iicps/src/xiicps_hw.h
View file

@ -69,17 +69,17 @@ extern "C" {
* Register offsets for the IIC. * Register offsets for the IIC.
* @{ * @{
*/ */
#define XIICPS_CR_OFFSET 0x00 /**< 32-bit Control */ #define XIICPS_CR_OFFSET 0x00U /**< 32-bit Control */
#define XIICPS_SR_OFFSET 0x04 /**< Status */ #define XIICPS_SR_OFFSET 0x04U /**< Status */
#define XIICPS_ADDR_OFFSET 0x08 /**< IIC Address */ #define XIICPS_ADDR_OFFSET 0x08U /**< IIC Address */
#define XIICPS_DATA_OFFSET 0x0C /**< IIC FIFO Data */ #define XIICPS_DATA_OFFSET 0x0CU /**< IIC FIFO Data */
#define XIICPS_ISR_OFFSET 0x10 /**< Interrupt Status */ #define XIICPS_ISR_OFFSET 0x10U /**< Interrupt Status */
#define XIICPS_TRANS_SIZE_OFFSET 0x14 /**< Transfer Size */ #define XIICPS_TRANS_SIZE_OFFSET 0x14U /**< Transfer Size */
#define XIICPS_SLV_PAUSE_OFFSET 0x18 /**< Slave monitor pause */ #define XIICPS_SLV_PAUSE_OFFSET 0x18U /**< Slave monitor pause */
#define XIICPS_TIME_OUT_OFFSET 0x1C /**< Time Out */ #define XIICPS_TIME_OUT_OFFSET 0x1CU /**< Time Out */
#define XIICPS_IMR_OFFSET 0x20 /**< Interrupt Enabled Mask */ #define XIICPS_IMR_OFFSET 0x20U /**< Interrupt Enabled Mask */
#define XIICPS_IER_OFFSET 0x24 /**< Interrupt Enable */ #define XIICPS_IER_OFFSET 0x24U /**< Interrupt Enable */
#define XIICPS_IDR_OFFSET 0x28 /**< Interrupt Disable */ #define XIICPS_IDR_OFFSET 0x28U /**< Interrupt Disable */
/* @} */ /* @} */
/** @name Control Register /** @name Control Register
@ -89,26 +89,26 @@ extern "C" {
* @{ * @{
*/ */
#define XIICPS_CR_DIV_A_MASK 0x0000C000 /**< Clock Divisor A */ #define XIICPS_CR_DIV_A_MASK 0x0000C000U /**< Clock Divisor A */
#define XIICPS_CR_DIV_A_SHIFT 14 /**< Clock Divisor A shift */ #define XIICPS_CR_DIV_A_SHIFT 14U /**< Clock Divisor A shift */
#define XIICPS_DIV_A_MAX 4 /**< Maximum value of Divisor A */ #define XIICPS_DIV_A_MAX 4U /**< Maximum value of Divisor A */
#define XIICPS_CR_DIV_B_MASK 0x00003F00 /**< Clock Divisor B */ #define XIICPS_CR_DIV_B_MASK 0x00003F00U /**< Clock Divisor B */
#define XIICPS_CR_DIV_B_SHIFT 8 /**< Clock Divisor B shift */ #define XIICPS_CR_DIV_B_SHIFT 8U /**< Clock Divisor B shift */
#define XIICPS_CR_CLR_FIFO_MASK 0x00000040 /**< Clear FIFO, auto clears*/ #define XIICPS_CR_CLR_FIFO_MASK 0x00000040U /**< Clear FIFO, auto clears*/
#define XIICPS_CR_SLVMON_MASK 0x00000020 /**< Slave monitor mode */ #define XIICPS_CR_SLVMON_MASK 0x00000020U /**< Slave monitor mode */
#define XIICPS_CR_HOLD_MASK 0x00000010 /**< Hold bus 1=Hold scl, #define XIICPS_CR_HOLD_MASK 0x00000010U /**< Hold bus 1=Hold scl,
0=terminate transfer */ 0=terminate transfer */
#define XIICPS_CR_ACKEN_MASK 0x00000008 /**< Enable TX of ACK when #define XIICPS_CR_ACKEN_MASK 0x00000008U /**< Enable TX of ACK when
Master receiver*/ Master receiver*/
#define XIICPS_CR_NEA_MASK 0x00000004 /**< Addressing Mode 1=7 bit, #define XIICPS_CR_NEA_MASK 0x00000004U /**< Addressing Mode 1=7 bit,
0=10 bit */ 0=10 bit */
#define XIICPS_CR_MS_MASK 0x00000002 /**< Master mode bit 1=Master, #define XIICPS_CR_MS_MASK 0x00000002U /**< Master mode bit 1=Master,
0=Slave */ 0=Slave */
#define XIICPS_CR_RD_WR_MASK 0x00000001 /**< Read or Write Master #define XIICPS_CR_RD_WR_MASK 0x00000001U /**< Read or Write Master
transfer 0=Transmitter, transfer 0=Transmitter,
1=Receiver*/ 1=Receiver*/
#define XIICPS_CR_RESET_VALUE 0 /**< Reset value of the Control #define XIICPS_CR_RESET_VALUE 0U /**< Reset value of the Control
register */ register */
/* @} */ /* @} */
/** @name IIC Status Register /** @name IIC Status Register
@ -116,11 +116,11 @@ extern "C" {
* This register is used to indicate status of the IIC controller. Read only * This register is used to indicate status of the IIC controller. Read only
* @{ * @{
*/ */
#define XIICPS_SR_BA_MASK 0x00000100 /**< Bus Active Mask */ #define XIICPS_SR_BA_MASK 0x00000100U /**< Bus Active Mask */
#define XIICPS_SR_RXOVF_MASK 0x00000080 /**< Receiver Overflow Mask */ #define XIICPS_SR_RXOVF_MASK 0x00000080U /**< Receiver Overflow Mask */
#define XIICPS_SR_TXDV_MASK 0x00000040 /**< Transmit Data Valid Mask */ #define XIICPS_SR_TXDV_MASK 0x00000040U /**< Transmit Data Valid Mask */
#define XIICPS_SR_RXDV_MASK 0x00000020 /**< Receiver Data Valid Mask */ #define XIICPS_SR_RXDV_MASK 0x00000020U /**< Receiver Data Valid Mask */
#define XIICPS_SR_RXRW_MASK 0x00000008 /**< Receive read/write Mask */ #define XIICPS_SR_RXRW_MASK 0x00000008U /**< Receive read/write Mask */
/* @} */ /* @} */
/** @name IIC Address Register /** @name IIC Address Register
@ -179,24 +179,24 @@ extern "C" {
* @{ * @{
*/ */
#define XIICPS_IXR_ARB_LOST_MASK 0x00000200 /**< Arbitration Lost Interrupt #define XIICPS_IXR_ARB_LOST_MASK 0x00000200U /**< Arbitration Lost Interrupt
mask */ mask */
#define XIICPS_IXR_RX_UNF_MASK 0x00000080 /**< FIFO Recieve Underflow #define XIICPS_IXR_RX_UNF_MASK 0x00000080U /**< FIFO Recieve Underflow
Interrupt mask */ Interrupt mask */
#define XIICPS_IXR_TX_OVR_MASK 0x00000040 /**< Transmit Overflow #define XIICPS_IXR_TX_OVR_MASK 0x00000040U /**< Transmit Overflow
Interrupt mask */ Interrupt mask */
#define XIICPS_IXR_RX_OVR_MASK 0x00000020 /**< Receive Overflow Interrupt #define XIICPS_IXR_RX_OVR_MASK 0x00000020U /**< Receive Overflow Interrupt
mask */ mask */
#define XIICPS_IXR_SLV_RDY_MASK 0x00000010 /**< Monitored Slave Ready #define XIICPS_IXR_SLV_RDY_MASK 0x00000010U /**< Monitored Slave Ready
Interrupt mask */ Interrupt mask */
#define XIICPS_IXR_TO_MASK 0x00000008 /**< Transfer Time Out #define XIICPS_IXR_TO_MASK 0x00000008U /**< Transfer Time Out
Interrupt mask */ Interrupt mask */
#define XIICPS_IXR_NACK_MASK 0x00000004 /**< NACK Interrupt mask */ #define XIICPS_IXR_NACK_MASK 0x00000004U /**< NACK Interrupt mask */
#define XIICPS_IXR_DATA_MASK 0x00000002 /**< Data Interrupt mask */ #define XIICPS_IXR_DATA_MASK 0x00000002U /**< Data Interrupt mask */
#define XIICPS_IXR_COMP_MASK 0x00000001 /**< Transfer Complete #define XIICPS_IXR_COMP_MASK 0x00000001U /**< Transfer Complete
Interrupt mask */ Interrupt mask */
#define XIICPS_IXR_DEFAULT_MASK 0x000002FF /**< Default ISR Mask */ #define XIICPS_IXR_DEFAULT_MASK 0x000002FFU /**< Default ISR Mask */
#define XIICPS_IXR_ALL_INTR_MASK 0x000002FF /**< All ISR Mask */ #define XIICPS_IXR_ALL_INTR_MASK 0x000002FFU /**< All ISR Mask */
/* @} */ /* @} */
@ -253,8 +253,8 @@ extern "C" {
* Read/Write * Read/Write
* @{ * @{
*/ */
#define XIICPS_TIME_OUT_MASK 0x000000FF /**< IIC Time Out mask */ #define XIICPS_TIME_OUT_MASK 0x000000FFU /**< IIC Time Out mask */
#define XIICPS_TO_RESET_VALUE 0x000000FF /**< IIC Time Out reset value */ #define XIICPS_TO_RESET_VALUE 0x000000FFU /**< IIC Time Out reset value */
/* @} */ /* @} */
/**************************** Type Definitions *******************************/ /**************************** Type Definitions *******************************/
@ -279,7 +279,7 @@ extern "C" {
* *
******************************************************************************/ ******************************************************************************/
#define XIicPs_ReadReg(BaseAddress, RegOffset) \ #define XIicPs_ReadReg(BaseAddress, RegOffset) \
XIicPs_In32((BaseAddress) + (RegOffset)) XIicPs_In32((BaseAddress) + (u32)(RegOffset))
/***************************************************************************/ /***************************************************************************/
/** /**
@ -297,7 +297,7 @@ extern "C" {
* *
******************************************************************************/ ******************************************************************************/
#define XIicPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \ #define XIicPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
XIicPs_Out32((BaseAddress) + (RegOffset), (RegisterValue)) XIicPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))
/***************************************************************************/ /***************************************************************************/
/** /**
@ -371,7 +371,7 @@ extern "C" {
/* /*
* Perform reset operation to the I2c interface * Perform reset operation to the I2c interface
*/ */
void XIicPs_ResetHw(u32 BaseAddr); void XIicPs_ResetHw(u32 BaseAddress);
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

8
XilinxProcessorIPLib/drivers/iicps/src/xiicps_intr.c
View file

@ -86,12 +86,12 @@
* *
******************************************************************************/ ******************************************************************************/
void XIicPs_SetStatusHandler(XIicPs *InstancePtr, void *CallBackRef, void XIicPs_SetStatusHandler(XIicPs *InstancePtr, void *CallBackRef,
XIicPs_IntrHandler FuncPtr) XIicPs_IntrHandler FunctionPtr)
{ {
Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(FuncPtr != NULL); Xil_AssertVoid(FunctionPtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
InstancePtr->StatusHandler = FuncPtr; InstancePtr->StatusHandler = FunctionPtr;
InstancePtr->CallBackRef = CallBackRef; InstancePtr->CallBackRef = CallBackRef;
} }

312
XilinxProcessorIPLib/drivers/iicps/src/xiicps_master.c
View file

@ -73,9 +73,9 @@
/***************** Macros (Inline Functions) Definitions *********************/ /***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/ /************************** Function Prototypes ******************************/
int TransmitFifoFill(XIicPs *InstancePtr); s32 TransmitFifoFill(XIicPs *InstancePtr);
static int XIicPs_SetupMaster(XIicPs *InstancePtr, int Role); static s32 XIicPs_SetupMaster(XIicPs *InstancePtr, s32 Role);
static void MasterSendData(XIicPs *InstancePtr); static void MasterSendData(XIicPs *InstancePtr);
/************************* Variable Definitions *****************************/ /************************* Variable Definitions *****************************/
@ -97,7 +97,7 @@ static void MasterSendData(XIicPs *InstancePtr);
* @note This send routine is for interrupt-driven transfer only. * @note This send routine is for interrupt-driven transfer only.
* *
****************************************************************************/ ****************************************************************************/
void XIicPs_MasterSend(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount, void XIicPs_MasterSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
u16 SlaveAddr) u16 SlaveAddr)
{ {
u32 BaseAddr; u32 BaseAddr;
@ -107,7 +107,7 @@ void XIicPs_MasterSend(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount,
*/ */
Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(MsgPtr != NULL); Xil_AssertVoid(MsgPtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
Xil_AssertVoid(XIICPS_ADDR_MASK >= SlaveAddr); Xil_AssertVoid(XIICPS_ADDR_MASK >= SlaveAddr);
@ -120,28 +120,28 @@ void XIicPs_MasterSend(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount,
/* /*
* Set repeated start if sending more than FIFO of data. * Set repeated start if sending more than FIFO of data.
*/ */
if ((InstancePtr->IsRepeatedStart) || if (((InstancePtr->IsRepeatedStart) != 0)||
(ByteCount > XIICPS_FIFO_DEPTH)) { ((ByteCount > XIICPS_FIFO_DEPTH) != 0U)) {
XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, XIicPs_WriteReg(BaseAddr, (u32)XIICPS_CR_OFFSET,
XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET) | XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) |
XIICPS_CR_HOLD_MASK); (u32)XIICPS_CR_HOLD_MASK);
} }
/* /*
* Setup as a master sending role. * Setup as a master sending role.
*/ */
XIicPs_SetupMaster(InstancePtr, SENDING_ROLE); (void)XIicPs_SetupMaster(InstancePtr, SENDING_ROLE);
TransmitFifoFill(InstancePtr); (void)TransmitFifoFill(InstancePtr);
/* /*
* Do the address transfer to notify the slave. * Do the address transfer to notify the slave.
*/ */
XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr); XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
XIicPs_EnableInterrupts(BaseAddr, XIicPs_EnableInterrupts(BaseAddr,
XIICPS_IXR_NACK_MASK | XIICPS_IXR_COMP_MASK | (u32)XIICPS_IXR_NACK_MASK | (u32)XIICPS_IXR_COMP_MASK |
XIICPS_IXR_ARB_LOST_MASK); (u32)XIICPS_IXR_ARB_LOST_MASK);
} }
/*****************************************************************************/ /*****************************************************************************/
@ -161,7 +161,7 @@ void XIicPs_MasterSend(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount,
* @note This receive routine is for interrupt-driven transfer only. * @note This receive routine is for interrupt-driven transfer only.
* *
****************************************************************************/ ****************************************************************************/
void XIicPs_MasterRecv(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount, void XIicPs_MasterRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
u16 SlaveAddr) u16 SlaveAddr)
{ {
u32 BaseAddr; u32 BaseAddr;
@ -171,7 +171,7 @@ void XIicPs_MasterRecv(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount,
*/ */
Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(MsgPtr != NULL); Xil_AssertVoid(MsgPtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
Xil_AssertVoid(XIICPS_ADDR_MASK >= SlaveAddr); Xil_AssertVoid(XIICPS_ADDR_MASK >= SlaveAddr);
BaseAddr = InstancePtr->Config.BaseAddress; BaseAddr = InstancePtr->Config.BaseAddress;
@ -183,22 +183,22 @@ void XIicPs_MasterRecv(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount,
InstancePtr->UpdateTxSize = 0; InstancePtr->UpdateTxSize = 0;
if ((ByteCount > XIICPS_FIFO_DEPTH) || if ((ByteCount > XIICPS_FIFO_DEPTH) ||
(InstancePtr->IsRepeatedStart)) ((InstancePtr->IsRepeatedStart) !=0))
{ {
XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET) | XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) |
XIICPS_CR_HOLD_MASK); (u32)XIICPS_CR_HOLD_MASK);
} }
/* /*
* Initialize for a master receiving role. * Initialize for a master receiving role.
*/ */
XIicPs_SetupMaster(InstancePtr, RECVING_ROLE); (void)XIicPs_SetupMaster(InstancePtr, RECVING_ROLE);
/* /*
* Do the address transfer to signal the slave. * Do the address transfer to signal the slave.
*/ */
XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr); XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
/* /*
* Setup the transfer size register so the slave knows how much * Setup the transfer size register so the slave knows how much
@ -207,17 +207,17 @@ void XIicPs_MasterRecv(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount,
if (ByteCount > XIICPS_MAX_TRANSFER_SIZE) { if (ByteCount > XIICPS_MAX_TRANSFER_SIZE) {
XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET, XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET,
XIICPS_MAX_TRANSFER_SIZE); XIICPS_MAX_TRANSFER_SIZE);
InstancePtr->CurrByteCount = XIICPS_MAX_TRANSFER_SIZE; InstancePtr->CurrByteCount = (s32)XIICPS_MAX_TRANSFER_SIZE;
InstancePtr->UpdateTxSize = 1; InstancePtr->UpdateTxSize = 1;
}else { }else {
XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET, XIicPs_WriteReg(BaseAddr, (u32)(XIICPS_TRANS_SIZE_OFFSET),
ByteCount); (u32)ByteCount);
} }
XIicPs_EnableInterrupts(BaseAddr, XIicPs_EnableInterrupts(BaseAddr,
XIICPS_IXR_NACK_MASK | XIICPS_IXR_DATA_MASK | (u32)XIICPS_IXR_NACK_MASK | (u32)XIICPS_IXR_DATA_MASK |
XIICPS_IXR_RX_OVR_MASK | XIICPS_IXR_COMP_MASK | (u32)XIICPS_IXR_RX_OVR_MASK | (u32)XIICPS_IXR_COMP_MASK |
XIICPS_IXR_ARB_LOST_MASK); (u32)XIICPS_IXR_ARB_LOST_MASK);
} }
/*****************************************************************************/ /*****************************************************************************/
@ -240,40 +240,42 @@ void XIicPs_MasterRecv(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount,
* @note This send routine is for polled mode transfer only. * @note This send routine is for polled mode transfer only.
* *
****************************************************************************/ ****************************************************************************/
int XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr,
int ByteCount, u16 SlaveAddr) s32 ByteCount, u16 SlaveAddr)
{ {
u32 IntrStatusReg; u32 IntrStatusReg;
u32 StatusReg; u32 StatusReg;
u32 BaseAddr; u32 BaseAddr;
u32 Intrs; u32 Intrs;
u32 Value;
s32 Status;
/* /*
* Assert validates the input arguments. * Assert validates the input arguments.
*/ */
Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(MsgPtr != NULL); Xil_AssertNonvoid(MsgPtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(XIICPS_ADDR_MASK >= SlaveAddr); Xil_AssertNonvoid(XIICPS_ADDR_MASK >= SlaveAddr);
BaseAddr = InstancePtr->Config.BaseAddress; BaseAddr = InstancePtr->Config.BaseAddress;
InstancePtr->SendBufferPtr = MsgPtr; InstancePtr->SendBufferPtr = MsgPtr;
InstancePtr->SendByteCount = ByteCount; InstancePtr->SendByteCount = ByteCount;
if ((InstancePtr->IsRepeatedStart) || if (((InstancePtr->IsRepeatedStart) != 0) ||
(ByteCount > XIICPS_FIFO_DEPTH)) { ((ByteCount > XIICPS_FIFO_DEPTH) != 0U)) {
XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET) | XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) |
XIICPS_CR_HOLD_MASK); (u32)XIICPS_CR_HOLD_MASK);
} }
XIicPs_SetupMaster(InstancePtr, SENDING_ROLE); (void)XIicPs_SetupMaster(InstancePtr, SENDING_ROLE);
/* /*
* Intrs keeps all the error-related interrupts. * Intrs keeps all the error-related interrupts.
*/ */
Intrs = XIICPS_IXR_ARB_LOST_MASK | XIICPS_IXR_TX_OVR_MASK | Intrs = (u32)XIICPS_IXR_ARB_LOST_MASK | (u32)XIICPS_IXR_TX_OVR_MASK |
XIICPS_IXR_NACK_MASK; (u32)XIICPS_IXR_NACK_MASK;
/* /*
* Clear the interrupt status register before use it to monitor. * Clear the interrupt status register before use it to monitor.
@ -284,9 +286,9 @@ int XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr,
/* /*
* Transmit first FIFO full of data. * Transmit first FIFO full of data.
*/ */
TransmitFifoFill(InstancePtr); (void)TransmitFifoFill(InstancePtr);
XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr); XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET); IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
@ -294,23 +296,28 @@ int XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr,
* Continue sending as long as there is more data and * Continue sending as long as there is more data and
* there are no errors. * there are no errors.
*/ */
while ((InstancePtr->SendByteCount > 0) && Value = ((InstancePtr->SendByteCount > (s32)0) &&
((IntrStatusReg & Intrs) == 0)) { ((IntrStatusReg & Intrs) == (u32)0U));
while (Value != (u32)0x00U) {
StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET); StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
/* /*
* Wait until transmit FIFO is empty. * Wait until transmit FIFO is empty.
*/ */
if ((StatusReg & XIICPS_SR_TXDV_MASK) != 0) { if ((StatusReg & XIICPS_SR_TXDV_MASK) != 0U) {
IntrStatusReg = XIicPs_ReadReg(BaseAddr, IntrStatusReg = XIicPs_ReadReg(BaseAddr,
XIICPS_ISR_OFFSET); XIICPS_ISR_OFFSET);
Value = ((InstancePtr->SendByteCount > (s32)0) &&
((IntrStatusReg & Intrs) == (u32)0U));
continue; continue;
} }
/* /*
* Send more data out through transmit FIFO. * Send more data out through transmit FIFO.
*/ */
TransmitFifoFill(InstancePtr); (void)TransmitFifoFill(InstancePtr);
Value = ((InstancePtr->SendByteCount > (s32)0) &&
((IntrStatusReg & Intrs) == (u32)0U));
} }
/* /*
@ -322,18 +329,18 @@ int XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr,
/* /*
* If there is an error, tell the caller. * If there is an error, tell the caller.
*/ */
if ((IntrStatusReg & Intrs) != 0) { if ((IntrStatusReg & Intrs) != 0U) {
return XST_FAILURE; return (s32)XST_FAILURE;
} }
} }
if (!(InstancePtr->IsRepeatedStart)) { if ((!(InstancePtr->IsRepeatedStart)) != 0) {
XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
XIicPs_ReadReg(BaseAddr,XIICPS_CR_OFFSET) & XIicPs_ReadReg(BaseAddr,XIICPS_CR_OFFSET) &
(~XIICPS_CR_HOLD_MASK)); (~XIICPS_CR_HOLD_MASK));
} }
return XST_SUCCESS; return (s32)XST_SUCCESS;
} }
/*****************************************************************************/ /*****************************************************************************/
@ -356,38 +363,46 @@ int XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr,
* @note This receive routine is for polled mode transfer only. * @note This receive routine is for polled mode transfer only.
* *
****************************************************************************/ ****************************************************************************/
int XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr,
int ByteCount, u16 SlaveAddr) s32 ByteCount, u16 SlaveAddr)
{ {
u32 IntrStatusReg; u32 IntrStatusReg;
u32 Intrs; u32 Intrs;
u32 StatusReg; u32 StatusReg;
u32 BaseAddr; u32 BaseAddr;
int IsHold = 0; s32 BytesToRecv;
int UpdateTxSize = 0; s32 BytesToRead;
s32 TransSize;
s32 Tmp = 0;
u32 Status_Rcv;
u32 Status;
s32 Result;
s32 IsHold = 0;
s32 UpdateTxSize = 0;
s32 ByteCountVar = ByteCount;
/* /*
* Assert validates the input arguments. * Assert validates the input arguments.
*/ */
Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(MsgPtr != NULL); Xil_AssertNonvoid(MsgPtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(XIICPS_ADDR_MASK >= SlaveAddr); Xil_AssertNonvoid(XIICPS_ADDR_MASK >= SlaveAddr);
BaseAddr = InstancePtr->Config.BaseAddress; BaseAddr = InstancePtr->Config.BaseAddress;
InstancePtr->RecvBufferPtr = MsgPtr; InstancePtr->RecvBufferPtr = MsgPtr;
InstancePtr->RecvByteCount = ByteCount; InstancePtr->RecvByteCount = ByteCountVar;
if((ByteCount > XIICPS_FIFO_DEPTH) || if((ByteCountVar > XIICPS_FIFO_DEPTH) ||
(InstancePtr->IsRepeatedStart)) ((InstancePtr->IsRepeatedStart) !=0))
{ {
XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET) | XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) |
XIICPS_CR_HOLD_MASK); (u32)XIICPS_CR_HOLD_MASK);
IsHold = 1; IsHold = 1;
} }
XIicPs_SetupMaster(InstancePtr, RECVING_ROLE); (void)XIicPs_SetupMaster(InstancePtr, RECVING_ROLE);
/* /*
* Clear the interrupt status register before use it to monitor. * Clear the interrupt status register before use it to monitor.
@ -401,34 +416,33 @@ int XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr,
* Set up the transfer size register so the slave knows how much * Set up the transfer size register so the slave knows how much
* to send to us. * to send to us.
*/ */
if (ByteCount > XIICPS_MAX_TRANSFER_SIZE) { if (ByteCountVar > XIICPS_MAX_TRANSFER_SIZE) {
XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET, XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET,
XIICPS_MAX_TRANSFER_SIZE); XIICPS_MAX_TRANSFER_SIZE);
ByteCount = XIICPS_MAX_TRANSFER_SIZE; ByteCountVar = (s32)XIICPS_MAX_TRANSFER_SIZE;
UpdateTxSize = 1; UpdateTxSize = 1;
}else { }else {
XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET, XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET,
ByteCount); ByteCountVar);
} }
/* /*
* Intrs keeps all the error-related interrupts. * Intrs keeps all the error-related interrupts.
*/ */
Intrs = XIICPS_IXR_ARB_LOST_MASK | XIICPS_IXR_RX_OVR_MASK | Intrs = (u32)XIICPS_IXR_ARB_LOST_MASK | (u32)XIICPS_IXR_RX_OVR_MASK |
XIICPS_IXR_RX_UNF_MASK | XIICPS_IXR_NACK_MASK; (u32)XIICPS_IXR_RX_UNF_MASK | (u32)XIICPS_IXR_NACK_MASK;
/* /*
* Poll the interrupt status register to find the errors. * Poll the interrupt status register to find the errors.
*/ */
IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET); IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
while ((InstancePtr->RecvByteCount > 0) && while ((InstancePtr->RecvByteCount > 0) &&
((IntrStatusReg & Intrs) == 0)) { ((IntrStatusReg & Intrs) == 0U)) {
StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET); StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
while (StatusReg & XIICPS_SR_RXDV_MASK) { while ((StatusReg & XIICPS_SR_RXDV_MASK) != 0U) {
if ((InstancePtr->RecvByteCount < if (((InstancePtr->RecvByteCount <
XIICPS_DATA_INTR_DEPTH) && IsHold && XIICPS_DATA_INTR_DEPTH) != 0U) && (IsHold != 0) &&
(!(InstancePtr->IsRepeatedStart))) { ((!(InstancePtr->IsRepeatedStart)) != 0)) {
IsHold = 0; IsHold = 0;
XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
XIicPs_ReadReg(BaseAddr, XIicPs_ReadReg(BaseAddr,
@ -436,22 +450,24 @@ int XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr,
(~XIICPS_CR_HOLD_MASK)); (~XIICPS_CR_HOLD_MASK));
} }
XIicPs_RecvByte(InstancePtr); XIicPs_RecvByte(InstancePtr);
ByteCount --; ByteCountVar --;
if (UpdateTxSize && if ((UpdateTxSize != 0) &&
(ByteCount == XIICPS_FIFO_DEPTH + 1)) ((ByteCountVar == (XIICPS_FIFO_DEPTH + 1)) != 0U)) {
break; break;
}
StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET); StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
} }
if (UpdateTxSize && (ByteCount == XIICPS_FIFO_DEPTH + 1)) { if ((UpdateTxSize != 0) && ((ByteCountVar == (XIICPS_FIFO_DEPTH + 1)) != 0U)) {
/* /*
* wait while fifo is full * wait while fifo is full
*/ */
while(XIicPs_ReadReg(BaseAddr, while(XIicPs_ReadReg(BaseAddr,
XIICPS_TRANS_SIZE_OFFSET) != XIICPS_TRANS_SIZE_OFFSET) !=
(ByteCount - XIICPS_FIFO_DEPTH)); (u32)(ByteCountVar - XIICPS_FIFO_DEPTH)) { ;
}
if ((InstancePtr->RecvByteCount - XIICPS_FIFO_DEPTH) > if ((InstancePtr->RecvByteCount - XIICPS_FIFO_DEPTH) >
XIICPS_MAX_TRANSFER_SIZE) { XIICPS_MAX_TRANSFER_SIZE) {
@ -459,7 +475,7 @@ int XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr,
XIicPs_WriteReg(BaseAddr, XIicPs_WriteReg(BaseAddr,
XIICPS_TRANS_SIZE_OFFSET, XIICPS_TRANS_SIZE_OFFSET,
XIICPS_MAX_TRANSFER_SIZE); XIICPS_MAX_TRANSFER_SIZE);
ByteCount = XIICPS_MAX_TRANSFER_SIZE + ByteCountVar = (s32)XIICPS_MAX_TRANSFER_SIZE +
XIICPS_FIFO_DEPTH; XIICPS_FIFO_DEPTH;
}else { }else {
XIicPs_WriteReg(BaseAddr, XIicPs_WriteReg(BaseAddr,
@ -467,24 +483,26 @@ int XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr,
InstancePtr->RecvByteCount - InstancePtr->RecvByteCount -
XIICPS_FIFO_DEPTH); XIICPS_FIFO_DEPTH);
UpdateTxSize = 0; UpdateTxSize = 0;
ByteCount = InstancePtr->RecvByteCount; ByteCountVar = InstancePtr->RecvByteCount;
} }
} }
IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET); IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
} }
if (!(InstancePtr->IsRepeatedStart)) { if ((!(InstancePtr->IsRepeatedStart)) != 0) {
XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
XIicPs_ReadReg(BaseAddr,XIICPS_CR_OFFSET) & XIicPs_ReadReg(BaseAddr,XIICPS_CR_OFFSET) &
(~XIICPS_CR_HOLD_MASK)); (~XIICPS_CR_HOLD_MASK));
} }
if ((IntrStatusReg & Intrs) != 0x0U) {
if (IntrStatusReg & Intrs) { Result = (s32)XST_FAILURE;
return XST_FAILURE; }
else {
Result = (s32)XST_SUCCESS;
} }
return XST_SUCCESS; return Result;
} }
/*****************************************************************************/ /*****************************************************************************/
@ -514,33 +532,33 @@ void XIicPs_EnableSlaveMonitor(XIicPs *InstancePtr, u16 SlaveAddr)
BaseAddr = InstancePtr->Config.BaseAddress; BaseAddr = InstancePtr->Config.BaseAddress;
/* Clear transfer size register */ /* Clear transfer size register */
XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET, 0x0); XIicPs_WriteReg(BaseAddr, (u32)XIICPS_TRANS_SIZE_OFFSET, 0x0U);
/* /*
* Enable slave monitor mode in control register. * Enable slave monitor mode in control register.
*/ */
ConfigReg = XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET); ConfigReg = XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET);
ConfigReg |= XIICPS_CR_MS_MASK | XIICPS_CR_NEA_MASK | ConfigReg |= (u32)XIICPS_CR_MS_MASK | (u32)XIICPS_CR_NEA_MASK |
XIICPS_CR_CLR_FIFO_MASK | XIICPS_CR_SLVMON_MASK; (u32)XIICPS_CR_CLR_FIFO_MASK | (u32)XIICPS_CR_SLVMON_MASK;
ConfigReg &= ~XIICPS_CR_RD_WR_MASK; ConfigReg &= (u32)(~XIICPS_CR_RD_WR_MASK);
XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, ConfigReg); XIicPs_WriteReg(BaseAddr, (u32)XIICPS_CR_OFFSET, ConfigReg);
/* /*
* Set up interrupt flag for slave monitor interrupt. * Set up interrupt flag for slave monitor interrupt.
* Dont enable NACK. * Dont enable NACK.
*/ */
XIicPs_EnableInterrupts(BaseAddr, XIICPS_IXR_SLV_RDY_MASK); XIicPs_EnableInterrupts(BaseAddr, (u32)XIICPS_IXR_SLV_RDY_MASK);
/* /*
* Initialize the slave monitor register. * Initialize the slave monitor register.
*/ */
XIicPs_WriteReg(BaseAddr, XIICPS_SLV_PAUSE_OFFSET, 0xF); XIicPs_WriteReg(BaseAddr, (u32)XIICPS_SLV_PAUSE_OFFSET, 0xFU);
/* /*
* Set the slave address to start the slave address transmission. * Set the slave address to start the slave address transmission.
*/ */
XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr); XIicPs_WriteReg(BaseAddr, (u32)XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
return; return;
} }
@ -624,16 +642,16 @@ void XIicPs_DisableSlaveMonitor(XIicPs *InstancePtr)
void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr) void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr)
{ {
u32 IntrStatusReg; u32 IntrStatusReg;
u32 StatusEvent = 0; u32 StatusEvent = 0U;
u32 BaseAddr; u32 BaseAddr;
int ByteCnt; s32 ByteCnt;
int IsHold; s32 IsHold;
/* /*
* Assert validates the input arguments. * Assert validates the input arguments.
*/ */
Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
BaseAddr = InstancePtr->Config.BaseAddress; BaseAddr = InstancePtr->Config.BaseAddress;
@ -641,32 +659,32 @@ void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr)
* Read the Interrupt status register. * Read the Interrupt status register.
*/ */
IntrStatusReg = XIicPs_ReadReg(BaseAddr, IntrStatusReg = XIicPs_ReadReg(BaseAddr,
XIICPS_ISR_OFFSET); (u32)XIICPS_ISR_OFFSET);
/* /*
* Write the status back to clear the interrupts so no events are * Write the status back to clear the interrupts so no events are
* missed while processing this interrupt. * missed while processing this interrupt.
*/ */
XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg); XIicPs_WriteReg(BaseAddr, (u32)XIICPS_ISR_OFFSET, IntrStatusReg);
/* /*
* Use the Mask register AND with the Interrupt Status register so * Use the Mask register AND with the Interrupt Status register so
* disabled interrupts are not processed. * disabled interrupts are not processed.
*/ */
IntrStatusReg &= ~(XIicPs_ReadReg(BaseAddr, XIICPS_IMR_OFFSET)); IntrStatusReg &= ~(XIicPs_ReadReg(BaseAddr, (u32)XIICPS_IMR_OFFSET));
ByteCnt = InstancePtr->CurrByteCount; ByteCnt = InstancePtr->CurrByteCount;
IsHold = 0; IsHold = 0;
if (XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET) & XIICPS_CR_HOLD_MASK) { if ((XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) & (u32)XIICPS_CR_HOLD_MASK) != 0U) {
IsHold = 1; IsHold = 1;
} }
/* /*
* Send * Send
*/ */
if ((InstancePtr->IsSend) && if (((InstancePtr->IsSend) != 0) &&
(0 != (IntrStatusReg & XIICPS_IXR_COMP_MASK))) { ((u32)0U != (IntrStatusReg & (u32)XIICPS_IXR_COMP_MASK))) {
if (InstancePtr->SendByteCount > 0) { if (InstancePtr->SendByteCount > 0) {
MasterSendData(InstancePtr); MasterSendData(InstancePtr);
} else { } else {
@ -678,15 +696,15 @@ void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr)
/* /*
* Receive * Receive
*/ */
if ((!(InstancePtr->IsSend)) && if (((!(InstancePtr->IsSend))!= 0) &&
((0 != (IntrStatusReg & XIICPS_IXR_DATA_MASK)) || ((0 != (IntrStatusReg & (u32)XIICPS_IXR_DATA_MASK)) ||
(0 != (IntrStatusReg & XIICPS_IXR_COMP_MASK)))){ (0 != (IntrStatusReg & (u32)XIICPS_IXR_COMP_MASK)))){
while (XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET) & while ((XIicPs_ReadReg(BaseAddr, (u32)XIICPS_SR_OFFSET) &
XIICPS_SR_RXDV_MASK) { XIICPS_SR_RXDV_MASK) != 0U) {
if ((InstancePtr->RecvByteCount < if (((InstancePtr->RecvByteCount <
XIICPS_DATA_INTR_DEPTH) && IsHold && XIICPS_DATA_INTR_DEPTH)!= 0U) && (IsHold != 0) &&
(!(InstancePtr->IsRepeatedStart))) { ((!(InstancePtr->IsRepeatedStart))!= 0)) {
IsHold = 0; IsHold = 0;
XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
XIicPs_ReadReg(BaseAddr, XIicPs_ReadReg(BaseAddr,
@ -696,19 +714,21 @@ void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr)
XIicPs_RecvByte(InstancePtr); XIicPs_RecvByte(InstancePtr);
ByteCnt--; ByteCnt--;
if (InstancePtr->UpdateTxSize && if ((InstancePtr->UpdateTxSize != 0) &&
(ByteCnt == XIICPS_FIFO_DEPTH + 1)) ((ByteCnt == (XIICPS_FIFO_DEPTH + 1))!= 0U)) {
break; break;
}
} }
if (InstancePtr->UpdateTxSize && if ((InstancePtr->UpdateTxSize != 0) &&
(ByteCnt == XIICPS_FIFO_DEPTH + 1)) { ((ByteCnt == (XIICPS_FIFO_DEPTH + 1))!= 0U)) {
/* /*
* wait while fifo is full * wait while fifo is full
*/ */
while(XIicPs_ReadReg(BaseAddr, while(XIicPs_ReadReg(BaseAddr,
XIICPS_TRANS_SIZE_OFFSET) != XIICPS_TRANS_SIZE_OFFSET) !=
(ByteCnt - XIICPS_FIFO_DEPTH)); (u32)(ByteCnt - XIICPS_FIFO_DEPTH)) {
}
if ((InstancePtr->RecvByteCount - XIICPS_FIFO_DEPTH) > if ((InstancePtr->RecvByteCount - XIICPS_FIFO_DEPTH) >
XIICPS_MAX_TRANSFER_SIZE) { XIICPS_MAX_TRANSFER_SIZE) {
@ -716,7 +736,7 @@ void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr)
XIicPs_WriteReg(BaseAddr, XIicPs_WriteReg(BaseAddr,
XIICPS_TRANS_SIZE_OFFSET, XIICPS_TRANS_SIZE_OFFSET,
XIICPS_MAX_TRANSFER_SIZE); XIICPS_MAX_TRANSFER_SIZE);
ByteCnt = XIICPS_MAX_TRANSFER_SIZE + ByteCnt = (s32)XIICPS_MAX_TRANSFER_SIZE +
XIICPS_FIFO_DEPTH; XIICPS_FIFO_DEPTH;
}else { }else {
XIicPs_WriteReg(BaseAddr, XIicPs_WriteReg(BaseAddr,
@ -730,13 +750,13 @@ void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr)
InstancePtr->CurrByteCount = ByteCnt; InstancePtr->CurrByteCount = ByteCnt;
} }
if ((!(InstancePtr->IsSend)) && if (((!(InstancePtr->IsSend)) != 0) &&
(0 != (IntrStatusReg & XIICPS_IXR_COMP_MASK))) { (0U != (IntrStatusReg & XIICPS_IXR_COMP_MASK))) {
/* /*
* If all done, tell the application. * If all done, tell the application.
*/ */
if (InstancePtr->RecvByteCount == 0){ if (InstancePtr->RecvByteCount == 0){
if (!(InstancePtr->IsRepeatedStart)) { if ((!(InstancePtr->IsRepeatedStart)) != 0) {
XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
XIicPs_ReadReg(BaseAddr, XIicPs_ReadReg(BaseAddr,
XIICPS_CR_OFFSET) & XIICPS_CR_OFFSET) &
@ -750,12 +770,12 @@ void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr)
/* /*
* Slave ready interrupt, it is only meaningful for master mode. * Slave ready interrupt, it is only meaningful for master mode.
*/ */
if (0 != (IntrStatusReg & XIICPS_IXR_SLV_RDY_MASK)) { if (0U != (IntrStatusReg & XIICPS_IXR_SLV_RDY_MASK)) {
StatusEvent |= XIICPS_EVENT_SLAVE_RDY; StatusEvent |= XIICPS_EVENT_SLAVE_RDY;
} }
if (0 != (IntrStatusReg & XIICPS_IXR_NACK_MASK)) { if (0U != (IntrStatusReg & XIICPS_IXR_NACK_MASK)) {
if (!(InstancePtr->IsRepeatedStart)) { if ((!(InstancePtr->IsRepeatedStart)) != 0 ) {
XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
XIicPs_ReadReg(BaseAddr, XIicPs_ReadReg(BaseAddr,
XIICPS_CR_OFFSET) & XIICPS_CR_OFFSET) &
@ -767,10 +787,10 @@ void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr)
/* /*
* All other interrupts are treated as error. * All other interrupts are treated as error.
*/ */
if (0 != (IntrStatusReg & (XIICPS_IXR_NACK_MASK | if (0U != (IntrStatusReg & (XIICPS_IXR_NACK_MASK |
XIICPS_IXR_ARB_LOST_MASK | XIICPS_IXR_RX_UNF_MASK | XIICPS_IXR_ARB_LOST_MASK | XIICPS_IXR_RX_UNF_MASK |
XIICPS_IXR_TX_OVR_MASK | XIICPS_IXR_RX_OVR_MASK))) { XIICPS_IXR_TX_OVR_MASK | XIICPS_IXR_RX_OVR_MASK))) {
if (!(InstancePtr->IsRepeatedStart)) { if ((!(InstancePtr->IsRepeatedStart)) != 0) {
XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
XIicPs_ReadReg(BaseAddr, XIicPs_ReadReg(BaseAddr,
XIICPS_CR_OFFSET) & XIICPS_CR_OFFSET) &
@ -782,7 +802,7 @@ void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr)
/* /*
* Signal application if there are any events. * Signal application if there are any events.
*/ */
if (0 != StatusEvent) { if (StatusEvent != 0U) {
InstancePtr->StatusHandler(InstancePtr->CallBackRef, InstancePtr->StatusHandler(InstancePtr->CallBackRef,
StatusEvent); StatusEvent);
} }
@ -805,11 +825,11 @@ void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr)
* interrupts needs to setup interrupts after this call. * interrupts needs to setup interrupts after this call.
* *
****************************************************************************/ ****************************************************************************/
static int XIicPs_SetupMaster(XIicPs *InstancePtr, int Role) static s32 XIicPs_SetupMaster(XIicPs *InstancePtr, s32 Role)
{ {
u32 ControlReg; u32 ControlReg;
u32 BaseAddr; u32 BaseAddr;
u32 EnabledIntr = 0x0; u32 EnabledIntr = 0x0U;
Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr != NULL);
@ -820,31 +840,31 @@ static int XIicPs_SetupMaster(XIicPs *InstancePtr, int Role)
/* /*
* Only check if bus is busy when repeated start option is not set. * Only check if bus is busy when repeated start option is not set.
*/ */
if ((ControlReg & XIICPS_CR_HOLD_MASK) == 0) { if ((ControlReg & XIICPS_CR_HOLD_MASK) == 0U) {
if (XIicPs_BusIsBusy(InstancePtr)) { if (XIicPs_BusIsBusy(InstancePtr) == (s32)1) {
return XST_FAILURE; return (s32)XST_FAILURE;
} }
} }
/* /*
* Set up master, AckEn, nea and also clear fifo. * Set up master, AckEn, nea and also clear fifo.
*/ */
ControlReg |= XIICPS_CR_ACKEN_MASK | XIICPS_CR_CLR_FIFO_MASK | ControlReg |= (u32)XIICPS_CR_ACKEN_MASK | (u32)XIICPS_CR_CLR_FIFO_MASK |
XIICPS_CR_NEA_MASK | XIICPS_CR_MS_MASK; (u32)XIICPS_CR_NEA_MASK | (u32)XIICPS_CR_MS_MASK;
if (Role == RECVING_ROLE) { if (Role == RECVING_ROLE) {
ControlReg |= XIICPS_CR_RD_WR_MASK; ControlReg |= (u32)XIICPS_CR_RD_WR_MASK;
EnabledIntr = XIICPS_IXR_DATA_MASK |XIICPS_IXR_RX_OVR_MASK; EnabledIntr = (u32)XIICPS_IXR_DATA_MASK |(u32)XIICPS_IXR_RX_OVR_MASK;
}else { }else {
ControlReg &= ~XIICPS_CR_RD_WR_MASK; ControlReg &= (u32)(~XIICPS_CR_RD_WR_MASK);
} }
EnabledIntr |= XIICPS_IXR_COMP_MASK | XIICPS_IXR_ARB_LOST_MASK; EnabledIntr |= (u32)XIICPS_IXR_COMP_MASK | (u32)XIICPS_IXR_ARB_LOST_MASK;
XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, ControlReg); XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, ControlReg);
XIicPs_DisableAllInterrupts(BaseAddr); XIicPs_DisableAllInterrupts(BaseAddr);
return XST_SUCCESS; return (s32)XST_SUCCESS;
} }
/*****************************************************************************/ /*****************************************************************************/
@ -861,7 +881,7 @@ static int XIicPs_SetupMaster(XIicPs *InstancePtr, int Role)
****************************************************************************/ ****************************************************************************/
static void MasterSendData(XIicPs *InstancePtr) static void MasterSendData(XIicPs *InstancePtr)
{ {
TransmitFifoFill(InstancePtr); (void)TransmitFifoFill(InstancePtr);
/* /*
* Clear hold bit if done, so stop can be sent out. * Clear hold bit if done, so stop can be sent out.
@ -872,12 +892,12 @@ static void MasterSendData(XIicPs *InstancePtr)
* If user has enabled repeated start as an option, * If user has enabled repeated start as an option,
* do not disable it. * do not disable it.
*/ */
if (!(InstancePtr->IsRepeatedStart)) { if ((!(InstancePtr->IsRepeatedStart)) != 0) {
XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
XIICPS_CR_OFFSET, (u32)XIICPS_CR_OFFSET,
XIicPs_ReadReg(InstancePtr->Config.BaseAddress, XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
XIICPS_CR_OFFSET) & ~ XIICPS_CR_HOLD_MASK); (u32)XIICPS_CR_OFFSET) & (u32)(~ XIICPS_CR_HOLD_MASK));
} }
} }

133
XilinxProcessorIPLib/drivers/iicps/src/xiicps_options.c
View file

@ -115,13 +115,14 @@ static OptionsMap OptionsTable[] = {
* @note None. * @note None.
* *
******************************************************************************/ ******************************************************************************/
int XIicPs_SetOptions(XIicPs *InstancePtr, u32 Options) s32 XIicPs_SetOptions(XIicPs *InstancePtr, u32 Options)
{ {
u32 ControlReg; u32 ControlReg;
unsigned int Index; u32 Index;
u32 OptionsVar = Options;
Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress, ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
XIICPS_CR_OFFSET); XIICPS_CR_OFFSET);
@ -131,26 +132,26 @@ int XIicPs_SetOptions(XIicPs *InstancePtr, u32 Options)
* The hold bit in CR will be written by driver when the next transfer * The hold bit in CR will be written by driver when the next transfer
* is initiated. * is initiated.
*/ */
if (Options & XIICPS_REP_START_OPTION) { if ((OptionsVar & XIICPS_REP_START_OPTION) != 0U ) {
InstancePtr->IsRepeatedStart = 1; InstancePtr->IsRepeatedStart = 1;
Options = Options & (~XIICPS_REP_START_OPTION); OptionsVar = OptionsVar & (~XIICPS_REP_START_OPTION);
} }
/* /*
* Loop through the options table, turning the option on. * Loop through the options table, turning the option on.
*/ */
for (Index = 0; Index < XIICPS_NUM_OPTIONS; Index++) { for (Index = 0U; Index < XIICPS_NUM_OPTIONS; Index++) {
if (Options & OptionsTable[Index].Option) { if ((OptionsVar & OptionsTable[Index].Option) != (u32)0x0U) {
/* /*
* 10-bit option is specially treated, because it is * 10-bit option is specially treated, because it is
* using the 7-bit option, so turning it on means * using the 7-bit option, so turning it on means
* turning 7-bit option off. * turning 7-bit option off.
*/ */
if (OptionsTable[Index].Option & if ((OptionsTable[Index].Option &
XIICPS_10_BIT_ADDR_OPTION) { XIICPS_10_BIT_ADDR_OPTION) != (u32)0x0U) {
/* Turn 7-bit off */ /* Turn 7-bit off */
ControlReg &= ~OptionsTable[Index].Mask; ControlReg &= ~OptionsTable[Index].Mask;
} else { } else {
/* Turn 7-bit on */ /* Turn 7-bit on */
ControlReg |= OptionsTable[Index].Mask; ControlReg |= OptionsTable[Index].Mask;
} }
@ -169,7 +170,7 @@ int XIicPs_SetOptions(XIicPs *InstancePtr, u32 Options)
*/ */
InstancePtr->Options = XIicPs_GetOptions(InstancePtr); InstancePtr->Options = XIicPs_GetOptions(InstancePtr);
return XST_SUCCESS; return (s32)XST_SUCCESS;
} }
/*****************************************************************************/ /*****************************************************************************/
@ -194,13 +195,14 @@ int XIicPs_SetOptions(XIicPs *InstancePtr, u32 Options)
* @note None * @note None
* *
******************************************************************************/ ******************************************************************************/
int XIicPs_ClearOptions(XIicPs *InstancePtr, u32 Options) s32 XIicPs_ClearOptions(XIicPs *InstancePtr, u32 Options)
{ {
u32 ControlReg; u32 ControlReg;
unsigned int Index; u32 Index;
u32 OptionsVar = Options;
Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress, ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
XIICPS_CR_OFFSET); XIICPS_CR_OFFSET);
@ -210,24 +212,24 @@ int XIicPs_ClearOptions(XIicPs *InstancePtr, u32 Options)
* The hold bit in CR will be cleared by driver when the * The hold bit in CR will be cleared by driver when the
* following transfer ends. * following transfer ends.
*/ */
if (Options & XIICPS_REP_START_OPTION) { if ((OptionsVar & XIICPS_REP_START_OPTION) != (u32)0x0U ) {
InstancePtr->IsRepeatedStart = 0; InstancePtr->IsRepeatedStart = 0;
Options = Options & (~XIICPS_REP_START_OPTION); OptionsVar = OptionsVar & (~XIICPS_REP_START_OPTION);
} }
/* /*
* Loop through the options table and clear the specified options. * Loop through the options table and clear the specified options.
*/ */
for (Index = 0; Index < XIICPS_NUM_OPTIONS; Index++) { for (Index = 0U; Index < XIICPS_NUM_OPTIONS; Index++) {
if (Options & OptionsTable[Index].Option) { if ((OptionsVar & OptionsTable[Index].Option) != (u32)0x0U) {
/* /*
* 10-bit option is specially treated, because it is * 10-bit option is specially treated, because it is
* using the 7-bit option, so clearing it means turning * using the 7-bit option, so clearing it means turning
* 7-bit option on. * 7-bit option on.
*/ */
if (OptionsTable[Index].Option & if ((OptionsTable[Index].Option &
XIICPS_10_BIT_ADDR_OPTION) { XIICPS_10_BIT_ADDR_OPTION) != (u32)0x0U) {
/* Turn 7-bit on */ /* Turn 7-bit on */
ControlReg |= OptionsTable[Index].Mask; ControlReg |= OptionsTable[Index].Mask;
@ -273,12 +275,12 @@ int XIicPs_ClearOptions(XIicPs *InstancePtr, u32 Options)
******************************************************************************/ ******************************************************************************/
u32 XIicPs_GetOptions(XIicPs *InstancePtr) u32 XIicPs_GetOptions(XIicPs *InstancePtr)
{ {
u32 OptionsFlag = 0; u32 OptionsFlag = 0U;
u32 ControlReg; u32 ControlReg;
unsigned int Index; u32 Index;
Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
/* /*
* Read control register to find which options are currently set. * Read control register to find which options are currently set.
@ -289,16 +291,16 @@ u32 XIicPs_GetOptions(XIicPs *InstancePtr)
/* /*
* Loop through the options table to determine which options are set. * Loop through the options table to determine which options are set.
*/ */
for (Index = 0; Index < XIICPS_NUM_OPTIONS; Index++) { for (Index = 0U; Index < XIICPS_NUM_OPTIONS; Index++) {
if (ControlReg & OptionsTable[Index].Mask) { if ((ControlReg & OptionsTable[Index].Mask) != (u32)0x0U) {
OptionsFlag |= OptionsTable[Index].Option; OptionsFlag |= OptionsTable[Index].Option;
} }
if ((ControlReg & XIICPS_CR_NEA_MASK) == 0) { if ((ControlReg & XIICPS_CR_NEA_MASK) == (u32)0x0U) {
OptionsFlag |= XIICPS_10_BIT_ADDR_OPTION; OptionsFlag |= XIICPS_10_BIT_ADDR_OPTION;
} }
} }
if (InstancePtr->IsRepeatedStart) { if (InstancePtr->IsRepeatedStart != 0 ) {
OptionsFlag |= XIICPS_REP_START_OPTION; OptionsFlag |= XIICPS_REP_START_OPTION;
} }
return OptionsFlag; return OptionsFlag;
@ -331,7 +333,7 @@ u32 XIicPs_GetOptions(XIicPs *InstancePtr)
* @note The clock can not be faster than the input clock divide by 22. * @note The clock can not be faster than the input clock divide by 22.
* *
******************************************************************************/ ******************************************************************************/
int XIicPs_SetSClk(XIicPs *InstancePtr, u32 FsclHz) s32 XIicPs_SetSClk(XIicPs *InstancePtr, u32 FsclHz)
{ {
u32 Div_a; u32 Div_a;
u32 Div_b; u32 Div_b;
@ -346,26 +348,27 @@ int XIicPs_SetSClk(XIicPs *InstancePtr, u32 FsclHz)
u32 CalcDivB; u32 CalcDivB;
u32 BestDivA = 0; u32 BestDivA = 0;
u32 BestDivB = 0; u32 BestDivB = 0;
u32 FsclHzVar = FsclHz;
Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(FsclHz > 0); Xil_AssertNonvoid(FsclHzVar > 0U);
if (0 != XIicPs_In32((InstancePtr->Config.BaseAddress) + if (0U != XIicPs_In32((InstancePtr->Config.BaseAddress) +
XIICPS_TRANS_SIZE_OFFSET)) { XIICPS_TRANS_SIZE_OFFSET)) {
return XST_DEVICE_IS_STARTED; return (s32)XST_DEVICE_IS_STARTED;
} }
/* /*
* Assume Div_a is 0 and calculate (divisor_a+1) x (divisor_b+1). * Assume Div_a is 0 and calculate (divisor_a+1) x (divisor_b+1).
*/ */
Temp = (InstancePtr->Config.InputClockHz) / (22 * FsclHz); Temp = (InstancePtr->Config.InputClockHz) / ((u32)22U * FsclHzVar);
/* /*
* If the answer is negative or 0, the Fscl input is out of range. * If the answer is negative or 0, the Fscl input is out of range.
*/ */
if (0 == Temp) { if ((u32)(0U) == Temp) {
return XST_FAILURE; return (s32)XST_FAILURE;
} }
/* /*
@ -373,12 +376,12 @@ int XIicPs_SetSClk(XIicPs *InstancePtr, u32 FsclHz)
* If frequency 100KHz is selected, 90KHz should be set. * If frequency 100KHz is selected, 90KHz should be set.
* This is due to a hardware limitation. * This is due to a hardware limitation.
*/ */
if(FsclHz > 384600) { if(FsclHzVar > 384600U) {
FsclHz = 384600; FsclHzVar = 384600U;
} }
if((FsclHz <= 100000) && (FsclHz > 90000)) { if((FsclHzVar <= 100000U) && (FsclHzVar > 90000U)) {
FsclHz = 90000; FsclHzVar = 90000U;
} }
/* /*
@ -386,34 +389,36 @@ int XIicPs_SetSClk(XIicPs *InstancePtr, u32 FsclHz)
* find the closest clock rate achievable with divisors. * find the closest clock rate achievable with divisors.
* Iterate over the next value only if fractional part is involved. * Iterate over the next value only if fractional part is involved.
*/ */
TempLimit = ((InstancePtr->Config.InputClockHz) % (22 * FsclHz)) ? TempLimit = (((InstancePtr->Config.InputClockHz) %
Temp + 1 : Temp; ((u32)22 * FsclHzVar)) != (u32)0x0U) ?
BestError = FsclHz; Temp + (u32)1U : Temp;
BestError = FsclHzVar;
BestDivA = 0U;
BestDivB = 0U;
for ( ; Temp <= TempLimit ; Temp++) for ( ; Temp <= TempLimit ; Temp++)
{ {
LastError = FsclHz; LastError = FsclHzVar;
CalcDivA = 0; CalcDivA = 0U;
CalcDivB = 0; CalcDivB = 0U;
CurrentError = 0;
for (Div_b = 0; Div_b < 64; Div_b++) { for (Div_b = 0U; Div_b < 64U; Div_b++) {
Div_a = Temp / (Div_b + 1); Div_a = Temp / (Div_b + 1U);
if (Div_a != 0) if (Div_a != 0U){
Div_a = Div_a - 1; Div_a = Div_a - (u32)1U;
}
if (Div_a > 3) if (Div_a > 3U){
continue; continue;
}
ActualFscl = (InstancePtr->Config.InputClockHz) / ActualFscl = (InstancePtr->Config.InputClockHz) /
(22 * (Div_a + 1) * (Div_b + 1)); (22U * (Div_a + 1U) * (Div_b + 1U));
if (ActualFscl > FsclHz) if (ActualFscl > FsclHzVar){
CurrentError = (ActualFscl - FsclHz); CurrentError = (ActualFscl - FsclHzVar);}
else else{
CurrentError = (FsclHz - ActualFscl); CurrentError = (FsclHzVar - ActualFscl);}
if (LastError > CurrentError) { if (LastError > CurrentError) {
CalcDivA = Div_a; CalcDivA = Div_a;
@ -437,15 +442,15 @@ int XIicPs_SetSClk(XIicPs *InstancePtr, u32 FsclHz)
* Read the control register and mask the Divisors. * Read the control register and mask the Divisors.
*/ */
ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress, ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
XIICPS_CR_OFFSET); (u32)XIICPS_CR_OFFSET);
ControlReg &= ~(XIICPS_CR_DIV_A_MASK | XIICPS_CR_DIV_B_MASK); ControlReg &= ~((u32)XIICPS_CR_DIV_A_MASK | (u32)XIICPS_CR_DIV_B_MASK);
ControlReg |= (BestDivA << XIICPS_CR_DIV_A_SHIFT) | ControlReg |= (BestDivA << XIICPS_CR_DIV_A_SHIFT) |
(BestDivB << XIICPS_CR_DIV_B_SHIFT); (BestDivB << XIICPS_CR_DIV_B_SHIFT);
XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET, XIicPs_WriteReg(InstancePtr->Config.BaseAddress, (u32)XIICPS_CR_OFFSET,
ControlReg); ControlReg);
return XST_SUCCESS; return (s32)XST_SUCCESS;
} }
/*****************************************************************************/ /*****************************************************************************/
@ -472,7 +477,7 @@ u32 XIicPs_GetSClk(XIicPs *InstancePtr)
u32 Div_b; u32 Div_b;
Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress, ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
XIICPS_CR_OFFSET); XIICPS_CR_OFFSET);
@ -481,7 +486,7 @@ u32 XIicPs_GetSClk(XIicPs *InstancePtr)
Div_b = (ControlReg & XIICPS_CR_DIV_B_MASK) >> XIICPS_CR_DIV_B_SHIFT; Div_b = (ControlReg & XIICPS_CR_DIV_B_MASK) >> XIICPS_CR_DIV_B_SHIFT;
ActualFscl = (InstancePtr->Config.InputClockHz) / ActualFscl = (InstancePtr->Config.InputClockHz) /
(22 * (Div_a + 1) * (Div_b + 1)); (22U * (Div_a + 1U) * (Div_b + 1U));
return ActualFscl; return ActualFscl;
} }

14
XilinxProcessorIPLib/drivers/iicps/src/xiicps_selftest.c
View file

@ -55,7 +55,7 @@
/************************** Constant Definitions *****************************/ /************************** Constant Definitions *****************************/
#define REG_TEST_VALUE 0x00000005 #define REG_TEST_VALUE 0x00000005U
/**************************** Type Definitions *******************************/ /**************************** Type Definitions *******************************/
@ -88,11 +88,11 @@
* @note None. * @note None.
* *
******************************************************************************/ ******************************************************************************/
int XIicPs_SelfTest(XIicPs *InstancePtr) s32 XIicPs_SelfTest(XIicPs *InstancePtr)
{ {
Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
/* /*
* All the IIC registers should be in their default state right now. * All the IIC registers should be in their default state right now.
@ -103,7 +103,7 @@ int XIicPs_SelfTest(XIicPs *InstancePtr)
(XIICPS_IXR_ALL_INTR_MASK != (XIICPS_IXR_ALL_INTR_MASK !=
XIicPs_ReadReg(InstancePtr->Config.BaseAddress, XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
XIICPS_IMR_OFFSET))) { XIICPS_IMR_OFFSET))) {
return XST_FAILURE; return (s32)XST_FAILURE;
} }
XIicPs_Reset(InstancePtr); XIicPs_Reset(InstancePtr);
@ -116,14 +116,14 @@ int XIicPs_SelfTest(XIicPs *InstancePtr)
if (REG_TEST_VALUE != XIicPs_ReadReg(InstancePtr->Config.BaseAddress, if (REG_TEST_VALUE != XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
XIICPS_SLV_PAUSE_OFFSET)) { XIICPS_SLV_PAUSE_OFFSET)) {
return XST_FAILURE; return (s32)XST_FAILURE;
} }
XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
XIICPS_SLV_PAUSE_OFFSET, 0); XIICPS_SLV_PAUSE_OFFSET, 0U);
XIicPs_Reset(InstancePtr); XIicPs_Reset(InstancePtr);
return XST_SUCCESS; return (s32)XST_SUCCESS;
} }

6
XilinxProcessorIPLib/drivers/iicps/src/xiicps_sinit.c
View file

@ -64,7 +64,7 @@
/************************** Function Prototypes ******************************/ /************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/ /************************** Variable Definitions *****************************/
extern XIicPs_Config XIicPs_ConfigTable[]; extern XIicPs_Config XIicPs_ConfigTable[XPAR_XIICPS_NUM_INSTANCES];
/*****************************************************************************/ /*****************************************************************************/
/** /**
@ -85,7 +85,7 @@ extern XIicPs_Config XIicPs_ConfigTable[];
XIicPs_Config *XIicPs_LookupConfig(u16 DeviceId) XIicPs_Config *XIicPs_LookupConfig(u16 DeviceId)
{ {
XIicPs_Config *CfgPtr = NULL; XIicPs_Config *CfgPtr = NULL;
int Index; s32 Index;
for (Index = 0; Index < XPAR_XIICPS_NUM_INSTANCES; Index++) { for (Index = 0; Index < XPAR_XIICPS_NUM_INSTANCES; Index++) {
if (XIicPs_ConfigTable[Index].DeviceId == DeviceId) { if (XIicPs_ConfigTable[Index].DeviceId == DeviceId) {
@ -94,5 +94,5 @@ XIicPs_Config *XIicPs_LookupConfig(u16 DeviceId)
} }
} }
return CfgPtr; return (XIicPs_Config *)CfgPtr;
} }

221
XilinxProcessorIPLib/drivers/iicps/src/xiicps_slave.c
View file

@ -56,9 +56,9 @@
/***************** Macros (Inline Functions) Definitions *********************/ /***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/ /************************** Function Prototypes ******************************/
extern int TransmitFifoFill(XIicPs *InstancePtr); extern s32 TransmitFifoFill(XIicPs *InstancePtr);
static int SlaveRecvData(XIicPs *InstancePtr); static s32 SlaveRecvData(XIicPs *InstancePtr);
/************************* Variable Definitions *****************************/ /************************* Variable Definitions *****************************/
@ -80,11 +80,11 @@ static int SlaveRecvData(XIicPs *InstancePtr);
****************************************************************************/ ****************************************************************************/
void XIicPs_SetupSlave(XIicPs *InstancePtr, u16 SlaveAddr) void XIicPs_SetupSlave(XIicPs *InstancePtr, u16 SlaveAddr)
{ {
volatile u32 ControlReg; u32 ControlReg;
u32 BaseAddr; u32 BaseAddr;
Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
Xil_AssertVoid(XIICPS_ADDR_MASK >= SlaveAddr); Xil_AssertVoid(XIICPS_ADDR_MASK >= SlaveAddr);
BaseAddr = InstancePtr->Config.BaseAddress; BaseAddr = InstancePtr->Config.BaseAddress;
@ -94,9 +94,9 @@ void XIicPs_SetupSlave(XIicPs *InstancePtr, u16 SlaveAddr)
/* /*
* Set up master, AckEn, nea and also clear fifo. * Set up master, AckEn, nea and also clear fifo.
*/ */
ControlReg |= XIICPS_CR_ACKEN_MASK | XIICPS_CR_CLR_FIFO_MASK; ControlReg |= (u32)XIICPS_CR_ACKEN_MASK | (u32)XIICPS_CR_CLR_FIFO_MASK;
ControlReg |= XIICPS_CR_NEA_MASK; ControlReg |= (u32)XIICPS_CR_NEA_MASK;
ControlReg &= ~XIICPS_CR_MS_MASK; ControlReg &= (u32)(~XIICPS_CR_MS_MASK);
XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
ControlReg); ControlReg);
@ -104,7 +104,7 @@ void XIicPs_SetupSlave(XIicPs *InstancePtr, u16 SlaveAddr)
XIicPs_DisableAllInterrupts(BaseAddr); XIicPs_DisableAllInterrupts(BaseAddr);
XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
XIICPS_ADDR_OFFSET, SlaveAddr); XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
return; return;
} }
@ -124,7 +124,7 @@ void XIicPs_SetupSlave(XIicPs *InstancePtr, u16 SlaveAddr)
* @note This send routine is for interrupt-driven transfer only. * @note This send routine is for interrupt-driven transfer only.
* *
****************************************************************************/ ****************************************************************************/
void XIicPs_SlaveSend(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount) void XIicPs_SlaveSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
{ {
u32 BaseAddr; u32 BaseAddr;
@ -133,7 +133,7 @@ void XIicPs_SlaveSend(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount)
*/ */
Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(MsgPtr != NULL); Xil_AssertVoid(MsgPtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
BaseAddr = InstancePtr->Config.BaseAddress; BaseAddr = InstancePtr->Config.BaseAddress;
@ -142,9 +142,9 @@ void XIicPs_SlaveSend(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount)
InstancePtr->RecvBufferPtr = NULL; InstancePtr->RecvBufferPtr = NULL;
XIicPs_EnableInterrupts(BaseAddr, XIicPs_EnableInterrupts(BaseAddr,
XIICPS_IXR_DATA_MASK | XIICPS_IXR_COMP_MASK | (u32)XIICPS_IXR_DATA_MASK | (u32)XIICPS_IXR_COMP_MASK |
XIICPS_IXR_TO_MASK | XIICPS_IXR_NACK_MASK | (u32)XIICPS_IXR_TO_MASK | (u32)XIICPS_IXR_NACK_MASK |
XIICPS_IXR_TX_OVR_MASK); (u32)XIICPS_IXR_TX_OVR_MASK);
} }
/*****************************************************************************/ /*****************************************************************************/
@ -161,14 +161,14 @@ void XIicPs_SlaveSend(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount)
* @note This routine is for interrupt-driven transfer only. * @note This routine is for interrupt-driven transfer only.
* *
****************************************************************************/ ****************************************************************************/
void XIicPs_SlaveRecv(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount) void XIicPs_SlaveRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
{ {
/* /*
* Assert validates the input arguments. * Assert validates the input arguments.
*/ */
Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(MsgPtr != NULL); Xil_AssertVoid(MsgPtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
InstancePtr->RecvBufferPtr = MsgPtr; InstancePtr->RecvBufferPtr = MsgPtr;
@ -176,9 +176,9 @@ void XIicPs_SlaveRecv(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount)
InstancePtr->SendBufferPtr = NULL; InstancePtr->SendBufferPtr = NULL;
XIicPs_EnableInterrupts(InstancePtr->Config.BaseAddress, XIicPs_EnableInterrupts(InstancePtr->Config.BaseAddress,
XIICPS_IXR_DATA_MASK | XIICPS_IXR_COMP_MASK | (u32)XIICPS_IXR_DATA_MASK | (u32)XIICPS_IXR_COMP_MASK |
XIICPS_IXR_NACK_MASK | XIICPS_IXR_TO_MASK | (u32)XIICPS_IXR_NACK_MASK | (u32)XIICPS_IXR_TO_MASK |
XIICPS_IXR_RX_OVR_MASK | XIICPS_IXR_RX_UNF_MASK); (u32)XIICPS_IXR_RX_OVR_MASK | (u32)XIICPS_IXR_RX_UNF_MASK);
} }
@ -198,21 +198,23 @@ void XIicPs_SlaveRecv(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount)
* @note This send routine is for polled mode transfer only. * @note This send routine is for polled mode transfer only.
* *
****************************************************************************/ ****************************************************************************/
int XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount) s32 XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
{ {
volatile u32 IntrStatusReg; u32 IntrStatusReg;
volatile u32 StatusReg; u32 StatusReg;
u32 BaseAddr; u32 BaseAddr;
int Tmp; s32 Tmp;
int BytesToSend; s32 BytesToSend;
int Error = 0; s32 Error = 0;
s32 Status = (s32)XST_SUCCESS;
u32 Value;
/* /*
* Assert validates the input arguments. * Assert validates the input arguments.
*/ */
Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(MsgPtr != NULL); Xil_AssertNonvoid(MsgPtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
BaseAddr = InstancePtr->Config.BaseAddress; BaseAddr = InstancePtr->Config.BaseAddress;
InstancePtr->SendBufferPtr = MsgPtr; InstancePtr->SendBufferPtr = MsgPtr;
@ -222,78 +224,84 @@ int XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount)
* Use RXRW bit in status register to wait master to start a read. * Use RXRW bit in status register to wait master to start a read.
*/ */
StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET); StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
while (((StatusReg & XIICPS_SR_RXRW_MASK) == 0) && (!Error)) { while (((StatusReg & XIICPS_SR_RXRW_MASK) == 0U) &&
((!Error) != 0)) {
/* /*
* If master tries to send us data, it is an error. * If master tries to send us data, it is an error.
*/ */
if (StatusReg & XIICPS_SR_RXDV_MASK) { if ((StatusReg & XIICPS_SR_RXDV_MASK) != 0x0U) {
Error = 1; Error = 1;
} }
StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET); StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
} }
if (Error) { if (Error != 0) {
return XST_FAILURE; Status = (s32)XST_FAILURE;
} } else {
/*
* Clear the interrupt status register.
*/
IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
/*
* Send data as long as there is more data to send and
* there are no errors.
*/
while ((InstancePtr->SendByteCount > 0) && (!Error)){
/* /*
* Find out how many can be sent. * Clear the interrupt status register.
*/ */
BytesToSend = InstancePtr->SendByteCount; IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
if (BytesToSend > XIICPS_FIFO_DEPTH) { XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
BytesToSend = XIICPS_FIFO_DEPTH;
}
for(Tmp = 0; Tmp < BytesToSend; Tmp ++) {
XIicPs_SendByte(InstancePtr);
}
StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
/* /*
* Wait for master to read the data out of fifo. * Send data as long as there is more data to send and
* there are no errors.
*/ */
while (((StatusReg & XIICPS_SR_TXDV_MASK) != 0) && (!Error)) { Value = (InstancePtr->SendByteCount > (s32)0) &&
((!Error) != 0);
while (Value != (u32)0x00U) {
/* /*
* If master terminates the transfer before all data is * Find out how many can be sent.
* sent, it is an error.
*/ */
IntrStatusReg = XIicPs_ReadReg(BaseAddr, BytesToSend = InstancePtr->SendByteCount;
XIICPS_ISR_OFFSET); if (BytesToSend > (s32)(XIICPS_FIFO_DEPTH)) {
if (IntrStatusReg & XIICPS_IXR_NACK_MASK) { BytesToSend = (s32)(XIICPS_FIFO_DEPTH);
Error = 1;
} }
/* Clear ISR. for(Tmp = 0; Tmp < BytesToSend; Tmp ++) {
*/ XIicPs_SendByte(InstancePtr);
XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, }
IntrStatusReg);
StatusReg = XIicPs_ReadReg(BaseAddr, StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
XIICPS_SR_OFFSET);
/*
* Wait for master to read the data out of fifo.
*/
while (((StatusReg & XIICPS_SR_TXDV_MASK) != (u32)0x00U) &&
((!Error) != 0)) {
/*
* If master terminates the transfer before all data is
* sent, it is an error.
*/
IntrStatusReg = XIicPs_ReadReg(BaseAddr,
XIICPS_ISR_OFFSET);
if ((IntrStatusReg & XIICPS_IXR_NACK_MASK) != 0x0U) {
Error = 1;
}
/* Clear ISR.
*/
XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET,
IntrStatusReg);
StatusReg = XIicPs_ReadReg(BaseAddr,
XIICPS_SR_OFFSET);
}
Value = (InstancePtr->SendByteCount > (s32)0U) &&
((!Error) != 0);
} }
} }
if (Error != 0) {
if (Error) { Status = (s32)XST_FAILURE;
return XST_FAILURE;
} }
return XST_SUCCESS; return Status;
} }
/*****************************************************************************/ /*****************************************************************************/
/** /**
@ -310,18 +318,19 @@ int XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount)
* @note This receive routine is for polled mode transfer only. * @note This receive routine is for polled mode transfer only.
* *
****************************************************************************/ ****************************************************************************/
int XIicPs_SlaveRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount) s32 XIicPs_SlaveRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
{ {
volatile u32 IntrStatusReg; u32 IntrStatusReg;
volatile u32 StatusReg; u32 StatusReg;
u32 BaseAddr; u32 BaseAddr;
s32 Count;
/* /*
* Assert validates the input arguments. * Assert validates the input arguments.
*/ */
Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(MsgPtr != NULL); Xil_AssertNonvoid(MsgPtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
BaseAddr = InstancePtr->Config.BaseAddress; BaseAddr = InstancePtr->Config.BaseAddress;
InstancePtr->RecvBufferPtr = MsgPtr; InstancePtr->RecvBufferPtr = MsgPtr;
@ -342,25 +351,26 @@ int XIicPs_SlaveRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount)
XIicPs_WriteReg(BaseAddr, XIICPS_SR_OFFSET, StatusReg); XIicPs_WriteReg(BaseAddr, XIICPS_SR_OFFSET, StatusReg);
StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET); StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
while (InstancePtr->RecvByteCount > 0) { Count = InstancePtr->RecvByteCount;
while (Count > (s32)0) {
/* Wait for master to put data */ /* Wait for master to put data */
while ((StatusReg & XIICPS_SR_RXDV_MASK) == 0) { while ((StatusReg & XIICPS_SR_RXDV_MASK) == 0U) {
StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET); StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
/* /*
* If master terminates the transfer before we get all * If master terminates the transfer before we get all
* the data or the master tries to read from us, * the data or the master tries to read from us,
* it is an error. * it is an error.
*/ */
IntrStatusReg = XIicPs_ReadReg(BaseAddr, IntrStatusReg = XIicPs_ReadReg(BaseAddr,
XIICPS_ISR_OFFSET); XIICPS_ISR_OFFSET);
if ((IntrStatusReg & (XIICPS_IXR_DATA_MASK | if (((IntrStatusReg & (XIICPS_IXR_DATA_MASK |
XIICPS_IXR_COMP_MASK)) && XIICPS_IXR_COMP_MASK))!=0x0U) &&
((StatusReg & XIICPS_SR_RXDV_MASK) == 0) && ((StatusReg & XIICPS_SR_RXDV_MASK) == 0U) &&
(InstancePtr->RecvByteCount > 0)) { ((InstancePtr->RecvByteCount > 0) != 0x0U)) {
return XST_FAILURE; return (s32)XST_FAILURE;
} }
/* /*
@ -373,17 +383,18 @@ int XIicPs_SlaveRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount)
/* /*
* Read all data from FIFO. * Read all data from FIFO.
*/ */
while ((StatusReg & XIICPS_SR_RXDV_MASK) && while (((StatusReg & XIICPS_SR_RXDV_MASK)!=0x0U) &&
(InstancePtr->RecvByteCount > 0)){ ((InstancePtr->RecvByteCount > 0) != 0x0U)){
XIicPs_RecvByte(InstancePtr); XIicPs_RecvByte(InstancePtr);
StatusReg = XIicPs_ReadReg(BaseAddr, StatusReg = XIicPs_ReadReg(BaseAddr,
XIICPS_SR_OFFSET); XIICPS_SR_OFFSET);
} }
Count = InstancePtr->RecvByteCount;
} }
return XST_SUCCESS; return (s32)XST_SUCCESS;
} }
/*****************************************************************************/ /*****************************************************************************/
@ -430,17 +441,17 @@ int XIicPs_SlaveRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount)
****************************************************************************/ ****************************************************************************/
void XIicPs_SlaveInterruptHandler(XIicPs *InstancePtr) void XIicPs_SlaveInterruptHandler(XIicPs *InstancePtr)
{ {
volatile u32 IntrStatusReg; u32 IntrStatusReg;
u32 IsSend = 0; u32 IsSend = 0U;
u32 StatusEvent = 0; u32 StatusEvent = 0U;
int LeftOver; s32 LeftOver;
u32 BaseAddr; u32 BaseAddr;
/* /*
* Assert validates the input arguments. * Assert validates the input arguments.
*/ */
Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
BaseAddr = InstancePtr->Config.BaseAddress; BaseAddr = InstancePtr->Config.BaseAddress;
@ -465,7 +476,7 @@ void XIicPs_SlaveInterruptHandler(XIicPs *InstancePtr)
* Determine whether the device is sending. * Determine whether the device is sending.
*/ */
if (InstancePtr->RecvBufferPtr == NULL) { if (InstancePtr->RecvBufferPtr == NULL) {
IsSend = 1; IsSend = 1U;
} }
/* Data interrupt /* Data interrupt
@ -473,8 +484,8 @@ void XIicPs_SlaveInterruptHandler(XIicPs *InstancePtr)
* This means master wants to do more data transfers. * This means master wants to do more data transfers.
* Also check for completion of transfer, signal upper layer if done. * Also check for completion of transfer, signal upper layer if done.
*/ */
if (0 != (IntrStatusReg & XIICPS_IXR_DATA_MASK)) { if ((u32)0U != (IntrStatusReg & XIICPS_IXR_DATA_MASK)) {
if (IsSend) { if (IsSend != 0x0U) {
LeftOver = TransmitFifoFill(InstancePtr); LeftOver = TransmitFifoFill(InstancePtr);
/* /*
* We may finish send here * We may finish send here
@ -499,8 +510,8 @@ void XIicPs_SlaveInterruptHandler(XIicPs *InstancePtr)
* In slave mode, it means the master has done with this transfer, so * In slave mode, it means the master has done with this transfer, so
* we signal the application using completion event. * we signal the application using completion event.
*/ */
if (0 != (IntrStatusReg & XIICPS_IXR_COMP_MASK)) { if (0U != (IntrStatusReg & XIICPS_IXR_COMP_MASK)) {
if (IsSend) { if (IsSend != 0x0U) {
if (InstancePtr->SendByteCount > 0) { if (InstancePtr->SendByteCount > 0) {
StatusEvent |= XIICPS_EVENT_ERROR; StatusEvent |= XIICPS_EVENT_ERROR;
}else { }else {
@ -519,15 +530,15 @@ void XIicPs_SlaveInterruptHandler(XIicPs *InstancePtr)
/* /*
* Nack interrupt, pass this information to application. * Nack interrupt, pass this information to application.
*/ */
if (0 != (IntrStatusReg & XIICPS_IXR_NACK_MASK)) { if (0U != (IntrStatusReg & XIICPS_IXR_NACK_MASK)) {
StatusEvent |= XIICPS_EVENT_NACK; StatusEvent |= XIICPS_EVENT_NACK;
} }
/* /*
* All other interrupts are treated as error. * All other interrupts are treated as error.
*/ */
if (0 != (IntrStatusReg & (XIICPS_IXR_TO_MASK | if (0U != (IntrStatusReg & (XIICPS_IXR_TO_MASK |
XIICPS_IXR_RX_UNF_MASK | XIICPS_IXR_RX_UNF_MASK |
XIICPS_IXR_TX_OVR_MASK | XIICPS_IXR_TX_OVR_MASK |
XIICPS_IXR_RX_OVR_MASK))){ XIICPS_IXR_RX_OVR_MASK))){
@ -537,7 +548,7 @@ void XIicPs_SlaveInterruptHandler(XIicPs *InstancePtr)
/* /*
* Signal application if there are any events. * Signal application if there are any events.
*/ */
if (0 != StatusEvent) { if (0U != StatusEvent) {
InstancePtr->StatusHandler(InstancePtr->CallBackRef, InstancePtr->StatusHandler(InstancePtr->CallBackRef,
StatusEvent); StatusEvent);
} }
@ -556,17 +567,17 @@ void XIicPs_SlaveInterruptHandler(XIicPs *InstancePtr)
* @note None. * @note None.
* *
****************************************************************************/ ****************************************************************************/
static int SlaveRecvData(XIicPs *InstancePtr) static s32 SlaveRecvData(XIicPs *InstancePtr)
{ {
volatile u32 StatusReg; u32 StatusReg;
u32 BaseAddr; u32 BaseAddr;
BaseAddr = InstancePtr->Config.BaseAddress; BaseAddr = InstancePtr->Config.BaseAddress;
StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET); StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
while ((StatusReg & XIICPS_SR_RXDV_MASK) && while (((StatusReg & XIICPS_SR_RXDV_MASK)!=0x0U) &&
(InstancePtr->RecvByteCount > 0)) { ((InstancePtr->RecvByteCount > 0) != 0x0U)) {
XIicPs_RecvByte(InstancePtr); XIicPs_RecvByte(InstancePtr);
StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET); StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
} }