ttcps_v3_0 : Modified ttcps driver for MISRA-C:2012
This patch modifies ttcps_v3_0 driver for misrac rules. Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
This commit is contained in:
Venkata Naga Sai Krishna Kolapalli
Suneel Garapati
parent
9270b68a0a
commit
b4b7a5330d
7 changed files with 166 additions and 149 deletions
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@ -101,9 +101,11 @@
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* initialize it.
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*
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******************************************************************************/
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int XTtcPs_CfgInitialize(XTtcPs *InstancePtr, XTtcPs_Config *ConfigPtr,
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s32 XTtcPs_CfgInitialize(XTtcPs *InstancePtr, XTtcPs_Config *ConfigPtr,
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u32 EffectiveAddr)
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{
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s32 Status;
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u32 IsStartResult;
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/*
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* Assert to validate input arguments.
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*/
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@ -117,47 +119,48 @@ int XTtcPs_CfgInitialize(XTtcPs *InstancePtr, XTtcPs_Config *ConfigPtr,
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InstancePtr->Config.BaseAddress = EffectiveAddr;
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InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz;
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IsStartResult = XTtcPs_IsStarted(InstancePtr);
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/*
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* If the timer counter has already started, return an error
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* Device should be stopped first.
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*/
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if(XTtcPs_IsStarted(InstancePtr)) {
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return XST_DEVICE_IS_STARTED;
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if(IsStartResult == (u32)TRUE) {
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Status = XST_DEVICE_IS_STARTED;
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} else {
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/*
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* Reset the count control register to it's default value.
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*/
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XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
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XTTCPS_CNT_CNTRL_OFFSET,
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XTTCPS_CNT_CNTRL_RESET_VALUE);
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/*
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* Reset the rest of the registers to the default values.
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*/
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XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
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XTTCPS_CLK_CNTRL_OFFSET, 0x00U);
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XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
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XTTCPS_INTERVAL_VAL_OFFSET, 0x00U);
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XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
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XTTCPS_MATCH_1_OFFSET, 0x00U);
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XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
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XTTCPS_MATCH_2_OFFSET, 0x00U);
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XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
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XTTCPS_MATCH_2_OFFSET, 0x00U);
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XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
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XTTCPS_IER_OFFSET, 0x00U);
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XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
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XTTCPS_ISR_OFFSET, XTTCPS_IXR_ALL_MASK);
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InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
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/*
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* Reset the counter value
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*/
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XTtcPs_ResetCounterValue(InstancePtr);
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Status = XST_SUCCESS;
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}
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/*
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* Reset the count control register to it's default value.
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*/
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XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
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XTTCPS_CNT_CNTRL_OFFSET,
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XTTCPS_CNT_CNTRL_RESET_VALUE);
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/*
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* Reset the rest of the registers to the default values.
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*/
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XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
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XTTCPS_CLK_CNTRL_OFFSET, 0x00);
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XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
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XTTCPS_INTERVAL_VAL_OFFSET, 0x00);
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XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
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XTTCPS_MATCH_1_OFFSET, 0x00);
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XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
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XTTCPS_MATCH_2_OFFSET, 0x00);
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XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
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XTTCPS_MATCH_2_OFFSET, 0x00);
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XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
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XTTCPS_IER_OFFSET, 0x00);
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XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
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XTTCPS_ISR_OFFSET, XTTCPS_IXR_ALL_MASK);
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InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
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/*
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* Reset the counter value
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*/
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XTtcPs_ResetCounterValue(InstancePtr);
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return XST_SUCCESS;
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return Status;
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}
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/*****************************************************************************/
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@ -188,7 +191,7 @@ void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, u16 Value)
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*/
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Xil_AssertVoid(InstancePtr != NULL);
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Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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Xil_AssertVoid(MatchIndex < XTTCPS_NUM_MATCH_REG);
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Xil_AssertVoid(MatchIndex < (u8)XTTCPS_NUM_MATCH_REG);
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/*
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* Write the value to the correct match register with MatchIndex
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@ -275,9 +278,9 @@ void XTtcPs_SetPrescaler(XTtcPs *InstancePtr, u8 PrescalerValue)
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/*
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* Set the prescaler value and enable prescaler
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*/
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ClockReg |= (PrescalerValue << XTTCPS_CLK_CNTRL_PS_VAL_SHIFT) &
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XTTCPS_CLK_CNTRL_PS_VAL_MASK;
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ClockReg |= XTTCPS_CLK_CNTRL_PS_EN_MASK;
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ClockReg |= (u32)(((u32)PrescalerValue << (u32)XTTCPS_CLK_CNTRL_PS_VAL_SHIFT) &
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(u32)XTTCPS_CLK_CNTRL_PS_VAL_MASK);
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ClockReg |= (u32)XTTCPS_CLK_CNTRL_PS_EN_MASK;
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}
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/*
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@ -311,6 +314,7 @@ void XTtcPs_SetPrescaler(XTtcPs *InstancePtr, u8 PrescalerValue)
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****************************************************************************/
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u8 XTtcPs_GetPrescaler(XTtcPs *InstancePtr)
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{
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u8 Status;
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u32 ClockReg;
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/*
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@ -329,11 +333,14 @@ u8 XTtcPs_GetPrescaler(XTtcPs *InstancePtr)
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/*
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* Prescaler is disabled. Return the correct flag value
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*/
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return XTTCPS_CLK_CNTRL_PS_DISABLE;
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Status = (u8)XTTCPS_CLK_CNTRL_PS_DISABLE;
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}
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else {
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return ((ClockReg & XTTCPS_CLK_CNTRL_PS_VAL_MASK) >>
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XTTCPS_CLK_CNTRL_PS_VAL_SHIFT);
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Status = (u8)((ClockReg & (u32)XTTCPS_CLK_CNTRL_PS_VAL_MASK) >>
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(u32)XTTCPS_CLK_CNTRL_PS_VAL_SHIFT);
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}
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return Status;
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}
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/*****************************************************************************/
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@ -374,41 +381,41 @@ void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
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*/
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TempValue = InputClock/ Freq;
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if (TempValue < 4) {
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if (TempValue < 4U) {
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/*
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* The frequency is too high, it is too close to the input
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* clock value. Use maximum values to signal caller.
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*/
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*Interval = 0xFFFF;
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*Prescaler = 0xFF;
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*Interval = 0xFFFFU;
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*Prescaler = 0xFFU;
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return;
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}
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/*
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* First, do we need a prescaler or not?
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*/
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if (65536 > TempValue) {
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if (((u32)65536U) > TempValue) {
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/*
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* We do not need a prescaler, so set the values appropriately
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*/
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*Interval = TempValue;
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*Interval = (u16)TempValue;
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*Prescaler = XTTCPS_CLK_CNTRL_PS_DISABLE;
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return;
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}
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for (TmpPrescaler = 0; TmpPrescaler < XTTCPS_CLK_CNTRL_PS_DISABLE;
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for (TmpPrescaler = 0U; TmpPrescaler < XTTCPS_CLK_CNTRL_PS_DISABLE;
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TmpPrescaler++) {
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TempValue = InputClock/ (Freq * (1 << (TmpPrescaler + 1)));
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TempValue = InputClock/ (Freq * (1U << (TmpPrescaler + 1U)));
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/*
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* The first value less than 2^16 is the best bet
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*/
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if (65536 > TempValue) {
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if (((u32)65536U) > TempValue) {
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/*
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* Set the values appropriately
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*/
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*Interval = TempValue;
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*Interval = (u16)TempValue;
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*Prescaler = TmpPrescaler;
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return;
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}
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@ -417,7 +424,7 @@ void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
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/* Can not find interval values that work for the given frequency.
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* Return maximum values to signal caller.
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*/
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*Interval = 0XFFFF;
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*Prescaler = 0XFF;
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*Interval = 0XFFFFU;
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*Prescaler = 0XFFU;
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return;
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}
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@ -112,14 +112,14 @@ extern "C" {
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*
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* @{
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*/
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#define XTTCPS_OPTION_EXTERNAL_CLK 0x0001 /**< External clock source */
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#define XTTCPS_OPTION_CLK_EDGE_NEG 0x0002 /**< Clock on trailing edge for
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#define XTTCPS_OPTION_EXTERNAL_CLK 0x00000001U /**< External clock source */
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#define XTTCPS_OPTION_CLK_EDGE_NEG 0x00000002U /**< Clock on trailing edge for
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external clock*/
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#define XTTCPS_OPTION_INTERVAL_MODE 0x0004 /**< Interval mode */
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#define XTTCPS_OPTION_DECREMENT 0x0008 /**< Decrement the counter */
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#define XTTCPS_OPTION_MATCH_MODE 0x0010 /**< Match mode */
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#define XTTCPS_OPTION_WAVE_DISABLE 0x0020 /**< No waveform output */
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#define XTTCPS_OPTION_WAVE_POLARITY 0x0040 /**< Waveform polarity */
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#define XTTCPS_OPTION_INTERVAL_MODE 0x00000004U /**< Interval mode */
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#define XTTCPS_OPTION_DECREMENT 0x00000008U /**< Decrement the counter */
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#define XTTCPS_OPTION_MATCH_MODE 0x00000010U /**< Match mode */
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#define XTTCPS_OPTION_WAVE_DISABLE 0x00000020U /**< No waveform output */
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#define XTTCPS_OPTION_WAVE_POLARITY 0x00000040U /**< Waveform polarity */
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/*@}*/
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/**************************** Type Definitions *******************************/
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@ -151,10 +151,10 @@ typedef struct {
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* Internal helper macros
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*/
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#define InstReadReg(InstancePtr, RegOffset) \
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(Xil_In32(((InstancePtr)->Config.BaseAddress) + (RegOffset)))
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(Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)(RegOffset)))
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#define InstWriteReg(InstancePtr, RegOffset, Data) \
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(Xil_Out32(((InstancePtr)->Config.BaseAddress) + (RegOffset), (Data)))
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(Xil_Out32(((InstancePtr)->Config.BaseAddress) + (u32)(RegOffset), (u32)(Data)))
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/*****************************************************************************/
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/**
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@ -208,8 +208,8 @@ typedef struct {
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*
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****************************************************************************/
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#define XTtcPs_IsStarted(InstancePtr) \
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(int)((InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) & \
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XTTCPS_CNT_CNTRL_DIS_MASK) == 0)
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((InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) & \
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XTTCPS_CNT_CNTRL_DIS_MASK) == 0U)
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/*****************************************************************************/
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/**
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@ -280,7 +280,7 @@ typedef struct {
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#define XTtcPs_ResetCounterValue(InstancePtr) \
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InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET, \
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(InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) | \
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XTTCPS_CNT_CNTRL_RST_MASK))
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(u32)XTTCPS_CNT_CNTRL_RST_MASK))
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/*****************************************************************************/
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/**
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@ -377,7 +377,7 @@ XTtcPs_Config *XTtcPs_LookupConfig(u16 DeviceId);
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/*
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* Required functions, in xttcps.c
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*/
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int XTtcPs_CfgInitialize(XTtcPs *InstancePtr,
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s32 XTtcPs_CfgInitialize(XTtcPs *InstancePtr,
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XTtcPs_Config * ConfigPtr, u32 EffectiveAddr);
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void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, u16 Value);
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@ -392,13 +392,13 @@ void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
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/*
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* Functions for options, in file xttcps_options.c
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*/
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int XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options);
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s32 XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options);
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u32 XTtcPs_GetOptions(XTtcPs *InstancePtr);
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/*
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* Function for self-test, in file xttcps_selftest.c
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*/
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int XTtcPs_SelfTest(XTtcPs *InstancePtr);
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s32 XTtcPs_SelfTest(XTtcPs *InstancePtr);
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#ifdef __cplusplus
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}
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@ -73,47 +73,47 @@
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*/
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XTtcPs_Config XTtcPs_ConfigTable[XPAR_XTTCPS_NUM_INSTANCES] = {
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{
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XPAR_XTTCPS_0_DEVICE_ID, /* Device ID for instance */
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XPAR_XTTCPS_0_BASEADDR, /* Device base address */
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XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ /* Device input clock frequency */
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(u16)XPAR_XTTCPS_0_DEVICE_ID, /* Device ID for instance */
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(u32)XPAR_XTTCPS_0_BASEADDR, /* Device base address */
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(u32)XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ /* Device input clock frequency */
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},
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#ifdef XPAR_XTTCPS_1_DEVICE_ID
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{
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XPAR_XTTCPS_1_DEVICE_ID, /* Device ID for instance */
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XPAR_XTTCPS_1_BASEADDR, /* Device base address */
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XPAR_XTTCPS_1_CLOCK_HZ /* Device input clock frequency */
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(u16)XPAR_XTTCPS_1_DEVICE_ID, /* Device ID for instance */
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(u32)XPAR_XTTCPS_1_BASEADDR, /* Device base address */
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(u32)XPAR_XTTCPS_1_CLOCK_HZ /* Device input clock frequency */
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},
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#endif
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#ifdef XPAR_XTTCPS_2_DEVICE_ID
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{
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XPAR_XTTCPS_2_DEVICE_ID, /* Device ID for instance */
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XPAR_XTTCPS_2_BASEADDR, /* Device base address */
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XPAR_XTTCPS_2_CLOCK_HZ /* Device input clock frequency */
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(u16)XPAR_XTTCPS_2_DEVICE_ID, /* Device ID for instance */
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(u32)XPAR_XTTCPS_2_BASEADDR, /* Device base address */
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(u32)XPAR_XTTCPS_2_CLOCK_HZ /* Device input clock frequency */
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},
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#endif
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#ifdef XPAR_XTTCPS_3_DEVICE_ID
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{
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XPAR_XTTCPS_3_DEVICE_ID, /* Device ID for instance */
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XPAR_XTTCPS_3_BASEADDR, /* Device base address */
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XPAR_XTTCPS_3_CLOCK_HZ /* Device input clock frequency */
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(u16)XPAR_XTTCPS_3_DEVICE_ID, /* Device ID for instance */
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(u32)XPAR_XTTCPS_3_BASEADDR, /* Device base address */
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(u32)XPAR_XTTCPS_3_CLOCK_HZ /* Device input clock frequency */
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},
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#endif
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#ifdef XPAR_XTTCPS_4_DEVICE_ID
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{
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XPAR_XTTCPS_4_DEVICE_ID, /* Device ID for instance */
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XPAR_XTTCPS_4_BASEADDR, /* Device base address */
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XPAR_XTTCPS_4_CLOCK_HZ /* Device input clock frequency */
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(u16)XPAR_XTTCPS_4_DEVICE_ID, /* Device ID for instance */
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(u32)XPAR_XTTCPS_4_BASEADDR, /* Device base address */
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(u32)XPAR_XTTCPS_4_CLOCK_HZ /* Device input clock frequency */
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},
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#endif
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#ifdef XPAR_XTTCPS_5_DEVICE_ID
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{
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XPAR_XTTCPS_5_DEVICE_ID, /* Device ID for instance */
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XPAR_XTTCPS_5_BASEADDR, /* Device base address */
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XPAR_XTTCPS_5_CLOCK_HZ /* Device input clock frequency */
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(u16)XPAR_XTTCPS_5_DEVICE_ID, /* Device ID for instance */
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(u32)XPAR_XTTCPS_5_BASEADDR, /* Device base address */
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(u32)XPAR_XTTCPS_5_CLOCK_HZ /* Device input clock frequency */
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},
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#endif
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};
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@ -70,48 +70,48 @@ extern "C" {
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*
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* @{
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*/
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#define XTTCPS_CLK_CNTRL_OFFSET 0x00000000 /**< Clock Control Register */
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#define XTTCPS_CNT_CNTRL_OFFSET 0x0000000C /**< Counter Control Register*/
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#define XTTCPS_COUNT_VALUE_OFFSET 0x00000018 /**< Current Counter Value */
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#define XTTCPS_INTERVAL_VAL_OFFSET 0x00000024 /**< Interval Count Value */
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#define XTTCPS_MATCH_0_OFFSET 0x00000030 /**< Match 1 value */
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#define XTTCPS_MATCH_1_OFFSET 0x0000003C /**< Match 2 value */
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#define XTTCPS_MATCH_2_OFFSET 0x00000048 /**< Match 3 value */
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#define XTTCPS_ISR_OFFSET 0x00000054 /**< Interrupt Status Register */
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#define XTTCPS_IER_OFFSET 0x00000060 /**< Interrupt Enable Register */
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#define XTTCPS_CLK_CNTRL_OFFSET 0x00000000U /**< Clock Control Register */
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#define XTTCPS_CNT_CNTRL_OFFSET 0x0000000CU /**< Counter Control Register*/
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#define XTTCPS_COUNT_VALUE_OFFSET 0x00000018U /**< Current Counter Value */
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#define XTTCPS_INTERVAL_VAL_OFFSET 0x00000024U /**< Interval Count Value */
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#define XTTCPS_MATCH_0_OFFSET 0x00000030U /**< Match 1 value */
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#define XTTCPS_MATCH_1_OFFSET 0x0000003CU /**< Match 2 value */
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#define XTTCPS_MATCH_2_OFFSET 0x00000048U /**< Match 3 value */
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#define XTTCPS_ISR_OFFSET 0x00000054U /**< Interrupt Status Register */
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#define XTTCPS_IER_OFFSET 0x00000060U /**< Interrupt Enable Register */
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/* @} */
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/** @name Clock Control Register
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* Clock Control Register definitions
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* @{
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*/
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#define XTTCPS_CLK_CNTRL_PS_EN_MASK 0x00000001 /**< Prescale enable */
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#define XTTCPS_CLK_CNTRL_PS_VAL_MASK 0x0000001E /**< Prescale value */
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#define XTTCPS_CLK_CNTRL_PS_VAL_SHIFT 1 /**< Prescale shift */
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#define XTTCPS_CLK_CNTRL_PS_DISABLE 16 /**< Prescale disable */
|
||||
#define XTTCPS_CLK_CNTRL_SRC_MASK 0x00000020 /**< Clock source */
|
||||
#define XTTCPS_CLK_CNTRL_EXT_EDGE_MASK 0x00000040 /**< External Clock edge */
|
||||
#define XTTCPS_CLK_CNTRL_PS_EN_MASK 0x00000001U /**< Prescale enable */
|
||||
#define XTTCPS_CLK_CNTRL_PS_VAL_MASK 0x0000001EU /**< Prescale value */
|
||||
#define XTTCPS_CLK_CNTRL_PS_VAL_SHIFT 1U /**< Prescale shift */
|
||||
#define XTTCPS_CLK_CNTRL_PS_DISABLE 16U /**< Prescale disable */
|
||||
#define XTTCPS_CLK_CNTRL_SRC_MASK 0x00000020U /**< Clock source */
|
||||
#define XTTCPS_CLK_CNTRL_EXT_EDGE_MASK 0x00000040U /**< External Clock edge */
|
||||
/* @} */
|
||||
|
||||
/** @name Counter Control Register
|
||||
* Counter Control Register definitions
|
||||
* @{
|
||||
*/
|
||||
#define XTTCPS_CNT_CNTRL_DIS_MASK 0x00000001 /**< Disable the counter */
|
||||
#define XTTCPS_CNT_CNTRL_INT_MASK 0x00000002 /**< Interval mode */
|
||||
#define XTTCPS_CNT_CNTRL_DECR_MASK 0x00000004 /**< Decrement mode */
|
||||
#define XTTCPS_CNT_CNTRL_MATCH_MASK 0x00000008 /**< Match mode */
|
||||
#define XTTCPS_CNT_CNTRL_RST_MASK 0x00000010 /**< Reset counter */
|
||||
#define XTTCPS_CNT_CNTRL_EN_WAVE_MASK 0x00000020 /**< Enable waveform */
|
||||
#define XTTCPS_CNT_CNTRL_POL_WAVE_MASK 0x00000040 /**< Waveform polarity */
|
||||
#define XTTCPS_CNT_CNTRL_RESET_VALUE 0x00000021 /**< Reset value */
|
||||
#define XTTCPS_CNT_CNTRL_DIS_MASK 0x00000001U /**< Disable the counter */
|
||||
#define XTTCPS_CNT_CNTRL_INT_MASK 0x00000002U /**< Interval mode */
|
||||
#define XTTCPS_CNT_CNTRL_DECR_MASK 0x00000004U /**< Decrement mode */
|
||||
#define XTTCPS_CNT_CNTRL_MATCH_MASK 0x00000008U /**< Match mode */
|
||||
#define XTTCPS_CNT_CNTRL_RST_MASK 0x00000010U /**< Reset counter */
|
||||
#define XTTCPS_CNT_CNTRL_EN_WAVE_MASK 0x00000020U /**< Enable waveform */
|
||||
#define XTTCPS_CNT_CNTRL_POL_WAVE_MASK 0x00000040U /**< Waveform polarity */
|
||||
#define XTTCPS_CNT_CNTRL_RESET_VALUE 0x00000021U /**< Reset value */
|
||||
/* @} */
|
||||
|
||||
/** @name Current Counter Value Register
|
||||
* Current Counter Value Register definitions
|
||||
* @{
|
||||
*/
|
||||
#define XTTCPS_COUNT_VALUE_MASK 0x0000FFFF /**< 16-bit counter value */
|
||||
#define XTTCPS_COUNT_VALUE_MASK 0x0000FFFFU /**< 16-bit counter value */
|
||||
/* @} */
|
||||
|
||||
/** @name Interval Value Register
|
||||
|
|
@ -119,7 +119,7 @@ extern "C" {
|
|||
* down to.
|
||||
* @{
|
||||
*/
|
||||
#define XTTCPS_INTERVAL_VAL_MASK 0x0000FFFF /**< 16-bit Interval value*/
|
||||
#define XTTCPS_INTERVAL_VAL_MASK 0x0000FFFFU /**< 16-bit Interval value*/
|
||||
/* @} */
|
||||
|
||||
/** @name Match Registers
|
||||
|
|
@ -127,8 +127,8 @@ extern "C" {
|
|||
* registers.
|
||||
* @{
|
||||
*/
|
||||
#define XTTCPS_MATCH_MASK 0x0000FFFF /**< 16-bit Match value */
|
||||
#define XTTCPS_NUM_MATCH_REG 3 /**< Num of Match reg */
|
||||
#define XTTCPS_MATCH_MASK 0x0000FFFFU /**< 16-bit Match value */
|
||||
#define XTTCPS_NUM_MATCH_REG 3U /**< Num of Match reg */
|
||||
/* @} */
|
||||
|
||||
/** @name Interrupt Registers
|
||||
|
|
@ -136,12 +136,12 @@ extern "C" {
|
|||
*
|
||||
* @{
|
||||
*/
|
||||
#define XTTCPS_IXR_INTERVAL_MASK 0x00000001 /**< Interval Interrupt */
|
||||
#define XTTCPS_IXR_MATCH_0_MASK 0x00000002 /**< Match 1 Interrupt */
|
||||
#define XTTCPS_IXR_MATCH_1_MASK 0x00000004 /**< Match 2 Interrupt */
|
||||
#define XTTCPS_IXR_MATCH_2_MASK 0x00000008 /**< Match 3 Interrupt */
|
||||
#define XTTCPS_IXR_CNT_OVR_MASK 0x00000010 /**< Counter Overflow */
|
||||
#define XTTCPS_IXR_ALL_MASK 0x0000001F /**< All valid Interrupts */
|
||||
#define XTTCPS_IXR_INTERVAL_MASK 0x00000001U /**< Interval Interrupt */
|
||||
#define XTTCPS_IXR_MATCH_0_MASK 0x00000002U /**< Match 1 Interrupt */
|
||||
#define XTTCPS_IXR_MATCH_1_MASK 0x00000004U /**< Match 2 Interrupt */
|
||||
#define XTTCPS_IXR_MATCH_2_MASK 0x00000008U /**< Match 3 Interrupt */
|
||||
#define XTTCPS_IXR_CNT_OVR_MASK 0x00000010U /**< Counter Overflow */
|
||||
#define XTTCPS_IXR_ALL_MASK 0x0000001FU /**< All valid Interrupts */
|
||||
/* @} */
|
||||
|
||||
|
||||
|
|
@ -162,7 +162,7 @@ extern "C" {
|
|||
*
|
||||
*****************************************************************************/
|
||||
#define XTtcPs_ReadReg(BaseAddress, RegOffset) \
|
||||
(Xil_In32((BaseAddress) + (RegOffset)))
|
||||
(Xil_In32((BaseAddress) + (u32)(RegOffset)))
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
|
|
@ -181,7 +181,7 @@ extern "C" {
|
|||
*
|
||||
*****************************************************************************/
|
||||
#define XTtcPs_WriteReg(BaseAddress, RegOffset, Data) \
|
||||
(Xil_Out32((BaseAddress) + (RegOffset), (Data)))
|
||||
(Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data)))
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
|
|
@ -197,7 +197,7 @@ extern "C" {
|
|||
*
|
||||
*****************************************************************************/
|
||||
#define XTtcPs_Match_N_Offset(MatchIndex) \
|
||||
(XTTCPS_MATCH_0_OFFSET + (12 * (MatchIndex)))
|
||||
((u32)XTTCPS_MATCH_0_OFFSET + ((u32)(12U) * (u32)(MatchIndex)))
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
|
|
|
|||
|
|
@ -116,11 +116,12 @@ static OptionsMap TmrCtrOptionsTable[] = {
|
|||
* @note None
|
||||
*
|
||||
******************************************************************************/
|
||||
int XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options)
|
||||
s32 XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options)
|
||||
{
|
||||
u32 CountReg;
|
||||
u32 ClockReg;
|
||||
unsigned Index;
|
||||
u32 Index;
|
||||
s32 Status = XST_SUCCESS;
|
||||
|
||||
Xil_AssertNonvoid(InstancePtr != NULL);
|
||||
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
|
|
@ -134,8 +135,9 @@ int XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options)
|
|||
* Loop through the options table, turning the option on or off
|
||||
* depending on whether the bit is set in the incoming options flag.
|
||||
*/
|
||||
for (Index = 0; Index < XTTCPS_NUM_TMRCTR_OPTIONS; Index++) {
|
||||
if (Options & TmrCtrOptionsTable[Index].Option) {
|
||||
for (Index = 0U; Index < XTTCPS_NUM_TMRCTR_OPTIONS; Index++) {
|
||||
if(Status != (s32)XST_FAILURE) {
|
||||
if ((Options & TmrCtrOptionsTable[Index].Option) != (u32)0) {
|
||||
|
||||
switch (TmrCtrOptionsTable[Index].Register) {
|
||||
|
||||
|
|
@ -150,7 +152,8 @@ int XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options)
|
|||
break;
|
||||
|
||||
default:
|
||||
return XST_FAILURE;
|
||||
Status = XST_FAILURE;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else {
|
||||
|
|
@ -167,7 +170,9 @@ int XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options)
|
|||
break;
|
||||
|
||||
default:
|
||||
return XST_FAILURE;
|
||||
Status = XST_FAILURE;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -176,12 +181,14 @@ int XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options)
|
|||
* Now write the registers. Leave it to the upper layers to restart the
|
||||
* device.
|
||||
*/
|
||||
XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
|
||||
XTTCPS_CLK_CNTRL_OFFSET, ClockReg);
|
||||
XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
|
||||
XTTCPS_CNT_CNTRL_OFFSET, CountReg);
|
||||
if (Status != (s32)XST_FAILURE ) {
|
||||
XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
|
||||
XTTCPS_CLK_CNTRL_OFFSET, ClockReg);
|
||||
XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
|
||||
XTTCPS_CNT_CNTRL_OFFSET, CountReg);
|
||||
}
|
||||
|
||||
return XST_SUCCESS;
|
||||
return Status;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
|
|
@ -203,9 +210,9 @@ int XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options)
|
|||
******************************************************************************/
|
||||
u32 XTtcPs_GetOptions(XTtcPs *InstancePtr)
|
||||
{
|
||||
u32 OptionsFlag = 0;
|
||||
u32 OptionsFlag = 0U;
|
||||
u32 Register;
|
||||
unsigned Index;
|
||||
u32 Index;
|
||||
|
||||
Xil_AssertNonvoid(InstancePtr != NULL);
|
||||
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
|
|
@ -214,7 +221,7 @@ u32 XTtcPs_GetOptions(XTtcPs *InstancePtr)
|
|||
/*
|
||||
* Loop through the options table to determine which options are set
|
||||
*/
|
||||
for (Index = 0; Index < XTTCPS_NUM_TMRCTR_OPTIONS; Index++) {
|
||||
for (Index = 0U; Index < XTTCPS_NUM_TMRCTR_OPTIONS; Index++) {
|
||||
/*
|
||||
* Get the control register to determine which options are
|
||||
* currently set.
|
||||
|
|
@ -223,7 +230,7 @@ u32 XTtcPs_GetOptions(XTtcPs *InstancePtr)
|
|||
TmrCtrOptionsTable[Index].
|
||||
Register);
|
||||
|
||||
if (Register & TmrCtrOptionsTable[Index].Mask) {
|
||||
if ((Register & TmrCtrOptionsTable[Index].Mask) != (u32)0) {
|
||||
OptionsFlag |= TmrCtrOptionsTable[Index].Option;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -82,8 +82,9 @@
|
|||
* @note This test fails if it is not called right after initialization.
|
||||
*
|
||||
******************************************************************************/
|
||||
int XTtcPs_SelfTest(XTtcPs *InstancePtr)
|
||||
s32 XTtcPs_SelfTest(XTtcPs *InstancePtr)
|
||||
{
|
||||
s32 Status;
|
||||
u32 TempReg;
|
||||
|
||||
Xil_AssertNonvoid(InstancePtr != NULL);
|
||||
|
|
@ -94,9 +95,11 @@ int XTtcPs_SelfTest(XTtcPs *InstancePtr)
|
|||
*/
|
||||
TempReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
|
||||
XTTCPS_CNT_CNTRL_OFFSET);
|
||||
if (XTTCPS_CNT_CNTRL_RESET_VALUE != TempReg) {
|
||||
return XST_FAILURE;
|
||||
if (XTTCPS_CNT_CNTRL_RESET_VALUE != (u32)TempReg) {
|
||||
Status = XST_FAILURE;
|
||||
}
|
||||
|
||||
return XST_SUCCESS;
|
||||
else {
|
||||
Status = XST_SUCCESS;
|
||||
}
|
||||
return Status;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -48,8 +48,8 @@
|
|||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xparameters.h"
|
||||
#include "xttcps.h"
|
||||
#include "xparameters.h"
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
|
|
@ -60,7 +60,7 @@
|
|||
/************************** Function Prototypes ******************************/
|
||||
|
||||
/************************** Variable Definitions *****************************/
|
||||
extern XTtcPs_Config XTtcPs_ConfigTable[];
|
||||
extern XTtcPs_Config XTtcPs_ConfigTable[XPAR_XTTCPS_NUM_INSTANCES];
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
|
|
@ -81,14 +81,14 @@ extern XTtcPs_Config XTtcPs_ConfigTable[];
|
|||
XTtcPs_Config *XTtcPs_LookupConfig(u16 DeviceId)
|
||||
{
|
||||
XTtcPs_Config *CfgPtr = NULL;
|
||||
unsigned Index;
|
||||
u32 Index;
|
||||
|
||||
for (Index = 0; Index < XPAR_XTTCPS_NUM_INSTANCES; Index++) {
|
||||
for (Index = 0U; Index < (u32)XPAR_XTTCPS_NUM_INSTANCES; Index++) {
|
||||
if (XTtcPs_ConfigTable[Index].DeviceId == DeviceId) {
|
||||
CfgPtr = &XTtcPs_ConfigTable[Index];
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return CfgPtr;
|
||||
return (XTtcPs_Config *)CfgPtr;
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue