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dptx: Fixed a bit mask.

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Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
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Andrei-Liviu Simion 2015-01-07 13:48:15 -08:00 • committed by Suneel Garapati
parent b52732ead1
commit b529cc05c6
1 changed files with 1 additions and 1 deletions
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2
XilinxProcessorIPLib/drivers/dptx/src/xdptx_hw.h
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@ -667,7 +667,7 @@
0x00000020 /**< PLL locked for lanes
2 and 3. */
#define XDPTX_PHY_STATUS_PLL_FABRIC_LOCK_MASK \
0x00000020 /**< FPGA fabric clock PLL
0x00000040 /**< FPGA fabric clock PLL
locked. */
#define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_0_MASK \
0x00030000 /**< TX buffer status lane 0. */