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dp: tx: 4K2K reduced blanking requires line reset disable.

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Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Acked-by: K Krishna Deepak <kde@xilinx.com>
This commit is contained in:
Andrei-Liviu Simion 2015-09-01 17:56:33 -07:00 • committed by Nava kishore Manne
parent e1ce03e43a
commit b85e4c0b2e
1 changed files with 6 additions and 1 deletions
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7
XilinxProcessorIPLib/drivers/dp/src/xdp_spm.c
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@ -501,7 +501,7 @@ void XDp_TxCfgMsaUseCustom(XDp *InstancePtr, u8 Stream,
/* Copy the MSA values from the user configuration structure. */ /* Copy the MSA values from the user configuration structure. */
MsaConfig->PixelClockHz = MsaConfigCustom->PixelClockHz; MsaConfig->PixelClockHz = MsaConfigCustom->PixelClockHz;
MsaConfig->Vtm.VmId = MsaConfigCustom->Vtm.VmId; MsaConfig->Vtm.VmId = XVIDC_VM_CUSTOM;
MsaConfig->Vtm.FrameRate = MsaConfigCustom->Vtm.FrameRate; MsaConfig->Vtm.FrameRate = MsaConfigCustom->Vtm.FrameRate;
MsaConfig->Vtm.Timing.HActive = MsaConfig->Vtm.Timing.HActive =
MsaConfigCustom->Vtm.Timing.HActive; MsaConfigCustom->Vtm.Timing.HActive;
@ -806,6 +806,11 @@ void XDp_TxSetMsaValues(XDp *InstancePtr, u8 Stream)
StreamOffset[Stream - 1], MsaConfig->UserPixelWidth); StreamOffset[Stream - 1], MsaConfig->UserPixelWidth);
XDp_WriteReg(ConfigPtr->BaseAddr, XDP_TX_USER_DATA_COUNT_PER_LANE + XDp_WriteReg(ConfigPtr->BaseAddr, XDP_TX_USER_DATA_COUNT_PER_LANE +
StreamOffset[Stream - 1], MsaConfig->DataPerLane); StreamOffset[Stream - 1], MsaConfig->DataPerLane);
/* Disable the end of line reset to the internal video pipe in case of
* 4K2K reduced blanking. */
XDp_WriteReg(ConfigPtr->BaseAddr, XDP_TX_LINE_RESET_DISABLE,
(MsaConfig->Vtm.VmId == XVIDC_VM_4K2K_60_P_RB) ?
XDP_TX_LINE_RESET_DISABLE_MASK : 0);
/* Set the transfer unit values to the associated DisplayPort TX core /* Set the transfer unit values to the associated DisplayPort TX core
* registers. */ * registers. */