xilskey: Added BBRAM PS functionality
Added BBRAM PS programming APIs for Zynq MP platform In BBRAM there is no provision for saperate CRC check CRC check can be performed only while programming AES key So user no need to calculate CRC of key if they provide key for programming CRC check will also be performed internally. User can also make BBRAM key to Zero at any time. Signed-off-by: VNSL Durga <vnsldurg@xilinx.com> Reviewed-by: Harini Katakam <harinik@xilinx.com>
This commit is contained in:
VNSL Durga
Nava kishore Manne
parent
e7aeea3a1f
commit
b92437c68b
4 changed files with 670 additions and 2 deletions
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@ -1,6 +1,6 @@
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/******************************************************************************
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*
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* Copyright (C) 2013 - 2014 Xilinx, Inc. All rights reserved.
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* Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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@ -44,6 +44,7 @@
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* Ver Who Date Changes
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* ----- ---- -------- --------------------------------------------------------
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* 1.01a hk 09/18/13 First release
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* 4.0 vns 10/08/15 Added prototypes for ZynqMp BBRAM PS
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*
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****************************************************************************/
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#ifndef XILSKEY_BBRAM_H
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@ -192,10 +193,14 @@ typedef struct {
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/************************** Function Prototypes *****************************/
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/*
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* Function for BBRAM program and vefiry algorithm
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* Function for BBRAM program and verify algorithm
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*/
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int XilSKey_Bbram_Program(XilSKey_Bbram *InstancePtr);
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/* Functions to program AES key and function to zeroise AES key */
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u32 XilSKey_ZynqMp_Bbram_Program(u32 *AesKey);
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void XilSKey_ZynqMp_Bbram_Zeroise();
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#ifdef __cplusplus
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}
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#endif
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@ -547,6 +547,20 @@ typedef enum {
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}XSKEfusePs_ErrorCodes;
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/**
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* ZynqMP PS BBRAM error codes
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*/
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typedef enum {
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XSK_ZYNQMP_BBRAMPS_ERROR_NONE = 0,
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XSK_ZYNQMP_BBRAMPS_ERROR_IN_PRGRMG_ENABLE = 0x01, /**< If this error is occurred
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* programming is not
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* possible */
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XSK_ZYNQMP_BBRAMPS_ERROR_IN_CRC_CHECK = 0xB000, /**< If this error is occurred
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* programming is done but CRC
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* check is failed */
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XSK_ZYNQMP_BBRAMPS_ERROR_IN_PRGRMG = 0xC000 /**< programming of key is failed */
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}XskZynqMp_Ps_Bbram_ErrorCodes;
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/*
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* For backward compatibility with old error codes
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*/
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246
lib/sw_services/xilskey/src/xilskey_bbramps_zynqmp.c
Normal file
246
lib/sw_services/xilskey/src/xilskey_bbramps_zynqmp.c
Normal file
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@ -0,0 +1,246 @@
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/******************************************************************************
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*
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* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xilskey_bbramps_zynqmp.c
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*
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* This file contains the implementation of the interface functions for
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* programming BBRAM of ZynqMp.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ------ -------- ------------------------------------------------------
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* 4.0 vns 10/08/15 First release
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* </pre>
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*
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******************************************************************************/
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/***************************** Include Files *********************************/
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#include "xilskey_bbramps_zynqmp_hw.h"
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/***************** Macros (Inline Functions) Definitions *********************/
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/**************************** Type Definitions *******************************/
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/************************** Function Prototypes ******************************/
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static inline u32 XilSKey_ZynqMp_Bbram_PrgrmEn();
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static inline u32 XilSKey_ZynqMp_Bbram_CrcCalc(u32 *AesKey);
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extern u32 XilSKey_RowCrcCalculation(u32 PrevCRC, u32 Data, u32 Addr);
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/************************** Variable Definitions *****************************/
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/************************** Function Definitions *****************************/
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/*****************************************************************************/
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/**
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*
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* This function implements the BBRAM programming and verifying the key written.
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* Program and verification of AES will work only together.
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* CRC of the provided key will be calculated internally and verified.
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*
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* @param AesKey is a pointer to the key which has to be programmed.
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*
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* @return
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* - Error code from XskZynqMp_Ps_Bbram_ErrorCodes enum if it fails
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* - XST_SUCCESS if programming is done.
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*
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* @note None.
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*
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******************************************************************************/
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u32 XilSKey_ZynqMp_Bbram_Program(u32 *AesKey)
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{
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u32 Status = XST_SUCCESS;
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u32 AesCrc;
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u32 *KeyPtr = AesKey;
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u32 StatusRead;
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u32 Offset;
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/* Calculate CRC of AES */
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AesCrc = XilSKey_ZynqMp_Bbram_CrcCalc(AesKey);
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/* Set in programming mode */
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Status = XilSKey_ZynqMp_Bbram_PrgrmEn();
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if (Status != XST_SUCCESS) {
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return (Status + XSK_ZYNQMP_BBRAMPS_ERROR_IN_PRGRMG);
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}
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/* Program with provided key and check key written */
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Offset = XSK_ZYNQMP_BBRAM_0_OFFSET;
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while (Offset <= XSK_ZYNQMP_BBRAM_7_OFFSET) {
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XilSKey_WriteReg(XSK_ZYNQMP_BBRAM_BASEADDR, Offset, *KeyPtr);
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KeyPtr++;
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Offset = Offset + 4;
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}
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XilSKey_WriteReg(XSK_ZYNQMP_BBRAM_BASEADDR,
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XSK_ZYNQMP_BBRAM_AES_CRC_OFFSET, AesCrc);
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/* Check for CRC done */
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StatusRead = XilSKey_ReadReg(XSK_ZYNQMP_BBRAM_BASEADDR,
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XSK_ZYNQMP_BBRAM_STS_OFFSET);
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while ((StatusRead & XSK_ZYNQMP_BBRAM_STS_AES_CRC_DONE_MASK)
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== 0x00) {
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StatusRead =
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XilSKey_ReadReg(XSK_ZYNQMP_BBRAM_BASEADDR,
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XSK_ZYNQMP_BBRAM_STS_OFFSET);
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}
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if ((StatusRead & XSK_ZYNQMP_BBRAM_STS_AES_CRC_PASS_MASK) !=
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XSK_ZYNQMP_BBRAM_STS_AES_CRC_PASS_MASK) {
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return XSK_ZYNQMP_BBRAMPS_ERROR_IN_CRC_CHECK;
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}
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return Status;
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}
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/*****************************************************************************/
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/**
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*
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* This function zeroize's Bbram Key.
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*
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* @param None.
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*
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* @return None.
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*
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* @note BBRAM key will be zeroized.
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*
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******************************************************************************/
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void XilSKey_ZynqMp_Bbram_Zeroise()
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{
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u32 Status;
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XilSKey_WriteReg(XSK_ZYNQMP_BBRAM_BASEADDR, XSK_ZYNQMP_BBRAM_CTRL_OFFSET,
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XSK_ZYNQMP_BBRAM_CTRL_ZEROIZE_MASK);
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Status = XilSKey_ReadReg(XSK_ZYNQMP_BBRAM_BASEADDR,
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XSK_ZYNQMP_BBRAM_STS_OFFSET);
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while ((Status & XSK_ZYNQMP_BBRAM_STS_ZEROIZED_MASK) == 0x00) {
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Status = XilSKey_ReadReg(XSK_ZYNQMP_BBRAM_BASEADDR,
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XSK_ZYNQMP_BBRAM_STS_OFFSET);
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}
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}
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/*****************************************************************************/
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/**
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*
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* This function enables programming and zeroizes Bbram.
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*
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* @param None
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*
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* @return
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* - Error code from XskZynqMp_Ps_Bbram_ErrorCodes enum if it fails
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* - XST_SUCCESS if programming is done.
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*
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* @note None.
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*
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******************************************************************************/
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static inline u32 XilSKey_ZynqMp_Bbram_PrgrmEn()
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{
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u32 Status = XST_SUCCESS;
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u32 StatusRead;
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XilSKey_WriteReg(XSK_ZYNQMP_BBRAM_BASEADDR,
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XSK_ZYNQMP_BBRAM_PGM_MODE_OFFSET,XSK_ZYNQMP_BBRAM_PGM_MODE_SET_VAL);
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/* check for zeroized */
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StatusRead = XilSKey_ReadReg(XSK_ZYNQMP_BBRAM_BASEADDR,
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XSK_ZYNQMP_BBRAM_STS_OFFSET);
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while ((StatusRead & XSK_ZYNQMP_BBRAM_STS_ZEROIZED_MASK) ==
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0x00) {
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StatusRead =
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XilSKey_ReadReg(XSK_ZYNQMP_BBRAM_BASEADDR,
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XSK_ZYNQMP_BBRAM_STS_OFFSET);
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}
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StatusRead =
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XilSKey_ReadReg(XSK_ZYNQMP_BBRAM_BASEADDR,
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XSK_ZYNQMP_BBRAM_STS_OFFSET);
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if ((StatusRead & XSK_ZYNQMP_BBRAM_STS_PGM_MODE_MASK) !=
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XSK_ZYNQMP_BBRAM_STS_PGM_MODE_MASK) {
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return XSK_ZYNQMP_BBRAMPS_ERROR_IN_PRGRMG_ENABLE;
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}
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return Status;
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}
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/*****************************************************************************/
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/**
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*
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* This function calculates CRC of AES key.
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*
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* @param AesKey is a pointer to the key for which CRC has to be
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* calculated.
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*
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* @return CRC of AES key
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*
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* @note None.
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*
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******************************************************************************/
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static inline u32 XilSKey_ZynqMp_Bbram_CrcCalc(u32 *AesKey)
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{
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u32 Crc = 0;
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u32 Index;
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u32 Key_32 = 0;
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for (Index = 0; Index < 9 ; Index++) {
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if (Index != 0) {
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Crc =
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XilSKey_RowCrcCalculation(
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Crc, AesKey[8 - Index], 9-Index);
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}
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else {
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Crc = XilSKey_RowCrcCalculation(Crc, Key_32, 9-Index);
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}
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}
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return Crc;
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}
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403
lib/sw_services/xilskey/src/xilskey_bbramps_zynqmp_hw.h
Normal file
403
lib/sw_services/xilskey/src/xilskey_bbramps_zynqmp_hw.h
Normal file
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@ -0,0 +1,403 @@
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/******************************************************************************
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*
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* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
|
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* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
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*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
|
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* (b) that interact with a Xilinx device through a bus or interconnect.
|
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
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* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
|
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* in advertising or otherwise to promote the sale, use or other dealings in
|
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xilskey_bbramps_zynqmp_hw.h
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*
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* This header file contains identifiers and register-level driver functions (or
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* macros) that can be used to access the Xilinx ZynqMp BBRAM controller.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ------ -------- ------------------------------------------------------
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* 4.0 vns 10/08/15 First release
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* </pre>
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*
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******************************************************************************/
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#ifndef __XSK_BBRAMPS_ZYNQMP_HW_H__
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#define __XSK_BBRAMPS_ZYNQMP_HW_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************** Include Files *********************************/
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#include "xilskey_utils.h"
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#include "xil_io.h"
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#include "xilskey_bbram.h"
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/************************** Constant Definitions *****************************/
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/**************************** Type Definitions *******************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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/** @name Bbram Base Address
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* @{
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*/
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#define XSK_ZYNQMP_BBRAM_BASEADDR 0xFFCD0000U /**< Bbram base address */
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/*@}*/
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/** @name Register: BbramSts
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* @{
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*/
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#define XSK_ZYNQMP_BBRAM_STS_OFFSET 0x00000000U /**< Status
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* register offset */
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#define XSK_ZYNQMP_BBRAM_STS_RSTVAL 0x00000000U /**< Reset value */
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#define XSK_ZYNQMP_BBRAM_STS_AES_CRC_PASS_SHIFT 9U
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/**< AES crc pass shift
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*/
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#define XSK_ZYNQMP_BBRAM_STS_AES_CRC_PASS_WIDTH 1U
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/**< AES crc pass width
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*/
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#define XSK_ZYNQMP_BBRAM_STS_AES_CRC_PASS_MASK 0x00000200U
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/**< AES crc pass
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* mask */
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#define XSK_ZYNQMP_BBRAM_STS_AES_CRC_PASS_DEFVAL 0x0U
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/**< AES crc pass
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* default value */
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#define XSK_ZYNQMP_BBRAM_STS_AES_CRC_DONE_SHIFT 8U
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/**< AES CRC done
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* shift */
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#define XSK_ZYNQMP_BBRAM_STS_AES_CRC_DONE_WIDTH 1U
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/**< AES CRC done
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* width */
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#define XSK_ZYNQMP_BBRAM_STS_AES_CRC_DONE_MASK 0x00000100U
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/**< AES CRC done
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* mask */
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#define XSK_ZYNQMP_BBRAM_STS_AES_CRC_DONE_DEFVAL 0x0U
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/**< AES CRC done
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* default value */
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#define XSK_ZYNQMP_BBRAM_STS_ZEROIZED_SHIFT 4U
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/**< Bbram zeroised
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* shift */
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#define XSK_ZYNQMP_BBRAM_STS_ZEROIZED_WIDTH 1U
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/**< Bbram zeroised
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* width */
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#define XSK_ZYNQMP_BBRAM_STS_ZEROIZED_MASK 0x00000010U
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/**< Bbram zeroised
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* mask */
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#define XSK_ZYNQMP_BBRAM_STS_ZEROIZED_DEFVAL 0x0U
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/**< Bbram zeroised
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* default value */
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#define XSK_ZYNQMP_BBRAM_STS_PGM_MODE_SHIFT 0U
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/**< Bbram prgrmg mode
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* shift */
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#define XSK_ZYNQMP_BBRAM_STS_PGM_MODE_WIDTH 1U
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/**< Bbram prgrmg mode
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* width */
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#define XSK_ZYNQMP_BBRAM_STS_PGM_MODE_MASK 0x00000001U
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/**< Bbram prgrmg mode
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* mask */
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#define XSK_ZYNQMP_BBRAM_STS_PGM_MODE_DEFVAL 0x0U
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/**< Bbram prgrmg mode
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* default value */
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/*@}*/
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/** @name Register: BbramCtrl
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* @{
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*/
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#define XSK_ZYNQMP_BBRAM_CTRL_OFFSET 0x00000004U
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/**< Cotrol reg offset */
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#define XSK_ZYNQMP_BBRAM_CTRL_RSTVAL 0x00000000U
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/**< Cotrol reg reset value */
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||||
#define XSK_ZYNQMP_BBRAM_CTRL_ZEROIZE_SHIFT 0U
|
||||
/**< Cotrol reg zeroise shift */
|
||||
#define XSK_ZYNQMP_BBRAM_CTRL_ZEROIZE_WIDTH 1U
|
||||
/**< Cotrol reg zeroise width */
|
||||
#define XSK_ZYNQMP_BBRAM_CTRL_ZEROIZE_MASK 0x00000001U
|
||||
/**< Cotrol reg zeroise mask */
|
||||
#define XSK_ZYNQMP_BBRAM_CTRL_ZEROIZE_DEFVAL 0x0U
|
||||
/**< Cotrol reg default value*/
|
||||
/*@}*/
|
||||
|
||||
/** @name Register: BbramPgmMode
|
||||
* @{
|
||||
*/
|
||||
#define XSK_ZYNQMP_BBRAM_PGM_MODE_OFFSET 0x00000008U
|
||||
/**< Programming mode offset */
|
||||
#define XSK_ZYNQMP_BBRAM_PGM_MODE_RSTVAL 0x00000000U
|
||||
/**< prgrmg mode reset value */
|
||||
#define XSK_ZYNQMP_BBRAM_PGM_MODE_VAL_WIDTH 32U
|
||||
/**< prgrmg mode value width */
|
||||
#define XSK_ZYNQMP_BBRAM_PGM_MODE_VAL_MASK 0xffffffffU
|
||||
/**< prgrmg mode value mask */
|
||||
#define XSK_ZYNQMP_BBRAM_PGM_MODE_VAL_DEFVAL 0x0U
|
||||
/**< prgrmg mode default val */
|
||||
#define XSK_ZYNQMP_BBRAM_PGM_MODE_SET_VAL 0x757BDF0D
|
||||
/**< prgrmg mode set value */
|
||||
/*@}*/
|
||||
|
||||
/** @name Register: BbramAesCrc
|
||||
* @{
|
||||
*/
|
||||
#define XSK_ZYNQMP_BBRAM_AES_CRC_OFFSET 0x0000000CU
|
||||
/**< AES's CRC offset */
|
||||
#define XSK_ZYNQMP_BBRAM_AES_CRC_RSTVAL 0x00000000U
|
||||
/**< AES's CRC reset val */
|
||||
#define XSK_ZYNQMP_BBRAM_AES_CRC_VAL_SHIFT 0U
|
||||
/**< AES's CRC val shift */
|
||||
#define XSK_ZYNQMP_BBRAM_AES_CRC_VAL_WIDTH 32U
|
||||
/**< AES's CRC val width */
|
||||
#define XSK_ZYNQMP_BBRAM_AES_CRC_VAL_MASK 0xffffffffU
|
||||
/**< AES's CRC val mask */
|
||||
#define XSK_ZYNQMP_BBRAM_AES_CRC_VAL_DEFVAL 0x0U
|
||||
/**< AES's CRC default val */
|
||||
/*@}*/
|
||||
|
||||
/** @name Register: Bbram0
|
||||
* @{
|
||||
*/
|
||||
#define XSK_ZYNQMP_BBRAM_0_OFFSET 0x00000010U /**< Bbram0 offset */
|
||||
#define XSK_ZYNQMP_BBRAM_0_RSTVAL 0x00000000U /**< Bbram0 rst value */
|
||||
#define XSK_ZYNQMP_BBRAM_0_DATA_SHIFT 0U /**< Bbram0 data shift */
|
||||
#define XSK_ZYNQMP_BBRAM_0_DATA_WIDTH 32U /**< Bbram0 data width */
|
||||
#define XSK_ZYNQMP_BBRAM_0_DATA_MASK 0xffffffffU /**< Bbram0 data mask */
|
||||
#define XSK_ZYNQMP_BBRAM_0_DATA_DEFVAL 0x0U/**< Bbram0 def value */
|
||||
/*@}*/
|
||||
|
||||
/** @name Register: Bbram1
|
||||
* @{
|
||||
*/
|
||||
#define XSK_ZYNQMP_BBRAM_1_OFFSET 0x00000014U /**< Bbram1 offset */
|
||||
#define XSK_ZYNQMP_BBRAM_1_RSTVAL 0x00000000U /**< Bbram1 rst value */
|
||||
|
||||
#define XSK_ZYNQMP_BBRAM_1_DATA_SHIFT 0U /**< Bbram1 data shift */
|
||||
#define XSK_ZYNQMP_BBRAM_1_DATA_WIDTH 32U /**< Bbram1 data width */
|
||||
#define XSK_ZYNQMP_BBRAM_1_DATA_MASK 0xffffffffU /**< Bbram1 data mask */
|
||||
#define XSK_ZYNQMP_BBRAM_1_DATA_DEFVAL 0x0U/**< Bbram1 def value */
|
||||
/*@}*/
|
||||
|
||||
/** @name Register: Bbram2
|
||||
* @{
|
||||
*/
|
||||
#define XSK_ZYNQMP_BBRAM_2_OFFSET 0x00000018U /**< Bbram2 offset */
|
||||
#define XSK_ZYNQMP_BBRAM_2_RSTVAL 0x00000000U /**< Bbram2 rst value */
|
||||
|
||||
#define XSK_ZYNQMP_BBRAM_2_DATA_SHIFT 0U /**< Bbram2 data shift */
|
||||
#define XSK_ZYNQMP_BBRAM_2_DATA_WIDTH 32U /**< Bbram2 data width */
|
||||
#define XSK_ZYNQMP_BBRAM_2_DATA_MASK 0xffffffffU /**< Bbram2 data mask */
|
||||
#define XSK_ZYNQMP_BBRAM_2_DATA_DEFVAL 0x0U/**< Bbram2 def value */
|
||||
/*@}*/
|
||||
|
||||
/** @name Register: Bbram3
|
||||
* @{
|
||||
*/
|
||||
#define XSK_ZYNQMP_BBRAM_3_OFFSET 0x0000001CU/**< Bbram3 offset */
|
||||
#define XSK_ZYNQMP_BBRAM_3_RSTVAL 0x00000000U/**< Bbram3 rst value */
|
||||
|
||||
#define XSK_ZYNQMP_BBRAM_3_DATA_SHIFT 0U /**< Bbram3 data shift */
|
||||
#define XSK_ZYNQMP_BBRAM_3_DATA_WIDTH 32U/**< Bbram3 data width */
|
||||
#define XSK_ZYNQMP_BBRAM_3_DATA_MASK 0xffffffffU/**< Bbram3 data mask */
|
||||
#define XSK_ZYNQMP_BBRAM_3_DATA_DEFVAL 0x0U/**< Bbram3 def value */
|
||||
/*@}*/
|
||||
|
||||
/** @name Register: Bbram4
|
||||
* @{
|
||||
*/
|
||||
#define XSK_ZYNQMP_BBRAM_4_OFFSET 0x00000020U/**< Bbram4 offset */
|
||||
#define XSK_ZYNQMP_BBRAM_4_RSTVAL 0x00000000U/**< Bbram4 rst value */
|
||||
|
||||
#define XSK_ZYNQMP_BBRAM_4_DATA_SHIFT 0U /**< Bbram4 data shift */
|
||||
#define XSK_ZYNQMP_BBRAM_4_DATA_WIDTH 32U/**< Bbram4 data width */
|
||||
#define XSK_ZYNQMP_BBRAM_4_DATA_MASK 0xffffffffU/**< Bbram4 data mask */
|
||||
#define XSK_ZYNQMP_BBRAM_4_DATA_DEFVAL 0x0U/**< Bbram4 def value */
|
||||
/*@}*/
|
||||
|
||||
/** @name Register: Bbram5
|
||||
* @{
|
||||
*/
|
||||
#define XSK_ZYNQMP_BBRAM_5_OFFSET 0x00000024U/**< Bbram5 offset */
|
||||
#define XSK_ZYNQMP_BBRAM_5_RSTVAL 0x00000000U/**< Bbram5 rst value */
|
||||
|
||||
#define XSK_ZYNQMP_BBRAM_5_DATA_SHIFT 0U /**< Bbram5 data shift */
|
||||
#define XSK_ZYNQMP_BBRAM_5_DATA_WIDTH 32U/**< Bbram5 data width */
|
||||
#define XSK_ZYNQMP_BBRAM_5_DATA_MASK 0xffffffffU/**< Bbram5 data mask */
|
||||
#define XSK_ZYNQMP_BBRAM_5_DATA_DEFVAL 0x0U/**< Bbram5 def value */
|
||||
/*@}*/
|
||||
|
||||
/** @name Register: Bbram6
|
||||
* @{
|
||||
*/
|
||||
#define XSK_ZYNQMP_BBRAM_6_OFFSET 0x00000028U/**< Bbram6 offset */
|
||||
#define XSK_ZYNQMP_BBRAM_6_RSTVAL 0x00000000U/**< Bbram6 rst value */
|
||||
|
||||
#define XSK_ZYNQMP_BBRAM_6_DATA_SHIFT 0U /**< Bbram6 data shift */
|
||||
#define XSK_ZYNQMP_BBRAM_6_DATA_WIDTH 32U/**< Bbram6 data width */
|
||||
#define XSK_ZYNQMP_BBRAM_6_DATA_MASK 0xffffffffU/**< Bbram6 data mask */
|
||||
#define XSK_ZYNQMP_BBRAM_6_DATA_DEFVAL 0x0U/**< Bbram6 def value */
|
||||
/*@}*/
|
||||
|
||||
/** @name Register: Bbram7
|
||||
* @{
|
||||
*/
|
||||
#define XSK_ZYNQMP_BBRAM_7_OFFSET 0x0000002CU/**< Bbram7 offset */
|
||||
#define XSK_ZYNQMP_BBRAM_7_RSTVAL 0x00000000U/**< Bbram7 rst value */
|
||||
|
||||
#define XSK_ZYNQMP_BBRAM_7_DATA_SHIFT 0U /**< Bbram7 data shift */
|
||||
#define XSK_ZYNQMP_BBRAM_7_DATA_WIDTH 32U/**< Bbram7 data width */
|
||||
#define XSK_ZYNQMP_BBRAM_7_DATA_MASK 0xffffffffU/**< Bbram7 data mask */
|
||||
#define XSK_ZYNQMP_BBRAM_7_DATA_DEFVAL 0x0U /**< Bbram7 def value */
|
||||
/*@}*/
|
||||
|
||||
/** @name Register: Bbram8
|
||||
* @{
|
||||
*/
|
||||
#define XSK_ZYNQMP_BBRAM_8_OFFSET 0x00000030U/**< Bbram8 offset */
|
||||
#define XSK_ZYNQMP_BBRAM_8_RSTVAL 0x00000000U/**< Bbram8 rst value */
|
||||
|
||||
#define XSK_ZYNQMP_BBRAM_8_DATA_SHIFT 0U /**< Bbram8 data shift */
|
||||
#define XSK_ZYNQMP_BBRAM_8_DATA_WIDTH 32U/**< Bbram8 data width */
|
||||
#define XSK_ZYNQMP_BBRAM_8_DATA_MASK 0xffffffffU/**< Bbram8 data mask */
|
||||
#define XSK_ZYNQMP_BBRAM_8_DATA_DEFVAL 0x0U/**< Bbram8 def value */
|
||||
/*@}*/
|
||||
|
||||
/** @name Register: BbramSlverr
|
||||
* @{
|
||||
*/
|
||||
#define XSK_ZYNQMP_BBRAM_SLVERR_OFFSET 0x00000034U /**< Slave error control
|
||||
* offset */
|
||||
#define XSK_ZYNQMP_BBRAM_SLVERR_RSTVAL 0x00000000U /**< Slave error reg
|
||||
* reset value */
|
||||
|
||||
#define XSK_ZYNQMP_BBRAM_SLVERR_EN_SHIFT 0x0U /**< Slave error
|
||||
* enable shift */
|
||||
#define XSK_ZYNQMP_BBRAM_SLVERR_EN_WIDTH 0x1U /**< Slave error
|
||||
* enable width */
|
||||
#define XSK_ZYNQMP_BBRAM_SLVERR_EN_MASK 0x00000001U /**< Slave error
|
||||
* enable mask */
|
||||
#define XSK_ZYNQMP_BBRAM_SLVERR_EN_DEFVAL 0x0U /**< Slave error
|
||||
* enable def value*/
|
||||
/*@}*/
|
||||
|
||||
/** @name Register: BbramIsr
|
||||
* @{
|
||||
*/
|
||||
#define XSK_ZYNQMP_BBRAM_ISR_OFFSET 0x00000038U
|
||||
/**< ISR offset */
|
||||
#define XSK_ZYNQMP_BBRAM_ISR_RSTVAL 0x00000000U
|
||||
/**< ISR reset value */
|
||||
|
||||
#define XSK_ZYNQMP_BBRAM_ISR_APB_SLVERR_SHIFT 0x0U
|
||||
/**< ISR APB slave err
|
||||
* shift */
|
||||
#define XSK_ZYNQMP_BBRAM_ISR_APB_SLVERR_WIDTH 0x1U
|
||||
/**< ISR APB slave err
|
||||
* width */
|
||||
#define XSK_ZYNQMP_BBRAM_ISR_APB_SLVERR_MASK 0x00000001U
|
||||
/**< ISR APB slave err
|
||||
* maks */
|
||||
#define XSK_ZYNQMP_BBRAM_ISR_APB_SLVERR_DEFVAL 0x0U
|
||||
/**< ISR APB slave err
|
||||
* def value */
|
||||
/*@}*/
|
||||
|
||||
/** @name Register: BbramImr
|
||||
* @{
|
||||
*/
|
||||
#define XSK_ZYNQMP_BBRAM_IMR_OFFSET 0x0000003CU
|
||||
/**< IMR offset */
|
||||
#define XSK_ZYNQMP_BBRAM_IMR_RSTVAL 0x00000001U
|
||||
/**< IMR reset value */
|
||||
#define XSK_ZYNQMP_BBRAM_IMR_APB_SLVERR_SHIFT 0x0U
|
||||
/**< IMR APB slave err
|
||||
* shift */
|
||||
#define XSK_ZYNQMP_BBRAM_IMR_APB_SLVERR_WIDTH 0x1U
|
||||
/**< IMR APB slave err
|
||||
* width */
|
||||
#define XSK_ZYNQMP_BBRAM_IMR_APB_SLVERR_MASK 0x00000001U
|
||||
/**< IMR APB slave err
|
||||
* maks */
|
||||
#define XSK_ZYNQMP_BBRAM_IMR_APB_SLVERR_DEFVAL 0x1U
|
||||
/**< IMR APB slave err
|
||||
* def value */
|
||||
/*@}*/
|
||||
|
||||
/** @name Register: BbramIer
|
||||
* @{
|
||||
*/
|
||||
#define XSK_ZYNQMP_BBRAM_IER_OFFSET 0x00000040U
|
||||
/**< IER offset */
|
||||
#define XSK_ZYNQMP_BBRAM_IER_RSTVAL 0x00000000U
|
||||
/**< IER reset value */
|
||||
#define XSK_ZYNQMP_BBRAM_IER_APB_SLVERR_SHIFT 0U
|
||||
/**< IER APB slave err
|
||||
* shift */
|
||||
#define XSK_ZYNQMP_BBRAM_IER_APB_SLVERR_WIDTH 1U
|
||||
/**< IER APB slave err
|
||||
* width */
|
||||
#define XSK_ZYNQMP_BBRAM_IER_APB_SLVERR_MASK 0x00000001U
|
||||
/**< IER APB slave err
|
||||
* mask */
|
||||
#define XSK_ZYNQMP_BBRAM_IER_APB_SLVERR_DEFVAL 0x0U
|
||||
/**< IER APB slave err
|
||||
* def value */
|
||||
/*@}*/
|
||||
|
||||
/** @name Register: BbramIdr
|
||||
* @{
|
||||
*/
|
||||
#define XSK_ZYNQMP_BBRAM_IDR_OFFSET 0x00000044U
|
||||
/**< IDR offset */
|
||||
#define XSK_ZYNQMP_BBRAM_IDR_RSTVAL 0x00000000U
|
||||
/**< IDR reset value */
|
||||
#define XSK_ZYNQMP_BBRAM_IDR_APB_SLVERR_SHIFT 0x0U
|
||||
/**< IDR APB slave err
|
||||
* shift */
|
||||
#define XSK_ZYNQMP_BBRAM_IDR_APB_SLVERR_WIDTH 0x1U
|
||||
/**< IDR APB slave err
|
||||
* width */
|
||||
#define XSK_ZYNQMP_BBRAM_IDR_APB_SLVERR_MASK 0x00000001U
|
||||
/**< IDR APB slave err
|
||||
* mask */
|
||||
#define XSK_ZYNQMP_BBRAM_IDR_APB_SLVERR_DEFVAL 0x0U
|
||||
/**< IDR APB slave err
|
||||
* def value */
|
||||
/*@}*/
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions ********************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __XSK_BBRAMPS_ZYNQMP_HW__ */
|
||||
Loading…
Add table
Reference in a new issue