lwip: Add support for A53 and R5
Add support for lwip library to be picked for A53 & R5 and to use necessary GIC. Comment informational prints. This is to add support for Zynq Ultrascale MPSoC. Signed-off-by: Harini Katakam <harinik@xilinx.com> Reviewed-by: Anirudha Sarangi <anirudh@xilinx.com>
This commit is contained in:
Harini Katakam
Nava kishore Manne
parent
f406b72805
commit
baa1675449
1 changed files with 90 additions and 35 deletions
125
ThirdParty/sw_services/lwip141/data/lwip141.tcl
vendored
125
ThirdParty/sw_services/lwip141/data/lwip141.tcl
vendored
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@ -245,7 +245,8 @@ proc get_emac_periphs {processor} {
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|| $periphname == "axi_ethernet"
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|| $periphname == "axi_ethernet_buffer"
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|| $periphname == "axi_ethernetlite"
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|| $periphname == "ps7_ethernet"} {
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|| $periphname == "ps7_ethernet"
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|| $periphname == "psu_ethernet"} {
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lappend emac_periphs_list $periph
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} elseif {$periphname == "xps_ll_temac"} {
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set emac0_enabled "0"
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@ -288,7 +289,7 @@ proc get_emac_periphs {processor} {
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# all components to run lwIP are available.
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#---------------------------------------------
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proc lwip_drc {libhandle} {
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puts "Runnning DRC for lwIP library... \n"
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#puts "Runnning DRC for lwIP library... \n"
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# find the list of xps_ethernetlite, xps_ll_temac, or axi_ethernet cores
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set sw_processor [hsi::get_sw_processor]
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@ -299,13 +300,16 @@ proc lwip_drc {libhandle} {
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if { [llength $emac_periphs_list] == 0 } {
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set cpuname [common::get_property NAME $processor]
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error "ERROR: No Ethernet MAC cores are addressable from processor $cpuname. \
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lwIP requires atleast one EMAC (xps_ethernetlite | xps_ll_temac | axi_ethernet | axi_ethernet_buffer | axi_ethernetlite | ps7_ethernet) core \
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lwIP requires atleast one EMAC (xps_ethernetlite | xps_ll_temac | axi_ethernet | axi_ethernet_buffer | axi_ethernetlite | ps7_ethernet | psu_ethernet ) core \
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with its interrupt pin connected to the interrupt controller.\n" "" "MDT_ERROR"
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return
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}
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} else {
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set emac_names_list {}
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foreach emac $emac_periphs_list {
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lappend emac_names_list [common::get_property NAME $emac]
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foreach emac $emac_periphs_list {
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lappend emac_names_list [common::get_property NAME $emac]
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}
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#puts "lwIP can be used with the following EMAC peripherals found in your system: $emac_names_list"
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}
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#----
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@ -365,6 +369,19 @@ proc generate_lwip_opts {libhandle} {
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puts $lwipopts_fd "\#define PROCESSOR_LITTLE_ENDIAN"
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puts $lwipopts_fd "\#endif\n"
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}
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"psu_cortexr5" {
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puts $lwipopts_fd "\#ifndef PROCESSOR_LITTLE_ENDIAN"
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puts $lwipopts_fd "\#define PROCESSOR_LITTLE_ENDIAN"
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puts $lwipopts_fd "\#endif\n"
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}
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"psu_cortexa53" {
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puts $lwipopts_fd "\#ifndef PROCESSOR_LITTLE_ENDIAN"
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puts $lwipopts_fd "\#define PROCESSOR_LITTLE_ENDIAN"
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puts $lwipopts_fd "\#endif\n"
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}
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default {
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puts $lwipopts_fd "\#ifndef PROCESSOR_BIG_ENDIAN"
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puts $lwipopts_fd "\#define PROCESSOR_BIG_ENDIAN"
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@ -539,7 +556,7 @@ proc generate_lwip_opts {libhandle} {
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set use_axieth_on_zynq 0
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}
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if {$proctype != "ps7_cortexa9" || $use_axieth_on_zynq == 1} {
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if {$proctype == "microblaze" || $use_axieth_on_zynq == 1} {
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set tx_full_csum_temp [common::get_property CONFIG.tcp_ip_tx_checksum_offload $libhandle]
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if {$tx_full_csum_temp == true} {
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if {$checksum_txoption != 2} {
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@ -637,12 +654,12 @@ proc generate_lwip_opts {libhandle} {
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puts $lwipopts_fd "\#define MEMP_SEPARATE_POOLS 1"
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puts $lwipopts_fd "\#define MEMP_NUM_FRAG_PBUF 256"
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puts $lwipopts_fd "\#define IP_OPTIONS_ALLOWED 0"
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if {$proctype != "ps7_cortexa9"} {
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if {$proctype == "microblaze"} {
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puts $lwipopts_fd "\#define TCP_OVERSIZE 0"
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} else {
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puts $lwipopts_fd "\#define TCP_OVERSIZE TCP_MSS"
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}
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if {$proctype != "ps7_cortexa9"} {
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if {$proctype == "microblaze"} {
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puts $lwipopts_fd "\#define LWIP_COMPAT_MUTEX 1"
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puts $lwipopts_fd "\#define LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT 0"
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} else {
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@ -803,8 +820,10 @@ proc update_emaclite_topology {emac processor topologyvar} {
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set processor_type [common::get_property IP_NAME $processor]
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set force_emaclite_on_zynq 0
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if {$processor_type == "ps7_cortexa9" && $use_emaclite_on_zynq == 1} {
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set force_emaclite_on_zynq 1
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if {$use_emaclite_on_zynq == 1} {
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if {$processor_type == "ps7_cortexa9" || $processor_type == "psu_cortexr5" || $processor_type == "psu_cortexa53"} {
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set force_emaclite_on_zynq 1
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}
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}
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# get emac baseaddr
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@ -875,7 +894,7 @@ proc update_axi_ethernet_topology {emac processor topologyvar} {
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"" "mdt_error"
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}
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if { $intc_periph_type != [format "ps7_scugic"] } {
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if { $intc_periph_type != [format "ps7_scugic"] && $intc_periph_type != [format "psu_scugic"] && $intc_periph_type != [format "psu_acpu_gic"] && $intc_periph_type != [format "psu_rcpu_gic"]} {
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set topology(intc_baseaddr) [common::get_property CONFIG.C_BASEADDR $intc_handle]
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set topology(intc_baseaddr) [::hsm::utils::format_addr_string $topology(intc_baseaddr) "C_BASEADDR"]
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set topology(scugic_baseaddr) "0x0"
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@ -888,7 +907,7 @@ proc update_axi_ethernet_topology {emac processor topologyvar} {
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}
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proc update_ps7_ethernet_topology {emac processor topologyvar} {
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proc update_ps_ethernet_topology {emac processor topologyvar} {
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upvar $topologyvar topology
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set topology(emac_baseaddr) [common::get_property CONFIG.C_S_AXI_BASEADDR $emac]
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set topology(emac_type) "xemac_type_emacps"
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@ -901,6 +920,14 @@ proc update_ps7_ethernet_topology {emac processor topologyvar} {
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set topology(scugic_emac_intr) "0x36"
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} elseif {$ethernet_instance == "ps7_ethernet_1" || $ethernet_instance == "ps7_enet1"} {
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set topology(scugic_emac_intr) "0x4D"
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} elseif {$ethernet_instance == "psu_ethernet_0"} {
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set topology(scugic_emac_intr) "XPAR_XEMACPS_0_INTR"
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} elseif {$ethernet_instance == "psu_ethernet_1"} {
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set topology(scugic_emac_intr) "XPAR_XEMACPS_1_INTR"
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} elseif {$ethernet_instance == "psu_ethernet_2"} {
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set topology(scugic_emac_intr) "XPAR_XEMACPS_2_INTR"
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} elseif {$ethernet_instance == "psu_ethernet_3"} {
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set topology(scugic_emac_intr) "XPAR_XEMACPS_3_INTR"
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}
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}
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@ -970,7 +997,11 @@ proc generate_topology {libhandle} {
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generate_topology_per_emac $tfd topology
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incr topology_size 1
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} elseif {$iptype == "ps7_ethernet"} {
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update_ps7_ethernet_topology $emac $processor topology
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update_ps_ethernet_topology $emac $processor topology
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generate_topology_per_emac $tfd topology
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incr topology_size 1
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} elseif {$iptype == "psu_ethernet"} {
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update_ps_ethernet_topology $emac $processor topology
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generate_topology_per_emac $tfd topology
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incr topology_size 1
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}
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@ -998,17 +1029,28 @@ proc generate_adapterconfig_makefile {libhandle} {
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set have_axi_ethernet 0
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set have_axi_ethernet_fifo 0
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set have_axi_ethernet_dma 0
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set have_ps7_ethernet 0
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set have_ps_ethernet 0
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set force_axieth_on_zynq 0
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set force_emaclite_on_zynq 0
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if {$processor_type == "ps7_cortexa9" && $use_axieth_on_zynq == 1} {
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set force_axieth_on_zynq 1
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}
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if {$processor_type == "psu_cortexr5" && $use_axieth_on_zynq == 1} {
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set force_axieth_on_zynq 1
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}
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if {$processor_type == "psu_cortexa53" && $use_axieth_on_zynq == 1} {
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set force_axieth_on_zynq 1
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}
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if {$processor_type == "ps7_cortexa9" && $use_emaclite_on_zynq == 1} {
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set force_emaclite_on_zynq 1
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}
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if {$processor_type == "psu_cortexr5" && $use_emaclite_on_zynq == 1} {
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set force_emaclite_on_zynq 1
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}
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if {$processor_type == "psu_cortexa53" && $use_emaclite_on_zynq == 1} {
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set force_emaclite_on_zynq 1
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}
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foreach emac $emac_periphs_list {
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set iptype [common::get_property IP_NAME $emac]
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if {$iptype == "xps_ethernetlite" || $iptype == "opb_ethernetlite" || $iptype == "axi_ethernetlite"} {
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@ -1024,16 +1066,16 @@ proc generate_adapterconfig_makefile {libhandle} {
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} else {
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set have_axi_ethernet_dma 1
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}
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} elseif {$iptype == "ps7_ethernet"} {
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set have_ps7_ethernet 1
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} elseif {$iptype == "ps7_ethernet" || $iptype == "psu_ethernet" } {
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set have_ps_ethernet 1
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}
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}
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if {$force_axieth_on_zynq == 1 && $have_axi_ethernet == 1} {
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set have_ps7_ethernet 0
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set have_ps_ethernet 0
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set have_axi_ethernet 1
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}
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if {$force_emaclite_on_zynq == 1 && $have_emaclite == 1} {
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set have_ps7_ethernet 0
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set have_ps_ethernet 0
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set have_axi_ethernet 0
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}
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@ -1066,6 +1108,11 @@ proc generate_adapterconfig_makefile {libhandle} {
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#puts "Little Endian system"
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puts $fd "CONFIG_PROCESSOR_LITTLE_ENDIAN=y"
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}
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"psu_cortexr5" {
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puts $fd "GCC_COMPILER=arm-none-eabi-gcc"
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#puts "Little Endian system"
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puts $fd "CONFIG_PROCESSOR_LITTLE_ENDIAN=y"
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}
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default {
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puts "unknown processor type $proctype\n"
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}
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@ -1079,7 +1126,7 @@ proc generate_adapterconfig_makefile {libhandle} {
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puts $fd "CONFIG_XLLTEMAC=y"
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}
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if {$force_axieth_on_zynq == 1 || $have_ps7_ethernet == 0 } {
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if {$force_axieth_on_zynq == 1 || $have_ps_ethernet == 0 } {
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if {$have_axi_ethernet == 1} {
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puts $fd "CONFIG_AXI_ETHERNET=y"
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}
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@ -1089,8 +1136,8 @@ proc generate_adapterconfig_makefile {libhandle} {
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if {$have_axi_ethernet_fifo == 1} {
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puts $fd "CONFIG_AXI_ETHERNET_FIFO=y"
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}
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} elseif {$have_ps7_ethernet == 1} {
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puts $fd "CONFIG_PS7_ETHERNET=y"
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} elseif {$have_ps_ethernet == 1} {
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puts $fd "CONFIG_PS_ETHERNET=y"
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}
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set api_mode [common::get_property CONFIG.api_mode $libhandle]
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@ -1114,16 +1161,28 @@ proc generate_adapterconfig_include {libhandle} {
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set have_axi_ethernet 0
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set have_axi_ethernet_fifo 0
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set have_axi_ethernet_dma 0
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set have_ps7_ethernet 0
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set have_ps_ethernet 0
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set force_axieth_on_zynq 0
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set force_emaclite_on_zynq 0
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if {$processor_type == "ps7_cortexa9" && $use_axieth_on_zynq == 1} {
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set force_axieth_on_zynq 1
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}
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if {$processor_type == "psu_cortexr5" && $use_axieth_on_zynq == 1} {
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set force_axieth_on_zynq 1
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}
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if {$processor_type == "psu_cortexa53" && $use_axieth_on_zynq == 1} {
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set force_axieth_on_zynq 1
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}
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if {$processor_type == "ps7_cortexa9" && $use_emaclite_on_zynq == 1} {
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set force_emaclite_on_zynq 1
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}
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if {$processor_type == "psu_cortexr5" && $use_emaclite_on_zynq == 1} {
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set force_emaclite_on_zynq 1
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}
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if {$processor_type == "psu_cortexa53" && $use_emaclite_on_zynq == 1} {
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set force_emaclite_on_zynq 1
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}
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foreach emac $emac_periphs_list {
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set iptype [common::get_property IP_NAME $emac]
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@ -1140,12 +1199,12 @@ proc generate_adapterconfig_include {libhandle} {
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set have_axi_ethernet_dma 1
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}
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set have_axi_ethernet 1
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} elseif {$iptype == "ps7_ethernet"} {
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set have_ps7_ethernet 1
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} elseif {$iptype == "ps7_ethernet" || $iptype == "psu_ethernet"} {
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set have_ps_ethernet 1
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}
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}
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if {$force_emaclite_on_zynq == 1 && $have_emaclite == 1} {
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set have_ps7_ethernet 0
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set have_ps_ethernet 0
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set have_axi_ethernet 0
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}
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@ -1173,11 +1232,7 @@ proc generate_adapterconfig_include {libhandle} {
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puts $fd "\#define XLWIP_CONFIG_INCLUDE_EMACLITE 1"
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}
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if {$have_temac == 1} {
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puts $fd "\#define XLWIP_CONFIG_INCLUDE_TEMAC 1"
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}
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if {$force_axieth_on_zynq == 1 || $have_ps7_ethernet == 0 } {
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if {$force_axieth_on_zynq == 1 || $have_ps_ethernet == 0 } {
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if {$have_axi_ethernet == 1} {
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puts $fd "\#define XLWIP_CONFIG_INCLUDE_AXI_ETHERNET 1"
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}
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@ -1187,11 +1242,11 @@ proc generate_adapterconfig_include {libhandle} {
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if {$have_axi_ethernet_fifo == 1} {
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puts $fd "\#define XLWIP_CONFIG_INCLUDE_AXI_ETHERNET_FIFO 1"
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}
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} elseif {$have_ps7_ethernet == 1} {
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} elseif {$have_ps_ethernet == 1} {
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puts $fd "\#define XLWIP_CONFIG_INCLUDE_GEM 1"
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}
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if {$have_temac == 1 || $have_axi_ethernet == 1} {
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if {$have_axi_ethernet == 1} {
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set ndesc [common::get_property CONFIG.n_tx_descriptors $libhandle]
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puts $fd "\#define XLWIP_CONFIG_N_TX_DESC $ndesc"
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set ndesc [common::get_property CONFIG.n_rx_descriptors $libhandle]
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@ -1204,7 +1259,7 @@ proc generate_adapterconfig_include {libhandle} {
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puts $fd "\#define XLWIP_CONFIG_N_RX_COALESCE $ncoalesce"
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puts $fd ""
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}
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if {$have_ps7_ethernet == 1} {
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if {$have_ps_ethernet == 1} {
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set emacnum [common::get_property CONFIG.emac_number $libhandle]
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puts $fd "\#define XLWIP_CONFIG_EMAC_NUMBER $emacnum"
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set ndesc [common::get_property CONFIG.n_tx_descriptors $libhandle]
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