BSP: removed PEEP related code

This patch removes PEEP related code from standalone
BSP cortexa9 and also removes uart.c and smc.c.

Also removed function definition of XSmc_NorInit and
XSmc_NorInit from cortexa9/smc.h

Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
This commit is contained in:
Kinjal Pravinbhai Patel 2014-08-04 12:47:03 +05:30 committed by Jagannadha Sutradharudu Teki
parent 65aed475af
commit c361aa8b5b
7 changed files with 16 additions and 332 deletions

View file

@ -192,4 +192,9 @@
* 4.2 pkp 08/04/14 Removed unimplemented nanosleep routine from cortexa9/usleep.c as
* it is not possible to generate timer in nanosecond due to limited
* cpu frequency
* 4.2 pkp 08/04/14 Removed PEEP board related code which contained initialization of
* uart, smc nor and sram from cortexa9/gcc/xil-crt0.s and armcc/boot.s
* and iccarm/boot.s. Also uart.c and smc.c have been removed. Also
* removed function definition of XSmc_NorInit and XSmc_NorInit from
* cortexa9/smc.h
******************************************************************************************/

View file

@ -50,6 +50,8 @@
; 3.07a sgd 07/05/12 Updated with reset and start Global Timer
; 3.07a sgd 10/19/12 SMC NOR and SRAM initialization with build option
; 4.2 pkp 06/19/14 Enabled asynchronous abort exception
; 4.2 pkp 08/04/14 Removed PEEP board related code which contained
; initialization of uart smc nor and sram
; </pre>
;
; @note
@ -76,9 +78,6 @@
IMPORT _vector_table
IMPORT __main
IMPORT Xil_ExceptionInit
IMPORT XSmc_NorInit
IMPORT XSmc_SramInit
IMPORT Init_Uart
IMPORT XTime_SetTime
PSS_L2CC_BASE_ADDR EQU 0xF8F02000
@ -347,16 +346,7 @@ mmu_loop:
mrs r0, cpsr /* get the current PSR */
bic r0, r0, #0x100 /* enable asynchronous abort exception */
msr cpsr_xsf, r0
#ifdef PEEP
; Initialize STDOUT to 115200bps
bl Init_Uart
bl XSmc_NorInit
bl XSmc_SramInit
#endif
; Clear cp15 regs with unknown reset values
mov r0, #0x0
mcr p15, 0, r0, c5, c0, 0 ; DFSR

View file

@ -43,7 +43,9 @@
* 3.06a sgd 05/16/12 Added global constructors and cleanup code
* Uart initialization based on compiler flag
* 3.07a sgd 07/05/12 Updated with reset and start Global Timer
* 3.07a sgd 10/19/12 SMC NOR and SRAM initialization with build option
* 3.07a sgd 10/19/12 SMC NOR and SRAM initialization with build option
* 4.2 pkp 08/04/14 Removed PEEP board related code which contained
* initialization of uart smc nor and sram
* </pre>
*
* @note
@ -52,9 +54,6 @@
*
******************************************************************************/
.extern XSmc_NorInit
.extern XSmc_SramInit
.file "xil-crt0.S"
.section ".got2","aw"
.align 2
@ -112,17 +111,6 @@ _start:
mov r0, #0x0
mov r1, #0x0
bl XTime_SetTime
#ifdef PEEP
/* Initialize STDOUT */
bl Init_Uart
/* Initialize the SMC interfaces for NOR */
bl XSmc_NorInit
/* Initialize the SMC interfaces for SRAM */
bl XSmc_SramInit
#endif
#ifdef PROFILING /* defined in Makefile */
/* Setup profiling stuff */

View file

@ -40,7 +40,9 @@
;
; Ver Who Date Changes
; ----- ------- -------- ---------------------------------------------------
; 1.00a Initial version
; 1.00a Initial version
; 4.2 pkp 08/04/14 Removed PEEP board related code which contained
; initialization of uart smc nor and sram
; </pre>
;
; @note
@ -69,9 +71,6 @@
IMPORT MMUTable
IMPORT __cmain
IMPORT Xil_ExceptionInit
IMPORT XSmc_NorInit
IMPORT XSmc_SramInit
IMPORT Init_Uart
IMPORT XTime_SetTime
PSS_L2CC_BASE_ADDR EQU 0xF8F02000
@ -361,14 +360,6 @@ mmu_loop
; Initialize the vector table
;bl Xil_ExceptionInit
#ifdef PEEP
; Initialize STDOUT to 115200bps
bl Init_Uart
bl XSmc_NorInit
bl XSmc_SramInit
#endif
; Clear cp15 regs with unknown reset values
mov r0, #0x0

View file

@ -1,138 +0,0 @@
/******************************************************************************
*
* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file smc.c
*
* This file contains APIs for configuring the PL353 Static Memory Controller
* interfaces for NAND flash, SRAM and NOR flash.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------
* 1.00a sdm 08/02/10 Initial version
* </pre>
*
* @note
*
* None.
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "smc.h"
/***************** Macros (Inline Functions) Definitions *********************/
/**************************** Type Definitions *******************************/
/************************** Constant Definitions *****************************/
/*
* Register values for using NOR interface of SMC Controller
*/
#define NOR_SET_CYCLES ((0x0 << 20) | /* set_t6 or we_time from sram_cycles */ \
(0x1 << 17) | /* set_t5 or t_tr from sram_cycles */ \
(0x2 << 14) | /* set_t4 or t_pc from sram_cycles */ \
(0x5 << 11) | /* set_t3 or t_wp from sram_cycles */ \
(0x2 << 8) | /* set_t2 t_ceoe from sram_cycles */ \
(0x7 << 4) | /* set_t1 t_wc from sram_cycles */ \
(0x7)) /* set_t0 t_rc from sram_cycles */
#define NOR_SET_OPMODE ((0x1 << 13) | /* set_burst_align,set to 32 beats */ \
(0x1 << 12) | /* set_bls,set to default */ \
(0x0 << 11) | /* set_adv bit, set to default */ \
(0x0 << 10) | /* set_baa, we don't use baa_n */ \
(0x0 << 7) | /* set_wr_bl,write brust len,set to 0 */ \
(0x0 << 6) | /* set_wr_sync, set to 0 */ \
(0x0 << 3) | /* set_rd_bl,read brust len,set to 0 */ \
(0x0 << 2) | /* set_rd_sync, set to 0 */ \
(0x0)) /* set_mw, memory width, 16bits width*/
/* 0x00002000 */
#define NOR_DIRECT_CMD ((0x0 << 23) | /* Chip 0 from interface 0 */ \
(0x2 << 21) | /* UpdateRegs operation */ \
(0x0 << 20) | /* No ModeReg write */ \
(0x0)) /* Addr, not used in UpdateRegs */
/* Register values for using SRAM interface of SMC Controller */
#define SRAM_SET_CYCLES (0x00125155)
#define SRAM_SET_OPMODE (0x00003000)
#define SRAM_DIRECT_CMD (0x00C00000) /* Chip 1 */
/************************** Variable Definitions *****************************/
/************************** Function Prototypes ******************************/
/****************************************************************************
*
* Configure the SMC interface for SRAM.
*
* @param None.
*
* @return None.
*
* @note None.
*
****************************************************************************/
void XSmc_SramInit (void)
{
Xil_Out32(XPAR_XPARPORTPS_CTRL_BASEADDR + XSMCPSS_MC_SET_CYCLES,
SRAM_SET_CYCLES);
Xil_Out32(XPAR_XPARPORTPS_CTRL_BASEADDR + XSMCPSS_MC_SET_OPMODE,
SRAM_SET_OPMODE);
Xil_Out32(XPAR_XPARPORTPS_CTRL_BASEADDR + XSMCPSS_MC_DIRECT_CMD,
SRAM_DIRECT_CMD);
}
/****************************************************************************
*
* Configure the SMC interface for NOR flash.
*
* @param None.
*
* @return None.
*
* @note None.
*
****************************************************************************/
void XSmc_NorInit(void)
{
Xil_Out32(XPAR_XPARPORTPS_CTRL_BASEADDR + XSMCPSS_MC_SET_CYCLES,
NOR_SET_CYCLES);
Xil_Out32(XPAR_XPARPORTPS_CTRL_BASEADDR + XSMCPSS_MC_SET_OPMODE,
NOR_SET_OPMODE);
Xil_Out32(XPAR_XPARPORTPS_CTRL_BASEADDR + XSMCPSS_MC_DIRECT_CMD,
NOR_DIRECT_CMD);
}

View file

@ -39,6 +39,8 @@
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------
* 1.00a sdm 11/03/09 Initial release.
* 4.2 pkp 08/04/14 Removed function definition of XSmc_NorInit and XSmc_NorInit
* as smc.c is removed
* </pre>
*
* @note None.
@ -105,9 +107,6 @@ extern "C" {
/************************** Function Prototypes ******************************/
void XSmc_SramInit (void);
void XSmc_NorInit(void);
#ifdef __cplusplus
}
#endif /* __cplusplus */

View file

@ -1,151 +0,0 @@
/******************************************************************************
*
* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file uart.c
*
* This file contains APIs for configuring the UART.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------
* 1.00a sdm 08/02/10 Initial version
* </pre>
*
* @note
*
* None.
*
******************************************************************************/
#include "xparameters.h"
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
/* Register offsets */
#define UART_CR_OFFSET 0x00
#define UART_MR_OFFSET 0x04
#define UART_BAUDGEN_OFFSET 0x18
#define UART_BAUDDIV_OFFSET 0x34
#define MAX_BAUD_ERROR_RATE 3 /* max % error allowed */
#define UART_BAUDRATE 115200
void Init_Uart(void);
void Init_Uart(void)
{
#ifdef STDOUT_BASEADDRESS
u8 IterBAUDDIV; /* Iterator for available baud divisor values */
u32 BRGR_Value; /* Calculated value for baud rate generator */
u32 CalcBaudRate; /* Calculated baud rate */
u32 BaudError; /* Diff between calculated and requested baud
* rate */
u32 Best_BRGR = 0; /* Best value for baud rate generator */
u8 Best_BAUDDIV = 0; /* Best value for baud divisor */
u32 Best_Error = 0xFFFFFFFF;
u32 PercentError;
u32 InputClk;
u32 BaudRate = UART_BAUDRATE;
#if (STDOUT_BASEADDRESS == XPAR_XUARTPS_0_BASEADDR)
InputClk = XPAR_XUARTPS_0_UART_CLK_FREQ_HZ;
#elif (STDOUT_BASEADDRESS == XPAR_XUARTPS_1_BASEADDR)
InputClk = XPAR_XUARTPS_1_UART_CLK_FREQ_HZ;
#else
/* STDIO is not set or axi_uart is being used for STDIO */
return;
#endif
/*
* Determine the Baud divider. It can be 4to 254.
* Loop through all possible combinations
*/
for (IterBAUDDIV = 4; IterBAUDDIV < 255; IterBAUDDIV++) {
/*
* Calculate the value for BRGR register
*/
BRGR_Value = InputClk / (BaudRate * (IterBAUDDIV + 1));
/*
* Calculate the baud rate from the BRGR value
*/
CalcBaudRate = InputClk/ (BRGR_Value * (IterBAUDDIV + 1));
/*
* Avoid unsigned integer underflow
*/
if (BaudRate > CalcBaudRate) {
BaudError = BaudRate - CalcBaudRate;
} else {
BaudError = CalcBaudRate - BaudRate;
}
/*
* Find the calculated baud rate closest to requested baud rate.
*/
if (Best_Error > BaudError) {
Best_BRGR = BRGR_Value;
Best_BAUDDIV = IterBAUDDIV;
Best_Error = BaudError;
}
}
/*
* Make sure the best error is not too large.
*/
PercentError = (Best_Error * 100) / BaudRate;
if (MAX_BAUD_ERROR_RATE < PercentError) {
return;
}
/* set CD and BDIV */
Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDGEN_OFFSET, Best_BRGR);
Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDDIV_OFFSET, Best_BAUDDIV);
/*
* 8 data, 1 stop, 0 parity bits
* sel_clk=uart_clk=APB clock
*/
Xil_Out32(STDOUT_BASEADDRESS + UART_MR_OFFSET, 0x20);
/* enable Tx/Rx and reset Tx/Rx data path */
Xil_Out32((STDOUT_BASEADDRESS + UART_CR_OFFSET), 0x17);
return;
#endif
}