BSP: removed PEEP related code
This patch removes PEEP related code from standalone BSP cortexa9 and also removes uart.c and smc.c. Also removed function definition of XSmc_NorInit and XSmc_NorInit from cortexa9/smc.h Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com> Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
This commit is contained in:
Kinjal Pravinbhai Patel
Jagannadha Sutradharudu Teki
parent
65aed475af
commit
c361aa8b5b
7 changed files with 16 additions and 332 deletions
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@ -192,4 +192,9 @@
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* 4.2 pkp 08/04/14 Removed unimplemented nanosleep routine from cortexa9/usleep.c as
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* it is not possible to generate timer in nanosecond due to limited
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* cpu frequency
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* 4.2 pkp 08/04/14 Removed PEEP board related code which contained initialization of
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* uart, smc nor and sram from cortexa9/gcc/xil-crt0.s and armcc/boot.s
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* and iccarm/boot.s. Also uart.c and smc.c have been removed. Also
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* removed function definition of XSmc_NorInit and XSmc_NorInit from
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* cortexa9/smc.h
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******************************************************************************************/
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@ -50,6 +50,8 @@
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; 3.07a sgd 07/05/12 Updated with reset and start Global Timer
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; 3.07a sgd 10/19/12 SMC NOR and SRAM initialization with build option
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; 4.2 pkp 06/19/14 Enabled asynchronous abort exception
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; 4.2 pkp 08/04/14 Removed PEEP board related code which contained
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; initialization of uart smc nor and sram
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; </pre>
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;
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; @note
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@ -76,9 +78,6 @@
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IMPORT _vector_table
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IMPORT __main
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IMPORT Xil_ExceptionInit
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IMPORT XSmc_NorInit
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IMPORT XSmc_SramInit
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IMPORT Init_Uart
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IMPORT XTime_SetTime
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PSS_L2CC_BASE_ADDR EQU 0xF8F02000
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@ -347,16 +346,7 @@ mmu_loop:
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mrs r0, cpsr /* get the current PSR */
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bic r0, r0, #0x100 /* enable asynchronous abort exception */
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msr cpsr_xsf, r0
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#ifdef PEEP
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; Initialize STDOUT to 115200bps
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bl Init_Uart
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bl XSmc_NorInit
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bl XSmc_SramInit
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#endif
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; Clear cp15 regs with unknown reset values
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mov r0, #0x0
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mcr p15, 0, r0, c5, c0, 0 ; DFSR
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@ -43,7 +43,9 @@
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* 3.06a sgd 05/16/12 Added global constructors and cleanup code
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* Uart initialization based on compiler flag
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* 3.07a sgd 07/05/12 Updated with reset and start Global Timer
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* 3.07a sgd 10/19/12 SMC NOR and SRAM initialization with build option
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* 3.07a sgd 10/19/12 SMC NOR and SRAM initialization with build option
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* 4.2 pkp 08/04/14 Removed PEEP board related code which contained
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* initialization of uart smc nor and sram
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* </pre>
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*
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* @note
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@ -52,9 +54,6 @@
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*
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******************************************************************************/
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.extern XSmc_NorInit
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.extern XSmc_SramInit
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.file "xil-crt0.S"
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.section ".got2","aw"
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.align 2
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@ -112,17 +111,6 @@ _start:
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mov r0, #0x0
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mov r1, #0x0
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bl XTime_SetTime
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#ifdef PEEP
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/* Initialize STDOUT */
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bl Init_Uart
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/* Initialize the SMC interfaces for NOR */
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bl XSmc_NorInit
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/* Initialize the SMC interfaces for SRAM */
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bl XSmc_SramInit
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#endif
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#ifdef PROFILING /* defined in Makefile */
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/* Setup profiling stuff */
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@ -40,7 +40,9 @@
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;
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; Ver Who Date Changes
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; ----- ------- -------- ---------------------------------------------------
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; 1.00a Initial version
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; 1.00a Initial version
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; 4.2 pkp 08/04/14 Removed PEEP board related code which contained
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; initialization of uart smc nor and sram
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; </pre>
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;
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; @note
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@ -69,9 +71,6 @@
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IMPORT MMUTable
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IMPORT __cmain
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IMPORT Xil_ExceptionInit
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IMPORT XSmc_NorInit
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IMPORT XSmc_SramInit
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IMPORT Init_Uart
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IMPORT XTime_SetTime
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PSS_L2CC_BASE_ADDR EQU 0xF8F02000
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@ -361,14 +360,6 @@ mmu_loop
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; Initialize the vector table
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;bl Xil_ExceptionInit
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#ifdef PEEP
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; Initialize STDOUT to 115200bps
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bl Init_Uart
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bl XSmc_NorInit
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bl XSmc_SramInit
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#endif
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; Clear cp15 regs with unknown reset values
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mov r0, #0x0
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@ -1,138 +0,0 @@
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/******************************************************************************
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*
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* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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* @file smc.c
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*
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* This file contains APIs for configuring the PL353 Static Memory Controller
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* interfaces for NAND flash, SRAM and NOR flash.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- ---------------------------------------------------
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* 1.00a sdm 08/02/10 Initial version
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* </pre>
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*
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* @note
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*
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* None.
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*
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******************************************************************************/
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/***************************** Include Files *********************************/
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#include "smc.h"
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/***************** Macros (Inline Functions) Definitions *********************/
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/**************************** Type Definitions *******************************/
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/************************** Constant Definitions *****************************/
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/*
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* Register values for using NOR interface of SMC Controller
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*/
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#define NOR_SET_CYCLES ((0x0 << 20) | /* set_t6 or we_time from sram_cycles */ \
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(0x1 << 17) | /* set_t5 or t_tr from sram_cycles */ \
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(0x2 << 14) | /* set_t4 or t_pc from sram_cycles */ \
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(0x5 << 11) | /* set_t3 or t_wp from sram_cycles */ \
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(0x2 << 8) | /* set_t2 t_ceoe from sram_cycles */ \
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(0x7 << 4) | /* set_t1 t_wc from sram_cycles */ \
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(0x7)) /* set_t0 t_rc from sram_cycles */
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#define NOR_SET_OPMODE ((0x1 << 13) | /* set_burst_align,set to 32 beats */ \
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(0x1 << 12) | /* set_bls,set to default */ \
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(0x0 << 11) | /* set_adv bit, set to default */ \
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(0x0 << 10) | /* set_baa, we don't use baa_n */ \
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(0x0 << 7) | /* set_wr_bl,write brust len,set to 0 */ \
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(0x0 << 6) | /* set_wr_sync, set to 0 */ \
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(0x0 << 3) | /* set_rd_bl,read brust len,set to 0 */ \
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(0x0 << 2) | /* set_rd_sync, set to 0 */ \
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(0x0)) /* set_mw, memory width, 16bits width*/
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/* 0x00002000 */
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#define NOR_DIRECT_CMD ((0x0 << 23) | /* Chip 0 from interface 0 */ \
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(0x2 << 21) | /* UpdateRegs operation */ \
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(0x0 << 20) | /* No ModeReg write */ \
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(0x0)) /* Addr, not used in UpdateRegs */
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/* Register values for using SRAM interface of SMC Controller */
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#define SRAM_SET_CYCLES (0x00125155)
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#define SRAM_SET_OPMODE (0x00003000)
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#define SRAM_DIRECT_CMD (0x00C00000) /* Chip 1 */
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/************************** Variable Definitions *****************************/
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/************************** Function Prototypes ******************************/
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/****************************************************************************
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*
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* Configure the SMC interface for SRAM.
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*
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* @param None.
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*
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* @return None.
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*
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* @note None.
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*
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****************************************************************************/
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void XSmc_SramInit (void)
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{
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Xil_Out32(XPAR_XPARPORTPS_CTRL_BASEADDR + XSMCPSS_MC_SET_CYCLES,
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SRAM_SET_CYCLES);
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Xil_Out32(XPAR_XPARPORTPS_CTRL_BASEADDR + XSMCPSS_MC_SET_OPMODE,
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SRAM_SET_OPMODE);
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Xil_Out32(XPAR_XPARPORTPS_CTRL_BASEADDR + XSMCPSS_MC_DIRECT_CMD,
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SRAM_DIRECT_CMD);
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}
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/****************************************************************************
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*
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* Configure the SMC interface for NOR flash.
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*
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* @param None.
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*
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* @return None.
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*
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* @note None.
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*
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****************************************************************************/
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void XSmc_NorInit(void)
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{
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Xil_Out32(XPAR_XPARPORTPS_CTRL_BASEADDR + XSMCPSS_MC_SET_CYCLES,
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NOR_SET_CYCLES);
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Xil_Out32(XPAR_XPARPORTPS_CTRL_BASEADDR + XSMCPSS_MC_SET_OPMODE,
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NOR_SET_OPMODE);
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Xil_Out32(XPAR_XPARPORTPS_CTRL_BASEADDR + XSMCPSS_MC_DIRECT_CMD,
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NOR_DIRECT_CMD);
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}
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@ -39,6 +39,8 @@
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* Ver Who Date Changes
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* ----- ---- -------- ---------------------------------------------------
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* 1.00a sdm 11/03/09 Initial release.
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* 4.2 pkp 08/04/14 Removed function definition of XSmc_NorInit and XSmc_NorInit
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* as smc.c is removed
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* </pre>
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*
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* @note None.
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@ -105,9 +107,6 @@ extern "C" {
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/************************** Function Prototypes ******************************/
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void XSmc_SramInit (void);
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void XSmc_NorInit(void);
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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@ -1,151 +0,0 @@
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/******************************************************************************
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*
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* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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* @file uart.c
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*
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* This file contains APIs for configuring the UART.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- ---------------------------------------------------
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* 1.00a sdm 08/02/10 Initial version
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* </pre>
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*
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* @note
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*
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* None.
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*
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******************************************************************************/
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#include "xparameters.h"
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#include "xil_types.h"
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#include "xil_assert.h"
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#include "xil_io.h"
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/* Register offsets */
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#define UART_CR_OFFSET 0x00
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#define UART_MR_OFFSET 0x04
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#define UART_BAUDGEN_OFFSET 0x18
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#define UART_BAUDDIV_OFFSET 0x34
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#define MAX_BAUD_ERROR_RATE 3 /* max % error allowed */
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#define UART_BAUDRATE 115200
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void Init_Uart(void);
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void Init_Uart(void)
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{
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#ifdef STDOUT_BASEADDRESS
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u8 IterBAUDDIV; /* Iterator for available baud divisor values */
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u32 BRGR_Value; /* Calculated value for baud rate generator */
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u32 CalcBaudRate; /* Calculated baud rate */
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u32 BaudError; /* Diff between calculated and requested baud
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* rate */
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u32 Best_BRGR = 0; /* Best value for baud rate generator */
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u8 Best_BAUDDIV = 0; /* Best value for baud divisor */
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u32 Best_Error = 0xFFFFFFFF;
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u32 PercentError;
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u32 InputClk;
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u32 BaudRate = UART_BAUDRATE;
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#if (STDOUT_BASEADDRESS == XPAR_XUARTPS_0_BASEADDR)
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InputClk = XPAR_XUARTPS_0_UART_CLK_FREQ_HZ;
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#elif (STDOUT_BASEADDRESS == XPAR_XUARTPS_1_BASEADDR)
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InputClk = XPAR_XUARTPS_1_UART_CLK_FREQ_HZ;
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#else
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/* STDIO is not set or axi_uart is being used for STDIO */
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return;
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#endif
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/*
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* Determine the Baud divider. It can be 4to 254.
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* Loop through all possible combinations
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*/
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for (IterBAUDDIV = 4; IterBAUDDIV < 255; IterBAUDDIV++) {
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/*
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* Calculate the value for BRGR register
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*/
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BRGR_Value = InputClk / (BaudRate * (IterBAUDDIV + 1));
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/*
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* Calculate the baud rate from the BRGR value
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*/
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CalcBaudRate = InputClk/ (BRGR_Value * (IterBAUDDIV + 1));
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/*
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* Avoid unsigned integer underflow
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*/
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if (BaudRate > CalcBaudRate) {
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BaudError = BaudRate - CalcBaudRate;
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} else {
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BaudError = CalcBaudRate - BaudRate;
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}
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/*
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* Find the calculated baud rate closest to requested baud rate.
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*/
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if (Best_Error > BaudError) {
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Best_BRGR = BRGR_Value;
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Best_BAUDDIV = IterBAUDDIV;
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Best_Error = BaudError;
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}
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}
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/*
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* Make sure the best error is not too large.
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*/
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PercentError = (Best_Error * 100) / BaudRate;
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if (MAX_BAUD_ERROR_RATE < PercentError) {
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return;
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}
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/* set CD and BDIV */
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Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDGEN_OFFSET, Best_BRGR);
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Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDDIV_OFFSET, Best_BAUDDIV);
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/*
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* 8 data, 1 stop, 0 parity bits
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* sel_clk=uart_clk=APB clock
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*/
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Xil_Out32(STDOUT_BASEADDRESS + UART_MR_OFFSET, 0x20);
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/* enable Tx/Rx and reset Tx/Rx data path */
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Xil_Out32((STDOUT_BASEADDRESS + UART_CR_OFFSET), 0x17);
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return;
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#endif
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}
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