dptxss: Added custom resolution support

This patch adds custom resolution support and wrapper function
for setting a redriver path.

Signed-off-by: Shadul Shaikh <shaduls@xilinx.com>
Acked-by: Andrei-Liviu Simion <andreis@xilinx.com>

XilinxProcessorIPLib/drivers/dptxss/data/dptxss.tcl

@@ -27,6 +27,11 @@
 # Except as contained in this notice, the name of the Xilinx shall not be used
 # in advertising or otherwise to promote the sale, use or other dealings in
 # this Software without prior written authorization from Xilinx.
+#
+# MODIFICATION HISTORY:
+# Ver  Who Date     Changes
+# ---- --- -------- -----------------------------------------------------------
+# 1.00 sha 08/07/15 Added HDCP support to work with DP pass-through.
 ###############################################################################
 
 proc generate {drv_handle} {
@@ -48,6 +53,7 @@ proc hier_ip_define_config_file {drv_handle file_name drv_string args} {
 	set sub_core_params(displayport) "BASEADDR S_AXI_ACLK LANE_COUNT LINK_RATE MAX_BITS_PER_COLOR QUAD_PIXEL_ENABLE DUAL_PIXEL_ENABLE YCRCB_ENABLE YONLY_ENABLE GT_DATAWIDTH SECONDARY_SUPPORT AUDIO_CHANNELS MST_ENABLE NUMBER_OF_MST_STREAMS PROTOCOL_SELECTION FLOW_DIRECTION"
 	set sub_core_params(v_tc) "BASEADDR"
 	set sub_core_params(v_dual_splitter) "BASEADDR ACTIVE_COLS ACTIVE_ROWS MAX_SEGMENTS AXIS_VIDEO_MAX_TDATA_WIDTH AXIS_VIDEO_MAX_ITDATASMPLS_PER_CLK AXIS_VIDEO_MAX_OTDATASMPLS_PER_CLK MAX_OVRLAP MAX_SMPL_WIDTH HAS_AXI4_LITE HAS_IRQ"
+	set sub_core_params(hdcp) "BASEADDR S_AXI_FREQUENCY IS_RX IS_HDMI"
 
 	set filename [file join "src" $file_name]
 	set config_file [open $filename w]
@@ -86,7 +92,7 @@ proc hier_ip_define_config_file {drv_handle file_name drv_string args} {
 					}
 				}
 				if { $is_slave != 0 } {
-					puts -nonewline $config_file "#define [string toupper $final_child_cell_instance_name_present_g] \t1\n"
+					puts -nonewline $config_file "#define [string toupper $final_child_cell_instance_name_present_g]\t1\n"
 					if {$ip_name == "v_tc"} {
 						incr num_vtc
 					}

XilinxProcessorIPLib/drivers/dptxss/src/Makefile

@@ -14,10 +14,10 @@ INCLUDES=-I./. -I${INCLUDEDIR}
 
 OUTS = *.o
 
-INCLUDEFILES=*.h ./vtc/*.h ./dualsplitter/*.h ./dp/*.h
+INCLUDEFILES=*.h ./vtc/*.h ./dualsplitter/*.h ./dp/*.h ./hdcp1x/*.h
-LIBSOURCES=*.c ./vtc/*.c ./dualsplitter/*.c ./dp/*.c
+LIBSOURCES=*.c ./vtc/*.c ./dualsplitter/*.c ./dp/*.c ./hdcp1x/*.c
 
-OBJECTS = $(addsuffix .o, $(basename ./vtc/xdptxss_vtc.c ./dualsplitter/xdptxss_dualsplitter.c ./dp/xdptxss_dptx.c $(wildcard *.c)))
+OBJECTS = $(addsuffix .o, $(basename ./vtc/xdptxss_vtc.c ./dualsplitter/xdptxss_dualsplitter.c ./dp/xdptxss_dptx.c ./hdcp1x/xdptxss_hdcp1x.c $(wildcard *.c)))
 
 libs: banner xdptxss_libs clean
 

XilinxProcessorIPLib/drivers/dptxss/src/dp/xdptxss_dptx.c

@@ -41,10 +41,12 @@
 * MODIFICATION HISTORY:
 *
 * Ver  Who Date     Changes
-* ---- --- -------- --------------------------------------------------
+* ---- --- -------- ---------------------------------------------------------
 * 1.00 sha 01/29/15 Initial release.
 * 1.00 sha 07/21/15 Renamed file name with prefix xdptxss_* and function
 *                   names with prefix XDpTxSs_*.
+* 1.00 sha 08/07/15 Added support for customized main stream attributes for
+*                   Single Steam Transport and Multi-Stream Transport.
 * </pre>
 *
 ******************************************************************************/
@@ -121,7 +123,8 @@ u32 XDpTxSs_DpTxStart(XDp *InstancePtr, u8 TransportMode, u8 Bpc,
 	Xil_AssertNonvoid((Bpc == XVIDC_BPC_8) || (Bpc == XVIDC_BPC_10) ||
 			(Bpc == XVIDC_BPC_12) || (Bpc == XVIDC_BPC_16));
 	Xil_AssertNonvoid((VidMode < XVIDC_VM_NUM_SUPPORTED) ||
-			(VidMode == XVIDC_VM_USE_EDID_PREFERRED));
+			(VidMode == XVIDC_VM_USE_EDID_PREFERRED) ||
+			(VidMode == XVIDC_VM_CUSTOM));
 
 	/* Check for MST / SST mode */
 	if (TransportMode) {
@@ -159,9 +162,6 @@ u32 XDpTxSs_DpTxStart(XDp *InstancePtr, u8 TransportMode, u8 Bpc,
 		/* Enable downshifting during link training */
 		XDp_TxEnableTrainAdaptive(InstancePtr, 1);
 
-		/* Enable redriver on DP output path */
-		XDp_TxSetHasRedriverInPath(InstancePtr, 1);
-
 		/* Disable main stream to force sending of IDLE patterns. */
 		XDp_TxDisableMainLink(InstancePtr);
 
@@ -249,7 +249,7 @@ u32 XDpTxSs_DpTxStart(XDp *InstancePtr, u8 TransportMode, u8 Bpc,
 				XDp_TxTopologySortSinksByTiling(InstancePtr);
 			}
 		}
-		else {
+		else if (VidMode != XVIDC_VM_CUSTOM) {
 			xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO:MST:Using "
 				"user set resolution.\n\r");
 
@@ -287,6 +287,10 @@ u32 XDpTxSs_DpTxStart(XDp *InstancePtr, u8 TransportMode, u8 Bpc,
 				XDp_TxTopologySortSinksByTiling(InstancePtr);
 			}
 		}
+		else {
+			xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO:MST:Using "
+				"custom set resolution.\n\r");
+		}
 
 		xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO:MST:calculating "
 			"payload...\n\r");
@@ -346,27 +350,63 @@ u32 XDpTxSs_DpTxStart(XDp *InstancePtr, u8 TransportMode, u8 Bpc,
 				XDp_TxCfgMsaSetBpc(InstancePtr,
 					XDP_TX_STREAM_ID1 + StreamIndex, Bpc);
 
-				/* Enable sync clock mode for each stream */
+				/* Check for video mode */
-				XDp_TxCfgMsaEnSynchClkMode(InstancePtr,
+				if (VidMode == XVIDC_VM_CUSTOM) {
-					XDP_TX_STREAM_ID1 + StreamIndex, 1);
+					/* Enable sync clock mode for each
+					 * stream
+					 */
+					XDp_TxCfgMsaEnSynchClkMode(InstancePtr,
+						XDP_TX_STREAM_ID1 +
+						StreamIndex,
+					InstancePtr->TxInstance.MsaConfig[
+					StreamIndex].SynchronousClockMode);
 
-				/* Use standard video mode to calculate MSA */
+					/* Set user pixel width if video mode
-				XDp_TxCfgMsaUseStandardVideoMode(InstancePtr,
+					 * is 1920 x 2160
-					XDP_TX_STREAM_ID1 + StreamIndex,
+					 */
-						VidMode);
+					if ((InstancePtr->TxInstance.MsaConfig[
+						StreamIndex].Vtm.Timing.HActive
+							== 1920) &&
+					(InstancePtr->TxInstance.MsaConfig[
+						StreamIndex].Vtm.Timing.VActive
+							== 2160) &&
+					(InstancePtr->TxInstance.MsaConfig[
+					StreamIndex].OverrideUserPixelWidth
+								== 0)) {
+					InstancePtr->TxInstance.MsaConfig[
+						StreamIndex].UserPixelWidth =
+							4;
+					}
+				}
+				else {
+					/* Enable sync clock mode for each
+					 * stream
+					 */
+					XDp_TxCfgMsaEnSynchClkMode(InstancePtr,
+						XDP_TX_STREAM_ID1 +
+							StreamIndex, 1);
 
-				/* Set user pixel width if video mode is
+					/* Use standard video mode to calculate
-				 * UHD2
+					 * MSA
-				 */
+					 */
-				if ((InstancePtr->TxInstance.MsaConfig[
+					XDp_TxCfgMsaUseStandardVideoMode(
-					StreamIndex].Vtm.VmId ==
+						InstancePtr,
-						XVIDC_VM_UHD2_60_P) &&
+						XDP_TX_STREAM_ID1 +
+						StreamIndex, VidMode);
+
+					/* Set user pixel width if video mode
+					 * is UHD2
+					 */
+					if ((InstancePtr->TxInstance.MsaConfig[
+						StreamIndex].Vtm.VmId ==
+							XVIDC_VM_UHD2_60_P) &&
 					(InstancePtr->TxInstance.MsaConfig[
 					StreamIndex].OverrideUserPixelWidth ==
 									0)) {
 					InstancePtr->TxInstance.MsaConfig[
 						StreamIndex].UserPixelWidth =
 									4;
+					}
 				}
 
 				/* Apply to hardware */
@@ -437,9 +477,6 @@ u32 XDpTxSs_DpTxStart(XDp *InstancePtr, u8 TransportMode, u8 Bpc,
 		/* Enable downshifting during link training */
 		XDp_TxEnableTrainAdaptive(InstancePtr, 1);
 
-		/* Enable redriver on DP output path */
-		XDp_TxSetHasRedriverInPath(InstancePtr, 1);
-
 		/* Disable main stream to force sending of IDLE patterns. */
 		XDp_TxDisableMainLink(InstancePtr);
 
@@ -487,7 +524,7 @@ u32 XDpTxSs_DpTxStart(XDp *InstancePtr, u8 TransportMode, u8 Bpc,
 				VidMode = XVIDC_VM_640x480_60_P;
 			}
 		}
-		else {
+		else if (VidMode != XVIDC_VM_CUSTOM) {
 			xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO:SST:Using "
 				"user set resolution.\n\r");
 
@@ -503,6 +540,10 @@ u32 XDpTxSs_DpTxStart(XDp *InstancePtr, u8 TransportMode, u8 Bpc,
 				VidMode = XVIDC_VM_640x480_60_P;
 			}
 		}
+		else {
+			xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO:SST:Using "
+				"custom set resolution.\n\r");
+		}
 
 		xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO:SST:calculating "
 			"payload...\n\r");
@@ -535,12 +576,21 @@ u32 XDpTxSs_DpTxStart(XDp *InstancePtr, u8 TransportMode, u8 Bpc,
 		XDp_TxClearMsaValues(InstancePtr, XDP_TX_STREAM_ID3);
 		XDp_TxClearMsaValues(InstancePtr, XDP_TX_STREAM_ID4);
 
-		InstancePtr->TxInstance.MsaConfig[0].DynamicRange = 0;
-		InstancePtr->TxInstance.MsaConfig[0].YCbCrColorimetry = 0;
-
 		/* Enable sync clock mode */
-		XDp_TxCfgMsaEnSynchClkMode(InstancePtr,
+		if (VidMode == XVIDC_VM_CUSTOM) {
+			XDp_TxCfgMsaEnSynchClkMode(InstancePtr,
+				XDP_TX_STREAM_ID1,
+					InstancePtr->TxInstance.MsaConfig[
+						0].SynchronousClockMode);
+		}
+		else {
+			InstancePtr->TxInstance.MsaConfig[
+				0].DynamicRange = 0;
+			InstancePtr->TxInstance.MsaConfig[
+				0].YCbCrColorimetry = 0;
+			XDp_TxCfgMsaEnSynchClkMode(InstancePtr,
 						XDP_TX_STREAM_ID1, 1);
+		}
 
 		/* Set user provided BPC to stream 1 */
 		XDp_TxCfgMsaSetBpc(InstancePtr, XDP_TX_STREAM_ID1, Bpc);
@@ -548,16 +598,30 @@ u32 XDpTxSs_DpTxStart(XDp *InstancePtr, u8 TransportMode, u8 Bpc,
 		/* Set user standard video mode for stream 1 to populate
 		 * MSA values
 		 */
-		XDp_TxCfgMsaUseStandardVideoMode(InstancePtr,
+		if (VidMode != XVIDC_VM_CUSTOM) {
+			XDp_TxCfgMsaUseStandardVideoMode(InstancePtr,
 					XDP_TX_STREAM_ID1, VidMode);
 
-		/* Set user pixel width if video mode is UHD2 */
+			/* Set user pixel width if video mode is UHD2 */
-		if ((InstancePtr->TxInstance.MsaConfig[0].Vtm.VmId ==
+			if ((InstancePtr->TxInstance.MsaConfig[0].Vtm.VmId ==
-			XVIDC_VM_UHD2_60_P) &&
+				XVIDC_VM_UHD2_60_P) &&
-			(InstancePtr->TxInstance.MsaConfig[
+				(InstancePtr->TxInstance.MsaConfig[
-				0].OverrideUserPixelWidth == 0)) {
+					0].OverrideUserPixelWidth == 0)) {
-			InstancePtr->TxInstance.MsaConfig[
+					InstancePtr->TxInstance.MsaConfig[
-				0].UserPixelWidth = 4;
+					0].UserPixelWidth = 4;
+			}
+		}
+		else {
+			/* Set user pixel width if video mode is 1920 x 2160 */
+			if ((InstancePtr->TxInstance.MsaConfig[
+				0].Vtm.Timing.HActive == 1920) &&
+				(InstancePtr->TxInstance.MsaConfig[
+					0].Vtm.Timing.VActive == 2160) &&
+				(InstancePtr->TxInstance.MsaConfig[
+					0].OverrideUserPixelWidth == 0)) {
+				InstancePtr->TxInstance.MsaConfig[
+					0].UserPixelWidth = 4;
+			}
 		}
 
 		/* Set video mode */
@@ -785,8 +849,18 @@ static u32 Dp_CheckBandwidth(XDp *InstancePtr, u8 Bpc, XVidC_VideoMode VidMode)
 	if ((MstCapable != XST_SUCCESS) ||
 				(InstancePtr->TxInstance.MstEnable == 0)) {
 		u32 TransferUnitSize = 64;
-		u32 VideoBw = (XVidC_GetPixelClockHzByVmId(VidMode) / 1000) *
+		u32 VideoBw;
-				BitsPerPixel / 8;
+
+		/* Check video mode */
+		if (VidMode != XVIDC_VM_CUSTOM){
+			VideoBw = (XVidC_GetPixelClockHzByVmId(VidMode) /
+					1000) * BitsPerPixel / 8;
+		}
+		else {
+			VideoBw = InstancePtr->TxInstance.MsaConfig[
+				0].PixelClockHz / 1000 * BitsPerPixel / 8;
+		}
+
 		u32 AvgBytesPerTU = (VideoBw * TransferUnitSize) / LinkBw;
 
 		xdbg_printf(XDBG_DEBUG_GENERAL,"SS:INFO:Checking link "
@@ -821,8 +895,17 @@ static u32 Dp_CheckBandwidth(XDp *InstancePtr, u8 Bpc, XVidC_VideoMode VidMode)
 		u32 TsFrac;
 		u16 Pbn;
 
-		PeakPixelBw = ((double)XVidC_GetPixelClockHzByVmId(VidMode) /
+		if (VidMode != XVIDC_VM_CUSTOM){
+			PeakPixelBw =
+				((double)XVidC_GetPixelClockHzByVmId(VidMode) /
 					1000000) * ((double)BitsPerPixel / 8);
+		}
+		else {
+			PeakPixelBw =
+				((double)InstancePtr->TxInstance.MsaConfig[
+					0].PixelClockHz / 1000000) *
+					((double)BitsPerPixel / 8);
+		}
 
 		Pbn = 1.006 * PeakPixelBw * ((double)64 / 54);
 

XilinxProcessorIPLib/drivers/dptxss/src/dualsplitter/xdptxss_dualsplitter.c

@@ -41,10 +41,11 @@
 * MODIFICATION HISTORY:
 *
 * Ver  Who Date     Changes
-* ---- --- -------- --------------------------------------------------
+* ---- --- -------- -----------------------------------------------------------
 * 1.00 sha 01/29/15 Initial release.
 * 1.00 sha 07/21/15 Renamed file name with prefix xdptxss_* and function
 *                   name with prefix XDpTxSs_*.
+* 1.00 sha 08/07/15 Removed video mode check.
 * </pre>
 *
 ******************************************************************************/
@@ -99,7 +100,6 @@ u32 XDpTxSs_DsSetup(XDualSplitter *InstancePtr, u8 VertSplit,
 	u16 Height;
 	u16 Width;
 	u32 UserPixelWidth;
-	XVidC_VideoMode VmId;
 
 	/* Verify arguments. */
 	Xil_AssertNonvoid(InstancePtr != NULL);
@@ -107,14 +107,13 @@ u32 XDpTxSs_DsSetup(XDualSplitter *InstancePtr, u8 VertSplit,
 	Xil_AssertNonvoid((VertSplit == TRUE) || (VertSplit == FALSE));
 
 	UserPixelWidth = MsaConfig->UserPixelWidth;
-	VmId = MsaConfig->Vtm.VmId;
 	Height = MsaConfig->Vtm.Timing.VActive;
 
 	/* Dual Splitter register update enable */
 	XDualSplitter_RegUpdateEnable(InstancePtr);
 
 	/* Required parameters based on vertical split mode and 4k2k@60p */
-	if ((VertSplit) && (VmId == XVIDC_VM_UHD2_60_P)) {
+	if (VertSplit) {
 		ImgSegments = 0x2;
 		OSamples = 0x4;
 		ISamples = 0x4;

XilinxProcessorIPLib/drivers/dptxss/src/hdcp1x/xdptxss_hdcp1x.c

@@ -0,0 +1,69 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xdptxss_hdcp1x.c
+*
+* This file contains a minimal set of functions for the High-Bandwidth Content
+* Protection core to configure.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver  Who Date     Changes
+* ---- --- -------- -----------------------------------------------------
+* 1.00 sha 08/07/15 Initial release.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xdptxss_hdcp1x.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/************************** Function Definitions *****************************/

XilinxProcessorIPLib/drivers/dptxss/src/hdcp1x/xdptxss_hdcp1x.h

@@ -0,0 +1,83 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xdptxss_hdcp1x.h
+*
+* This is the header file for Xilinx DisplayPort Transmitter Subsystem
+* sub-core, is High-Bandwidth Content Protection (HDCP).
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver  Who Date     Changes
+* ---- --- -------- -----------------------------------------------------
+* 1.00 sha 08/07/15 Initial release.
+* </pre>
+*
+******************************************************************************/
+#ifndef XDPTXSS_HDCP1X_H_
+#define XDPTXSS_HDCP1X_H_	/**< Prevent circular inclusions
+				  *  by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#if (XPAR_XHDCP_NUM_INSTANCES > 0)
+#include "xhdcp1x.h"
+#endif
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Declarations ****************************/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* End of protection macro */

XilinxProcessorIPLib/drivers/dptxss/src/vtc/xdptxss_vtc.c

@@ -41,10 +41,11 @@
 * MODIFICATION HISTORY:
 *
 * Ver  Who Date     Changes
-* ---- --- -------- --------------------------------------------------
+* ---- --- -------- -----------------------------------------------------------
 * 1.00 sha 01/29/15 Initial release.
 * 1.00 sha 07/21/15 Renamed file name with prefix xdptxss_* and function
 *                   name with prefix XDpTxSs_*
+* 1.00 sha 08/07/15 Set interlace to zero when video mode is XVIDC_VM_CUSTOM.
 * </pre>
 *
 ******************************************************************************/
@@ -150,8 +151,13 @@ u32 XDpTxSs_VtcSetup(XVtc *InstancePtr, XDp_TxMainStreamAttributes *MsaConfig)
 	VideoTiming.VSyncPolarity = MsaConfig->Vtm.Timing.VSyncPolarity;
 
 	/* Check for interlaced mode */
-	VideoTiming.Interlaced = XVidC_VideoTimingModes[
+	if (MsaConfig->Vtm.VmId != XVIDC_VM_CUSTOM) {
-		MsaConfig->Vtm.VmId].Timing.F1VTotal == 0 ? 0: 1;
+		VideoTiming.Interlaced = XVidC_VideoTimingModes[
+			MsaConfig->Vtm.VmId].Timing.F1VTotal == 0 ? 0: 1;
+	}
+	else {
+		VideoTiming.Interlaced = 0;
+	}
 
 	/* Set timing */
 	XVtc_SetGeneratorTiming(InstancePtr, &VideoTiming);

XilinxProcessorIPLib/drivers/dptxss/src/xdptxss.c

@@ -45,9 +45,11 @@
 * MODIFICATION HISTORY:
 *
 * Ver  Who Date     Changes
-* ---- --- -------- --------------------------------------------------
+* ---- --- -------- ---------------------------------------------------------
 * 1.00 sha 01/29/15 Initial release.
 * 1.00 sha 07/21/15 Renamed sub-cores functions with prefix XDpTxSs_*
+* 1.00 sha 08/07/15 Added support for customized main stream attributes.
+*                   Added HDCP instance into global sub-cores structure.
 * </pre>
 *
 ******************************************************************************/
@@ -56,6 +58,7 @@
 
 #include "xdptxss.h"
 #include "string.h"
+#include "math.h"
 
 /************************** Constant Definitions *****************************/
 
@@ -69,6 +72,9 @@
 typedef struct {
 #if (XPAR_XDUALSPLITTER_NUM_INSTANCES > 0)
 	XDualSplitter DsInst;
+#endif
+#if (XPAR_XHDCP_NUM_INSTANCES > 0)
+	XHdcp1x Hdcp1xInst;
 #endif
 	XDp DpInst;
 	XVtc VtcInst[XDPTXSS_NUM_STREAMS];
@@ -77,6 +83,9 @@ typedef struct {
 /************************** Function Prototypes ******************************/
 
 static void DpTxSs_GetIncludedSubCores(XDpTxSs *InstancePtr);
+static void DpTxSs_CalculateMsa(XDpTxSs *InstancePtr, u8 Stream);
+static u32 DpTxSs_CheckRxDeviceMode(XDpTxSs *InstancePtr);
+static u32 DpTxSs_SetupSubCores(XDpTxSs *InstancePtr);
 
 /************************** Variable Definitions *****************************/
 
@@ -162,12 +171,6 @@ u32 XDpTxSs_CfgInitialize(XDpTxSs *InstancePtr, XDpTxSs_Config *CfgPtr,
 		DpConfig.BaseAddr += InstancePtr->Config.BaseAddress;
 		XDp_CfgInitialize(InstancePtr->DpPtr, &DpConfig,
 				DpConfig.BaseAddr);
-		Status = XDp_Initialize(InstancePtr->DpPtr);
-		if (Status != XST_SUCCESS) {
-			xdbg_printf(XDBG_DEBUG_GENERAL,"SS ERR:: DP TX "
-				"initialization failed!\n\r");
-			return XST_FAILURE;
-		}
 
 		/* Initialize user configurable parameters */
 		InstancePtr->UsrOpt.VmId = XVIDC_VM_USE_EDID_PREFERRED;
@@ -231,10 +234,15 @@ u32 XDpTxSs_CfgInitialize(XDpTxSs *InstancePtr, XDpTxSs_Config *CfgPtr,
 		}
 	}
 
-	/* Reset the hardware and set the flag to indicate the
+	/* Initialize DP */
-	 * subsystem is ready
+	Status = XDp_Initialize(InstancePtr->DpPtr);
-	 */
+	if (Status != XST_SUCCESS) {
-	XDpTxSs_Reset(InstancePtr);
+		xdbg_printf(XDBG_DEBUG_GENERAL,"SS ERR:: DP TX initialization "
+			"failed!\n\r");
+		return XST_FAILURE;
+	}
+
+	/* Set the flag to indicate the subsystem is ready */
 	InstancePtr->IsReady = (u32)XIL_COMPONENT_IS_READY;
 
 	return XST_SUCCESS;
@@ -300,59 +308,16 @@ void XDpTxSs_Reset(XDpTxSs *InstancePtr)
 u32 XDpTxSs_Start(XDpTxSs *InstancePtr)
 {
 	u32 Status;
-	u32 Index;
-	u8 SinkTotal;
-#if (XPAR_XDUALSPLITTER_NUM_INSTANCES > 0)
-	u8 VertSplit;
-#endif
 
 	/* Verify arguments. */
 	Xil_AssertNonvoid(InstancePtr != NULL);
 	Xil_AssertNonvoid((InstancePtr->UsrOpt.MstSupport == 0) ||
 				(InstancePtr->UsrOpt.MstSupport == 1));
 
-	/* Check for downstream device connected */
+	/* Check RX device in MST/SST */
-	if (!XDp_TxIsConnected(InstancePtr->DpPtr)) {
+	Status = DpTxSs_CheckRxDeviceMode(InstancePtr);
-		xdbg_printf(XDBG_DEBUG_GENERAL,"SS ERR: RX device "
+	if (Status != XST_SUCCESS) {
-				"is not connected!\n\r");
+		return Status;
-		return XST_FAILURE;
-	}
-
-	/* Check RX device is MST capable */
-	Status = XDp_TxMstCapable(InstancePtr->DpPtr);
-	if ((Status == XST_SUCCESS) && (InstancePtr->Config.MstSupport)) {
-		if (InstancePtr->UsrOpt.MstSupport <
-					InstancePtr->Config.MstSupport) {
-			/* Enable SST mode when RX is MST */
-			InstancePtr->UsrOpt.MstSupport = 0;
-
-			/* set maximum number of streams to one */
-			InstancePtr->UsrOpt.NumOfStreams = 1;
-			xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO: Setting "
-				"to SST even though RX device is with MST "
-					"capable!\n\r");
-		}
-		else {
-			/* Enable MST mode */
-			InstancePtr->UsrOpt.MstSupport =
-					InstancePtr->Config.MstSupport;
-
-			/* Restore maximum number of supported streams */
-			InstancePtr->UsrOpt.NumOfStreams =
-					InstancePtr->Config.NumMstStreams;
-			xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO: RX device "
-					"is with MST capable!\n\r");
-		}
-	}
-	else {
-		/* Enable SST mode */
-		InstancePtr->UsrOpt.MstSupport = 0;
-
-		/* set maximum number of streams to one */
-		InstancePtr->UsrOpt.NumOfStreams = 1;
-		xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO: RX device "
-			"is with SST capable. OR Design supports only SST "
-				"mode.\n\r");
 	}
 
 	/* Start DisplayPort sub-core configuration */
@@ -371,53 +336,84 @@ u32 XDpTxSs_Start(XDpTxSs *InstancePtr)
 	InstancePtr->UsrOpt.VmId =
 			InstancePtr->DpPtr->TxInstance.MsaConfig[0].Vtm.VmId;
 
-	/* Set number of stream to number of sinks found. Make sure that sink
+	/* Setup subsystem sub-cores */
-	 * total does not exceed total number supported streams in by Subsystem
+	Status = DpTxSs_SetupSubCores(InstancePtr);
-	 * configuration.
+	if (Status != XST_SUCCESS) {
-	 */
+		return Status;
-	if (InstancePtr->UsrOpt.MstSupport) {
-		SinkTotal = InstancePtr->DpPtr->TxInstance.Topology.SinkTotal;
-		InstancePtr->UsrOpt.NumOfStreams =
-		(SinkTotal > InstancePtr->UsrOpt.NumOfStreams)?
-			InstancePtr->UsrOpt.NumOfStreams:SinkTotal;
 	}
 
-#if (XPAR_XDUALSPLITTER_NUM_INSTANCES > 0)
+	return XST_SUCCESS;
-	if (InstancePtr->DsPtr) {
+}
-		/* Check video mode and MST support */
-		if ((InstancePtr->UsrOpt.VmId == XVIDC_VM_UHD2_60_P)
-				&& (InstancePtr->UsrOpt.MstSupport)) {
 
-			/* Vertical split mode */
+/*****************************************************************************/
-			VertSplit = (TRUE);
+/**
-		}
+*
-		else {
+* This function starts the DisplayPort Transmitter Subsystem with custom
-			/* Bypass mode */
+* multi-stream attributes (MSA)including all sub-cores.
-			VertSplit = (FALSE);
+*
-		}
+* @param	InstancePtr is a pointer to the XDpTxSs core instance.
+* @param	MsaConfigCustom is the structure that will be used to copy the
+*		main stream attributes from (into
+*		InstancePtr->DpPtr->TxInstance.MsaConfig).
+*
+* @return
+*		- XST_SUCCESS, if DP TX Subsystem and its included sub-cores
+*		configured successfully.
+*		- XST_FAILURE, otherwise.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 XDpTxSs_StartCustomMsa(XDpTxSs *InstancePtr,
+				XDpTxSs_MainStreamAttributes *MsaConfigCustom)
+{
+	u32 Status;
+	u8 Index;
 
-		/* Setup Dual Splitter in either bypass/vertical split mode */
+	/* Verify arguments. */
-		Status = XDpTxSs_DsSetup(InstancePtr->DsPtr, VertSplit,
+	Xil_AssertNonvoid(InstancePtr != NULL);
-				&InstancePtr->DpPtr->TxInstance.MsaConfig[0]);
+	Xil_AssertNonvoid((InstancePtr->UsrOpt.MstSupport == 0) ||
-		if (Status != XST_SUCCESS) {
+				(InstancePtr->UsrOpt.MstSupport == 1));
-			xdbg_printf(XDBG_DEBUG_GENERAL,"SS ERR: DS start "
+	Xil_AssertNonvoid(MsaConfigCustom != NULL);
-				"failed!\n\r");
+
+	/* Check RX device in MST/SST */
+	Status = DpTxSs_CheckRxDeviceMode(InstancePtr);
+	if (Status != XST_SUCCESS) {
 			return Status;
-		}
 	}
-#endif
 
-	/* Setup VTC */
+	/* Clear MSA values */
-	for (Index = 0; Index < InstancePtr->UsrOpt.NumOfStreams; Index++) {
+	(void)memset((void *)InstancePtr->DpPtr->TxInstance.MsaConfig, 0,
-		if (InstancePtr->VtcPtr[Index]) {
+		InstancePtr->UsrOpt.NumOfStreams *
-			Status = XDpTxSs_VtcSetup(InstancePtr->VtcPtr[Index],
+			sizeof(XDpTxSs_MainStreamAttributes));
-			&InstancePtr->DpPtr->TxInstance.MsaConfig[Index]);
+
-			if (Status != XST_SUCCESS) {
+	/* Copy user provided MSA values */
-				xdbg_printf(XDBG_DEBUG_GENERAL,"SS ERR: "
+	(void)memcpy((void *)InstancePtr->DpPtr->TxInstance.MsaConfig,
-					"VTC%d setup failed!\n\r", Index);
+		(const void *)MsaConfigCustom,
-				return Status;
+			InstancePtr->UsrOpt.NumOfStreams *
-			}
+				sizeof(XDpTxSs_MainStreamAttributes));
-		}
+
+	/* Calculate required MSA values from user provided MSA values */
+	for (Index = 1; Index <= InstancePtr->UsrOpt.NumOfStreams; Index ++) {
+		DpTxSs_CalculateMsa(InstancePtr, Index);
+	}
+
+	/* Start DisplayPort sub-core configuration */
+	Status = XDpTxSs_DpTxStart(InstancePtr->DpPtr,
+			InstancePtr->UsrOpt.MstSupport,
+				InstancePtr->UsrOpt.Bpc,
+					InstancePtr->UsrOpt.VmId);
+	if (Status != XST_SUCCESS) {
+		xdbg_printf(XDBG_DEBUG_GENERAL,"SS ERR: DP custom start "
+			"failed in %s!\n\r",
+				InstancePtr->UsrOpt.MstSupport?"MST":"SST");
+		return Status;
+	}
+
+	/* Setup subsystem sub-cores */
+	Status = DpTxSs_SetupSubCores(InstancePtr);
+	if (Status != XST_SUCCESS) {
+		return Status;
 	}
 
 	return XST_SUCCESS;
@@ -890,6 +886,34 @@ u32 XDpTxSs_IsMstCapable(XDpTxSs *InstancePtr)
 	return Status;
 }
 
+/*****************************************************************************/
+/**
+*
+* This function sets software switch that specify whether or not a redriver
+* exits on the DisplayPort output path.
+*
+* @param	InstancePtr is a pointer to the XDpTxSs core instance.
+* @param	Set establishes that a redriver exists in the DisplayPort output
+*		path.
+*		1 = Set redriver in the DisplayPort output path.
+*		0 = Unset redriver in the DisplayPort output path.
+*
+* @return	None.
+*
+* @note		Set the redriver in the DisplayPort output path before
+*		starting the training.
+*
+******************************************************************************/
+void XDpTxSs_SetHasRedriverInPath(XDpTxSs *InstancePtr, u8 Set)
+{
+	/* Verify arguments.*/
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid((Set == 1) || (Set == 0));
+
+	/* Set redriver in the DisplayPort output path */
+	XDp_TxSetHasRedriverInPath(InstancePtr->DpPtr, Set);
+}
+
 /*****************************************************************************/
 /**
 *
@@ -924,4 +948,250 @@ static void DpTxSs_GetIncludedSubCores(XDpTxSs *InstancePtr)
 				(&DpTxSsSubCores.VtcInst[Index]): NULL);
 	}
 }
+
+/*****************************************************************************/
+/**
+*
+* This function computes multi-stream attribute and populates frame rate,
+* pixel clock and so on.
+*
+* @param	InstancePtr is a pointer to the XDpTxSs core instance.
+* @param	Stream is the stream number for which the MSA values will be
+*		computed for.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void DpTxSs_CalculateMsa(XDpTxSs *InstancePtr, u8 Stream)
+{
+	XDpTxSs_MainStreamAttributes *MsaConfig;
+	XVidC_VideoMode VidMode;
+	double FrameClk;
+	u32 FrameRate;
+	u32 ClkFreq;
+	u8 LinkRate;
+
+	MsaConfig = &InstancePtr->DpPtr->TxInstance.MsaConfig[Stream - 1];
+	LinkRate = InstancePtr->DpPtr->TxInstance.LinkConfig.LinkRate;
+
+	/*Calculate pixel clock in HZ */
+	ClkFreq = (LinkRate * 27 * MsaConfig->MVid) / MsaConfig->NVid;
+	MsaConfig->PixelClockHz = ((u32)ClkFreq) * 1000000;
+
+	/*Calculate frame rate */
+	FrameClk = ceil((ClkFreq * 1000000.0) / (MsaConfig->Vtm.Timing.HTotal *
+				MsaConfig->Vtm.Timing.F0PVTotal));
+	FrameRate = (u32)FrameClk;
+
+	/* Round of frame rate */
+	if ((FrameRate == 59) || (FrameRate == 61)) {
+		FrameRate = 60;
+	}
+	else if ((FrameRate == 29) || (FrameRate == 31)) {
+		FrameRate = 30;
+	}
+	else if ((FrameRate == 76) || (FrameRate == 74)) {
+		FrameRate = 75;
+	}
+	MsaConfig->Vtm.FrameRate = FrameRate;
+
+	/* Calculate horizontal front porch */
+	MsaConfig->Vtm.Timing.HFrontPorch = MsaConfig->Vtm.Timing.HTotal -
+			MsaConfig->HStart - MsaConfig->Vtm.Timing.HActive;
+
+	/* Calculate horizontal back porch */
+	MsaConfig->Vtm.Timing.HBackPorch = MsaConfig->HStart -
+			MsaConfig->Vtm.Timing.HSyncWidth;
+
+	/* Calculate vertical frame zero front porch */
+	MsaConfig->Vtm.Timing.F0PVFrontPorch =
+		MsaConfig->Vtm.Timing.F0PVTotal - MsaConfig->VStart -
+			MsaConfig->Vtm.Timing.VActive;
+
+	/* Calculate vertical frame zero back porch */
+	MsaConfig->Vtm.Timing.F0PVBackPorch = MsaConfig->VStart -
+			MsaConfig->Vtm.Timing.F0PVSyncWidth;
+
+	/* Set frame 1 parameters */
+	MsaConfig->Vtm.Timing.F1VFrontPorch = 0;
+	MsaConfig->Vtm.Timing.F1VSyncWidth = 0;
+	MsaConfig->Vtm.Timing.F1VBackPorch = 0;
+	MsaConfig->Vtm.Timing.F1VTotal = 0;
+
+	/* Check video mode is present in video common library */
+	VidMode = XVidC_GetVideoModeId(MsaConfig->Vtm.Timing.HActive,
+			MsaConfig->Vtm.Timing.VActive,
+				MsaConfig->Vtm.FrameRate,
+					XVIDC_VF_PROGRESSIVE);
+	if (VidMode == XVIDC_VM_NOT_SUPPORTED) {
+		MsaConfig->Vtm.VmId = XVIDC_VM_CUSTOM;
+		InstancePtr->UsrOpt.VmId = XVIDC_VM_CUSTOM;
+	}
+	else {
+		MsaConfig->Vtm.VmId = XVIDC_VM_CUSTOM;
+		InstancePtr->UsrOpt.VmId = XVIDC_VM_CUSTOM;
+	}
+
+	/* Set bits per color */
+	InstancePtr->UsrOpt.Bpc = MsaConfig->BitsPerColor;
+
+	/* Use custom MSA */
+	XDp_TxCfgMsaUseCustom(InstancePtr->DpPtr, Stream, MsaConfig, TRUE);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function checks whether RX device in multi-stream (MST) / Single Stream
+* transport mode.
+*
+* @param	InstancePtr is a pointer to the XDpTxSs core instance.
+*
+* @return
+*		- XST_FAILURE if DisplayPort TX initialization failed or RX
+*		device is not connected.
+*		- XST_SUCCESS if RX device check is successful.
+*
+* @note		None.
+*
+******************************************************************************/
+static u32 DpTxSs_CheckRxDeviceMode(XDpTxSs *InstancePtr)
+{
+	u32 Status;
+
+	/* Check for downstream device connected */
+	if (!XDp_TxIsConnected(InstancePtr->DpPtr)) {
+		xdbg_printf(XDBG_DEBUG_GENERAL,"SS ERR: RX device "
+				"is not connected!\n\r");
+		return XST_FAILURE;
+	}
+
+	/* Check RX device is MST capable */
+	Status = XDp_TxMstCapable(InstancePtr->DpPtr);
+	if ((Status == XST_SUCCESS) && (InstancePtr->Config.MstSupport)) {
+		if (InstancePtr->UsrOpt.MstSupport <
+					InstancePtr->Config.MstSupport) {
+			/* Enable SST mode when RX is MST */
+			InstancePtr->UsrOpt.MstSupport = 0;
+
+			/* set maximum number of streams to one */
+			InstancePtr->UsrOpt.NumOfStreams = 1;
+			xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO: Setting "
+				"to SST even though RX device is with MST "
+					"capable!\n\r");
+		}
+		else {
+			/* Enable MST mode */
+			InstancePtr->UsrOpt.MstSupport =
+					InstancePtr->Config.MstSupport;
+
+			/* Restore maximum number of supported streams */
+			InstancePtr->UsrOpt.NumOfStreams =
+					InstancePtr->Config.NumMstStreams;
+			xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO: RX device "
+					"is with MST capable!\n\r");
+		}
+	}
+	else {
+		/* Enable SST mode */
+		InstancePtr->UsrOpt.MstSupport = 0;
+
+		/* set maximum number of streams to one */
+		InstancePtr->UsrOpt.NumOfStreams = 1;
+		xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO: RX device "
+			"is with SST capable. OR Design supports only SST "
+				"mode.\n\r");
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function configures DisplayPort TX subsystem sub-cores.
+*
+* @param	InstancePtr is a pointer to the XDpTxSs core instance.
+*
+* @return
+*		- XST_FAILURE if all sub-cores configuration failed.
+*		- XST_SUCCESS if all sub-cores configuration was successful.
+*
+* @note		None.
+*
+******************************************************************************/
+static u32 DpTxSs_SetupSubCores(XDpTxSs *InstancePtr)
+{
+	u32 Status;
+	u32 Index;
+	u8 SinkTotal;
+#if (XPAR_XDUALSPLITTER_NUM_INSTANCES > 0)
+	u8 VertSplit;
+#endif
+	/* Set number of stream to number of sinks found. Make sure that sink
+	 * total does not exceed total number supported streams in by Subsystem
+	 * configuration.
+	 */
+	if (InstancePtr->UsrOpt.MstSupport) {
+		SinkTotal = InstancePtr->DpPtr->TxInstance.Topology.SinkTotal;
+		InstancePtr->UsrOpt.NumOfStreams =
+		(SinkTotal > InstancePtr->UsrOpt.NumOfStreams)?
+			InstancePtr->UsrOpt.NumOfStreams:SinkTotal;
+	}
+
+#if (XPAR_XDUALSPLITTER_NUM_INSTANCES > 0)
+	if (InstancePtr->DsPtr) {
+		/* Check video mode and MST support */
+		if (InstancePtr->UsrOpt.MstSupport) {
+			if ((InstancePtr->UsrOpt.VmId == XVIDC_VM_UHD2_60_P)) {
+				/* Vertical split mode */
+				VertSplit = (TRUE);
+			}
+			else if ((InstancePtr->UsrOpt.VmId ==
+				XVIDC_VM_CUSTOM) &&
+				(InstancePtr->DpPtr->TxInstance.MsaConfig[
+				0].Vtm.Timing.HActive == 1920) &&
+				(InstancePtr->DpPtr->TxInstance.MsaConfig[
+					0].Vtm.Timing.VActive == 2160)) {
+				/* Vertical split mode */
+				VertSplit = (TRUE);
+			}
+			else {
+				/* Bypass mode */
+				VertSplit = FALSE;
+			}
+		}
+		else {
+			/* Bypass mode */
+			VertSplit = FALSE;
+		}
+
+		/* Setup Dual Splitter in either bypass/vertical split mode */
+		Status = XDpTxSs_DsSetup(InstancePtr->DsPtr, VertSplit,
+				&InstancePtr->DpPtr->TxInstance.MsaConfig[0]);
+		if (Status != XST_SUCCESS) {
+			xdbg_printf(XDBG_DEBUG_GENERAL,"SS ERR: DS start "
+				"failed!\n\r");
+			return Status;
+		}
+	}
+#endif
+
+	/* Setup VTC */
+	for (Index = 0; Index < InstancePtr->UsrOpt.NumOfStreams; Index++) {
+		if (InstancePtr->VtcPtr[Index]) {
+			Status = XDpTxSs_VtcSetup(InstancePtr->VtcPtr[Index],
+			&InstancePtr->DpPtr->TxInstance.MsaConfig[Index]);
+			if (Status != XST_SUCCESS) {
+				xdbg_printf(XDBG_DEBUG_GENERAL,"SS ERR: "
+					"VTC%d setup failed!\n\r", Index);
+				return Status;
+			}
+		}
+	}
+
+	return XST_SUCCESS;
+}
 /** @} */

XilinxProcessorIPLib/drivers/dptxss/src/xdptxss.h

@@ -91,9 +91,14 @@
 * MODIFICATION HISTORY:
 *
 * Ver  Who Date     Changes
-* ---- --- -------- --------------------------------------------------
+* ---- --- -------- ---------------------------------------------------------
 * 1.00 sha 01/29/15 Initial release.
 * 1.00 sha 07/21/15 Included renamed sub-cores header files.
+* 1.00 sha 08/07/15 Added new handler types: lane count, link rate,
+*                   pre-emphasis voltage swing adjust and set MSA.
+*                   Added support for customized main stream attributes.
+*                   Added function: XDpTxSs_SetHasRedriverInPath.
+*                   Added HDCP support data structure.
 * </pre>
 *
 ******************************************************************************/
@@ -116,6 +121,7 @@ extern "C" {
 /* Subsystem sub-cores header files */
 #include "xdptxss_dptx.h"
 #include "xdptxss_dualsplitter.h"
+#include "xdptxss_hdcp1x.h"
 #include "xdptxss_vtc.h"
 
 /************************** Constant Definitions *****************************/
@@ -131,9 +137,22 @@ typedef enum {
 	XDPTXSS_HANDLER_DP_HPD_EVENT = 1,	/**< A HPD event interrupt
 						  *  type for DisplayPort
 						  *  core */
-	XDPTXSS_HANDLER_DP_HPD_PULSE		/**< A HPD pulse interrupt
+	XDPTXSS_HANDLER_DP_HPD_PULSE,		/**< A HPD pulse interrupt
 						  *  type for DisplayPort
 						  *  core */
+	XDPTXSS_HANDLER_DP_LANE_COUNT_CHG,	/**< Lane count change
+						  *  interrupt type for
+						  *  DisplayPort core */
+	XDPTXSS_HANDLER_DP_LINK_RATE_CHG,	/**< Link rate change
+						  *  interrupt type for
+						  *  DisplayPort core */
+	XDPTXSS_HANDLER_DP_PE_VS_ADJUST,	/**< Pre-emphasis and voltage
+						  *  swing change interrupt
+						  *  type for DisplayPort
+						  *  core */
+	XDPTXSS_HANDLER_DP_SET_MSA		/**< Set MSA immediate change
+						  *  change interrupt type for
+						  *  DisplayPort core */
 } XDpTxSs_HandlerType;
 
 /**
@@ -177,6 +196,17 @@ typedef struct {
 				  *  information */
 } XDpTxSs_DpSubCore;
 
+#if (XPAR_XHDCP_NUM_INSTANCES > 0)
+/**
+* High-Bandwidth Content Protection (HDCP) Sub-core structure.
+*/
+typedef struct {
+	u16 IsPresent;		/**< Flag to hold the presence of HDCP core */
+	XHdcp1x_Config Hdcp1xConfig;	/**< HDCP core configuration
+					  *  information */
+} XDpTxSs_Hdcp1xSubCore;
+#endif
+
 /**
 * This typedef contains configuration information for the DisplayPort
 * Transmitter Subsystem core. Each DisplayPort TX Subsystem core should have
@@ -200,6 +230,9 @@ typedef struct {
 	u8 NumMstStreams;	/**< The total number of MST streams supported
 				  *  by this core instance. */
 	XDpTxSs_DpSubCore DpSubCore;	/**< DisplayPort Configuration */
+#if (XPAR_XHDCP_NUM_INSTANCES > 0)
+	XDpTxSs_Hdcp1xSubCore Hdcp1xSubCore;	/**< HDCP Configuration */
+#endif
 #if (XPAR_XDUALSPLITTER_NUM_INSTANCES > 0)
 	XDpTxSs_DsSubCore DsSubCore;	/**< Dual Splitter Configuration */
 #endif
@@ -219,6 +252,9 @@ typedef struct {
 	/* Sub-core instances */
 #if (XPAR_XDUALSPLITTER_NUM_INSTANCES > 0)
 	XDualSplitter *DsPtr;		/**< Dual Splitter sub-core instance */
+#endif
+#if (XPAR_XHDCP_NUM_INSTANCES > 0)
+	XHdcp1x *Hdcp1xPtr;		/**< HDCP sub-core instance */
 #endif
 	XDp *DpPtr;			/**< DisplayPort sub-core instance */
 	XVtc *VtcPtr[XDPTXSS_NUM_STREAMS];/**< Maximum number of VTC sub-core
@@ -234,6 +270,11 @@ typedef struct {
 */
 #define XDpTxSs_TimerHandler		XDp_TimerHandler
 
+/**
+* Main-Stream attributes.
+*/
+#define XDpTxSs_MainStreamAttributes	XDp_TxMainStreamAttributes
+
 /************************** Function Prototypes ******************************/
 
 /* Initialization function in xdptxss_sinit.c */
@@ -243,6 +284,8 @@ XDpTxSs_Config* XDpTxSs_LookupConfig(u16 DeviceId);
 u32 XDpTxSs_CfgInitialize(XDpTxSs *InstancePtr, XDpTxSs_Config *CfgPtr,
 				u32 EffectiveAddr);
 u32 XDpTxSs_Start(XDpTxSs *InstancePtr);
+u32 XDpTxSs_StartCustomMsa(XDpTxSs *InstancePtr,
+		XDpTxSs_MainStreamAttributes *MsaConfigCustom);
 void XDpTxSs_Stop(XDpTxSs *InstancePtr);
 void XDpTxSs_Reset(XDpTxSs *InstancePtr);
 u32 XDpTxSs_SetBpc(XDpTxSs *InstancePtr, u8 Bpc);
@@ -256,6 +299,7 @@ u32 XDpTxSs_IsMstCapable(XDpTxSs *InstancePtr);
 u32 XDpTxSs_GetRxCapabilities(XDpTxSs *InstancePtr);
 u32 XDpTxSs_GetEdid(XDpTxSs *InstancePtr, u8 *Edid);
 u32 XDpTxSs_GetRemoteEdid(XDpTxSs *InstancePtr, u8 SinkNum, u8 *Edid);
+void XDpTxSs_SetHasRedriverInPath(XDpTxSs *InstancePtr, u8 Set);
 
 void XDpTxSs_ReportCoreInfo(XDpTxSs *InstancePtr);
 void XDpTxSs_ReportLinkInfo(XDpTxSs *InstancePtr);

XilinxProcessorIPLib/drivers/dptxss/src/xdptxss_dbg.c

@@ -45,6 +45,7 @@
 * Ver  Who Date     Changes
 * ---- --- -------- --------------------------------------------------
 * 1.00 sha 01/29/15 Initial release.
+* 1.00 sha 08/07/15 Updated register offsets in debug MSA info.
 * </pre>
 *
 ******************************************************************************/
@@ -494,22 +495,22 @@ void XDpTxSs_ReportMsaInfo(XDpTxSs *InstancePtr)
 			"\tClocks, H Total      	(0x180) : %ld\n\r"
 			"\tClocks, V Total      	(0x184) : %ld\n\r"
 			"\tPolarity (V / H)     	(0x188) : %ld\n\r"
-			"\tHSync Width          	(0x180) : %ld\n\r"
+			"\tHSync Width          	(0x18C) : %ld\n\r"
-			"\tVSync Width          	(0x180) : %ld\n\r"
+			"\tVSync Width          	(0x190) : %ld\n\r"
-			"\tHorz Resolution      	(0x180) : %ld\n\r"
+			"\tHorz Resolution      	(0x194) : %ld\n\r"
-			"\tVert Resolution      	(0x180) : %ld\n\r"
+			"\tVert Resolution      	(0x198) : %ld\n\r"
-			"\tHorz Start           	(0x180) : %ld\n\r"
+			"\tHorz Start           	(0x19C) : %ld\n\r"
-			"\tVert Start           	(0x180) : %ld\n\r"
+			"\tVert Start           	(0x1A0) : %ld\n\r"
-			"\tMisc0                	(0x180) : 0x%08lX\n\r"
+			"\tMisc0                	(0x1A4) : 0x%08lX\n\r"
-			"\tMisc1                	(0x180) : 0x%08lX\n\r"
+			"\tMisc1                	(0x1A8) : 0x%08lX\n\r"
-			"\tUser Pixel Width     	(0x180) : %ld\n\r"
+			"\tUser Pixel Width     	(0x1B8) : %ld\n\r"
-			"\tM Vid                	(0x180) : %ld\n\r"
+			"\tM Vid                	(0x1AC) : %ld\n\r"
-			"\tN Vid                	(0x180) : %ld\n\r"
+			"\tN Vid                	(0x1B4) : %ld\n\r"
-			"\tTransfer Unit Size   	(0x180) : %ld\n\r"
+			"\tTransfer Unit Size   	(0x1B0) : %ld\n\r"
-			"\tUser Data Count      	(0x180) : %ld\n\r"
+			"\tUser Data Count      	(0x1BC) : %ld\n\r"
-			"\tMinimum bytes per TU 	(0x180) : %ld\n\r"
+			"\tMinimum bytes per TU 	(0x1C4) : %ld\n\r"
-			"\tFractional bytes per TU	(0x180) : %ld\n\r"
+			"\tFractional bytes per TU	(0x1C8) : %ld\n\r"
-			"\tInit wait              	(0x180) : %ld\n\r",
+			"\tInit wait              	(0x1CC) : %ld\n\r",
 		XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_MAIN_STREAM_HTOTAL),
 		XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_MAIN_STREAM_VTOTAL),
 		XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_MAIN_STREAM_POLARITY),

XilinxProcessorIPLib/drivers/dptxss/src/xdptxss_g.c

@@ -44,12 +44,9 @@
 * The configuration table for devices
 */
 
-#define XPAR_DP_TX_SUBSYSTEM_0_DP_PRESENT 	1
+#define XPAR_DP_TX_SUBSYSTEM_0_DP_PRESENT	1
-#define XPAR_DP_TX_SUBSYSTEM_0_VS_PRESENT 	1
+#define XPAR_DP_TX_SUBSYSTEM_0_DP_TX_HDCP_PRESENT	1
-#define XPAR_DP_TX_SUBSYSTEM_0_VTC1_PRESENT 	1
+#define XPAR_DP_TX_SUBSYSTEM_0_VTC1_PRESENT	1
-#define XPAR_DP_TX_SUBSYSTEM_0_VTC2_PRESENT 	1
-#define XPAR_DP_TX_SUBSYSTEM_0_VTC3_PRESENT 	1
-#define XPAR_DP_TX_SUBSYSTEM_0_VTC4_PRESENT 	1
 
 
 XDpTxSs_Config XDpTxSs_ConfigTable[] =
@@ -87,20 +84,13 @@ XDpTxSs_Config XDpTxSs_ConfigTable[] =
 			}
 		},
 		{
-			XPAR_DP_TX_SUBSYSTEM_0_VS_PRESENT,
+			XPAR_DP_TX_SUBSYSTEM_0_DP_TX_HDCP_PRESENT,
 			{
-				XPAR_DP_TX_SUBSYSTEM_0_VS_DEVICE_ID,
+				XPAR_DP_TX_SUBSYSTEM_0_DP_TX_HDCP_DEVICE_ID,
-				XPAR_DP_TX_SUBSYSTEM_0_VS_BASEADDR,
+				XPAR_DP_TX_SUBSYSTEM_0_DP_TX_HDCP_BASEADDR,
-				XPAR_DP_TX_SUBSYSTEM_0_VS_ACTIVE_COLS,
+				XPAR_DP_TX_SUBSYSTEM_0_DP_TX_HDCP_S_AXI_FREQUENCY,
-				XPAR_DP_TX_SUBSYSTEM_0_VS_ACTIVE_ROWS,
+				XPAR_DP_TX_SUBSYSTEM_0_DP_TX_HDCP_IS_RX,
-				XPAR_DP_TX_SUBSYSTEM_0_VS_MAX_SEGMENTS,
+				XPAR_DP_TX_SUBSYSTEM_0_DP_TX_HDCP_IS_HDMI
-				XPAR_DP_TX_SUBSYSTEM_0_VS_AXIS_VIDEO_MAX_TDATA_WIDTH,
-				XPAR_DP_TX_SUBSYSTEM_0_VS_AXIS_VIDEO_MAX_ITDATASMPLS_PER_CLK,
-				XPAR_DP_TX_SUBSYSTEM_0_VS_AXIS_VIDEO_MAX_OTDATASMPLS_PER_CLK,
-				XPAR_DP_TX_SUBSYSTEM_0_VS_MAX_OVRLAP,
-				XPAR_DP_TX_SUBSYSTEM_0_VS_MAX_SMPL_WIDTH,
-				XPAR_DP_TX_SUBSYSTEM_0_VS_HAS_AXI4_LITE,
-				XPAR_DP_TX_SUBSYSTEM_0_VS_HAS_IRQ
 			}
 		},
 		{
@@ -110,27 +100,6 @@ XDpTxSs_Config XDpTxSs_ConfigTable[] =
 					XPAR_DP_TX_SUBSYSTEM_0_VTC1_DEVICE_ID,
 					XPAR_DP_TX_SUBSYSTEM_0_VTC1_BASEADDR
 				}
-			},
-			{
-				XPAR_DP_TX_SUBSYSTEM_0_VTC2_PRESENT,
-				{
-					XPAR_DP_TX_SUBSYSTEM_0_VTC2_DEVICE_ID,
-					XPAR_DP_TX_SUBSYSTEM_0_VTC2_BASEADDR
-				}
-			},
-			{
-				XPAR_DP_TX_SUBSYSTEM_0_VTC3_PRESENT,
-				{
-					XPAR_DP_TX_SUBSYSTEM_0_VTC3_DEVICE_ID,
-					XPAR_DP_TX_SUBSYSTEM_0_VTC3_BASEADDR
-				}
-			},
-			{
-				XPAR_DP_TX_SUBSYSTEM_0_VTC4_PRESENT,
-				{
-					XPAR_DP_TX_SUBSYSTEM_0_VTC4_DEVICE_ID,
-					XPAR_DP_TX_SUBSYSTEM_0_VTC4_BASEADDR
-				}
 			}
 		}
 	}

XilinxProcessorIPLib/drivers/dptxss/src/xdptxss_intr.c

@@ -43,8 +43,10 @@
 * MODIFICATION HISTORY:
 *
 * Ver  Who Date     Changes
-* ---- --- -------- --------------------------------------------------
+* ---- --- -------- ---------------------------------------------------------
 * 1.00 sha 01/29/15 Initial release.
+* 1.00 sha 08/07/15 Added new handler types: lane count, link rate,
+*                   Pre-emphasis voltage swing adjust and Set MSA.
 * </pre>
 *
 ******************************************************************************/
@@ -79,7 +81,7 @@
 * The application is responsible for connecting this function to the interrupt
 * system. Application beyond this driver is also responsible for providing
 * callbacks to handle interrupts and installing the callbacks using
-* XDptxss_SetCallBack() during initialization phase.
+* XDpTxSs_SetCallBack() during initialization phase.
 *
 * @param	InstancePtr is a pointer to the XDpTxSs core instance that
 *		just interrupted.
@@ -108,10 +110,14 @@ void XDpTxSs_DpIntrHandler(void *InstancePtr)
 * HandlerType:
 *
 * <pre>
-* HandlerType                    Callback Function Type
+* HandlerType                         Callback Function Type
-* ------------------------------ ---------------------------------------------
+* ----------------------------------- -------------------------------------
-* (XDPTXSS_HANDLER_DP_HPD_EVENT) XDp_TxSetHpdEventHandler
+* (XDPTXSS_HANDLER_DP_HPD_EVENT)      XDp_TxSetHpdEventHandler
-* (XDPTXSS_HANDLER_DP_HPD_PULSE) XDp_TxSetHpdPulseHandler
+* (XDPTXSS_HANDLER_DP_HPD_PULSE)      XDp_TxSetHpdPulseHandler
+* (XDPTXSS_HANDLER_DP_LANE_COUNT_CHG) XDp_TxSetLaneCountChangeCallback
+* (XDPTXSS_HANDLER_DP_LINK_RATE_CHG)  XDp_TxSetLinkRateChangeCallback
+* (XDPTXSS_HANDLER_DP_PE_VS_ADJUST)   XDp_TxSetPeVsAdjustCallback
+* (XDPTXSS_HANDLER_DP_SET_MSA)        XDp_TxSetMsaHandler
 * </pre>
 *
 * @param	InstancePtr is a pointer to the XDpTxSs core instance.
@@ -154,6 +160,30 @@ u32 XDpTxSs_SetCallBack(XDpTxSs *InstancePtr, u32 HandlerType,
 			Status = XST_SUCCESS;
 			break;
 
+		case XDPTXSS_HANDLER_DP_LANE_COUNT_CHG:
+			XDp_TxSetLaneCountChangeCallback(InstancePtr->DpPtr,
+				CallbackFunc, CallbackRef);
+			Status = XST_SUCCESS;
+			break;
+
+		case XDPTXSS_HANDLER_DP_LINK_RATE_CHG:
+			XDp_TxSetLinkRateChangeCallback(InstancePtr->DpPtr,
+				CallbackFunc, CallbackRef);
+			Status = XST_SUCCESS;
+			break;
+
+		case XDPTXSS_HANDLER_DP_PE_VS_ADJUST:
+			XDp_TxSetPeVsAdjustCallback(InstancePtr->DpPtr,
+				CallbackFunc, CallbackRef);
+			Status = XST_SUCCESS;
+			break;
+
+		case XDPTXSS_HANDLER_DP_SET_MSA:
+			XDp_TxSetMsaHandler(InstancePtr->DpPtr, CallbackFunc,
+				CallbackRef);
+			Status = XST_SUCCESS;
+			break;
+
 		default:
 			Status = XST_INVALID_PARAM;
 			break;