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xilskey: Fixed Secure bit programming bug

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Modified if condition at programming the
secure row of ultrascale's efuse.

Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Acked-by: Harini Katakam <harinik@xilinx.com>
This commit is contained in:
VNSL Durga 2015-09-15 16:52:15 +05:30 • committed by Nava kishore Manne
parent cf3ea2ed03
commit c837085d9e
1 changed files with 2 additions and 2 deletions
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4
lib/sw_services/xilskey/src/xilskey_epl.c
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@ -1842,8 +1842,8 @@ static inline u8 XilSKey_EfusePl_ProgramBit_Ultra(u8 Row, u8 Bit, u8 Redundant,
/** /**
* If row = 10 then bits should be supported from 0 to 5 * If row = 10 then bits should be supported from 0 to 5
*/ */
if ((Row == XSK_EFUSEPL_SEC_ROW_ULTRA) &&\ if ((Row == XSK_EFUSEPL_SEC_ROW_ULTRA) &&
(Row > XSK_EFUSEPL_SEC_ROW_END_BIT_ULTRA) ) { (Bit > XSK_EFUSEPL_SEC_ROW_END_BIT_ULTRA) ) {
ErrorCode = XSK_EFUSEPL_ERROR_WRITE_BIT_OUT_OF_RANGE; ErrorCode = XSK_EFUSEPL_ERROR_WRITE_BIT_OUT_OF_RANGE;
return XST_FAILURE; return XST_FAILURE;
} }