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emacps: Remove PEEP board related code

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Remove PEEP board related code.

Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
This commit is contained in:
Punnaiah Choudary Kalluri 2015-02-02 19:45:10 +05:30 • committed by Suneel Garapati
parent 70384a8fc5
commit d10f762a49
2 changed files with 2 additions and 113 deletions
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25
XilinxProcessorIPLib/drivers/emacps/examples/xemacps_example_intr_dma.c
View file

@ -54,8 +54,6 @@
* - EmacPsResetDevice() demonstrates how to reset the driver/HW without
* loosing all configuration settings.
*
* NOTE:
* Define PEEP in xemacps_example.h to run the example on a PEEP board.
*
* <pre>
* MODIFICATION HISTORY:
@ -105,6 +103,7 @@
* TxFrameLength is now made global.
* 2.1 srt 07/11/14 Implemented 64-bit changes and modified as per
* Zynq Ultrascale Mp GEM specification
* 3.0 kpc 01/23/14 Removed PEEP board related code
*
* </pre>
*
@ -137,22 +136,11 @@
#define SLCR_GEM0_CLK_CTRL_ADDR (XPS_SYS_CTRL_BASEADDR + 0x140)
#define SLCR_GEM1_CLK_CTRL_ADDR (XPS_SYS_CTRL_BASEADDR + 0x144)
#ifdef PEEP /* Define PEEP in xemacps_example.h if the example is run on PEEP */
#define SLCR_GEM_10M_CLK_CTRL_VALUE 0x00103031
#define SLCR_GEM_100M_CLK_CTRL_VALUE 0x00103001
#define SLCR_GEM_1G_CLK_CTRL_VALUE 0x00103011
#endif
#define SLCR_LOCK_KEY_VALUE 0x767B
#define SLCR_UNLOCK_KEY_VALUE 0xDF0D
#define SLCR_ADDR_GEM_RST_CTRL (XPS_SYS_CTRL_BASEADDR + 0x214)
/* FIXME: These are constants to enable GEM0 */
#define GPIO_DATA2_REG 0xFF008048
#define GPIO_DATA2_DIR 0xFF008284
#define GPIO_GEM_MASK (3<<18)
#define GPIO_GEM_VAL_1G (1<<18)
/*************************** Variable Definitions ***************************/
@ -291,9 +279,7 @@ LONG EmacPsDmaIntrExample(XScuGic * IntcInstancePtr,
LONG Status;
XEmacPs_Config *Config;
XEmacPs_Bd BdTemplate;
#ifndef PEEP
u32 SlcrTxClkCntrl;
#endif
/*************************************/
/* Setup device for first-time usage */
@ -327,12 +313,6 @@ LONG EmacPsDmaIntrExample(XScuGic * IntcInstancePtr,
/* SLCR unlock */
*(volatile unsigned int *)(SLCR_UNLOCK_ADDR) = SLCR_UNLOCK_KEY_VALUE;
#ifdef PEEP
*(volatile unsigned int *)(SLCR_GEM0_CLK_CTRL_ADDR) =
SLCR_GEM_1G_CLK_CTRL_VALUE;
*(volatile unsigned int *)(SLCR_GEM1_CLK_CTRL_ADDR) =
SLCR_GEM_1G_CLK_CTRL_VALUE;
#else
if (EmacPsIntrId == XPS_GEM0_INT_ID) {
#ifdef XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0
/* GEM0 1G clock configuration*/
@ -356,7 +336,6 @@ LONG EmacPsDmaIntrExample(XScuGic * IntcInstancePtr,
SlcrTxClkCntrl;
#endif
}
#endif
/* SLCR lock */
*(unsigned int *)(SLCR_LOCK_ADDR) = SLCR_LOCK_KEY_VALUE;
sleep(1);
@ -479,10 +458,8 @@ LONG EmacPsDmaIntrExample(XScuGic * IntcInstancePtr,
*/
if (GemVersion == 2)
{
#ifndef PEEP /* For Zynq board */
XEmacPs_SetMdioDivisor(EmacPsInstancePtr, MDC_DIV_224);
sleep(1);
#endif
}
/*
* Set emacps to phy loopback

90
XilinxProcessorIPLib/drivers/emacps/examples/xemacps_example_util.c
View file

@ -49,6 +49,7 @@
* in xemacps_example.h.
* 1.01a asa 02/27/12 The sleep value after PHY loopback is setup is reduced
* for Zynq.
* 3.0 kpc 01/23/15 Removed PEEP board related code
* </pre>
*
*****************************************************************************/
@ -384,94 +385,6 @@ u32 XEmacPsDetectPHY(XEmacPs * EmacPsInstancePtr)
* @note None.
*
*****************************************************************************/
#ifdef PEEP /* Define PEEP in xemacps_example.h if the example is run on PEEP*/
#define PHY_REG0_RESET 0x8000
#define PHY_REG0_LOOPBACK 0x4000
#define PHY_REG0_10 0x0100
#define PHY_REG0_100 0x2100
#define PHY_REG0_1000 0x0140
#define PHY_R20_DFT_SPD_MASK 0x0070
#define PHY_R20_DFT_SPD_10 0x0040
#define PHY_R20_DFT_SPD_100 0x0050
#define PHY_R20_DFT_SPD_1000 0x0060
LONG EmacPsUtilEnterLoopback(XEmacPs * EmacPsInstancePtr, u32 Speed)
{
LONG Status;
u16 PhyReg0 = 0;
u16 PhyReg20 = 0;
u32 PhyAddr;
/* Detect the PHY address */
PhyAddr = XEmacPsDetectPHY(EmacPsInstancePtr);
if (PhyAddr >= 32) {
EmacPsUtilErrorTrap("Error detect phy");
return XST_FAILURE;
}
Status = XEmacPs_PhyRead(EmacPsInstancePtr, PhyAddr, 20, &PhyReg20);
Status |= XEmacPs_PhyRead(EmacPsInstancePtr, PhyAddr, 0, &PhyReg0);
PhyReg20 &= ~PHY_R20_DFT_SPD_MASK;
switch (Speed) {
case 10:
PhyReg20 |= PHY_R20_DFT_SPD_10;
break;
case 100:
PhyReg20 |= PHY_R20_DFT_SPD_100;
break;
case 1000:
PhyReg20 |= PHY_R20_DFT_SPD_1000;
break;
default:
EmacPsUtilErrorTrap("Error: speed not recognized ");
return XST_FAILURE;
}
Status |= XEmacPs_PhyWrite(EmacPsInstancePtr, PhyAddr, 20, PhyReg20);
Status |= XEmacPs_PhyWrite(EmacPsInstancePtr, PhyAddr, 0,
PhyReg0 | PHY_REG0_RESET);
/* setup speed and duplex */
switch (Speed) {
case 10:
PhyReg0 = PHY_REG0_10;
break;
case 100:
PhyReg0 = PHY_REG0_100;
break;
case 1000:
PhyReg0 = PHY_REG0_1000;
break;
default:
EmacPsUtilErrorTrap("Error: speed not recognized ");
return XST_FAILURE;
}
Status |= XEmacPs_PhyWrite(EmacPsInstancePtr, PhyAddr, 0, PhyReg0);
Status |= XEmacPs_PhyWrite(EmacPsInstancePtr, PhyAddr, 0,
(PhyReg0 | PHY_REG0_RESET));
/* FIXME: Sleep doesn't seem to work */
//sleep(1);
Status |= XEmacPs_PhyRead(EmacPsInstancePtr, PhyAddr, 0, &PhyReg0);
if (Status != XST_SUCCESS) {
EmacPsUtilErrorTrap("Error setup phy speed");
return XST_FAILURE;
}
/* enable loopback */
PhyReg0 |= PHY_REG0_LOOPBACK;
Status = XEmacPs_PhyWrite(EmacPsInstancePtr, PhyAddr, 0, PhyReg0);
if (Status != XST_SUCCESS) {
EmacPsUtilErrorTrap("Error setup phy loopback");
return XST_FAILURE;
}
return XST_SUCCESS;
}
#else /*For Zynq board*/
#define PHY_REG0_RESET 0x8000
#define PHY_REG0_LOOPBACK 0x4000
#define PHY_REG0_10 0x0100
@ -590,7 +503,6 @@ LONG EmacPsUtilEnterLoopback(XEmacPs * EmacPsInstancePtr, u32 Speed)
return XST_SUCCESS;
}
#endif /*PEEP*/
/****************************************************************************/
/**