dptx: Update examples.
Testing with the new IP configuration parameter (payload data width) required some changes to the examples. Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
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5 changed files with 118 additions and 52 deletions
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@ -271,6 +271,14 @@ static void Dptx_StartVideoStream(XDptx *InstancePtr)
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/* Set the bits per color. If not set, the default is 6. */
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XDptx_CfgMsaSetBpc(InstancePtr, XDPTX_STREAM_ID1, 8);
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/* Set synchronous clock mode. */
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XDptx_CfgMsaEnSynchClkMode(InstancePtr, XDPTX_STREAM_ID1, 1);
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XDptx_ClearMsaValues(InstancePtr, XDPTX_STREAM_ID1);
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XDptx_ClearMsaValues(InstancePtr, XDPTX_STREAM_ID2);
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XDptx_ClearMsaValues(InstancePtr, XDPTX_STREAM_ID3);
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XDptx_ClearMsaValues(InstancePtr, XDPTX_STREAM_ID4);
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/* Choose a method for selecting the video mode. There are 3 ways to do this:
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* 1) Use the preferred timing from the monitor's EDID:
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* u8 Edid[XDPTX_EDID_SIZE];
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@ -38,9 +38,8 @@
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* (MST) mode.
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*
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* @note When topology discovery is enabled, the required stack size will
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* be larger than the default that SDK sets of 0x400. Increase the
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* stack size if the ALLOCATE_FROM_SINKLIST option is used. Testing
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* was done with a stack size of 0x1000.
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* be larger than the default that SDK sets. Increase the stack
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* size if the ALLOCATE_FROM_SINKLIST option is used.
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* @note For this example to display output, the user will need to
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* implement initialization of the system (Dptx_PlatformInit) and,
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* after training is complete, implement configuration of the video
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@ -49,6 +48,8 @@
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* @note The functions Dptx_PlatformInit and Dptx_StreamSrc* are declared
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* extern in xdptx_example_common.h and are left up to the user to
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* implement.
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* @note Some setups require introduction of delays when sending sideband
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* messages.
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*
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* <pre>
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* MODIFICATION HISTORY:
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@ -94,6 +95,7 @@
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/**************************** Function Prototypes *****************************/
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u32 Dptx_MstExample(XDptx *InstancePtr, u16 DeviceId);
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u32 Dptx_MstExampleRun(XDptx *InstancePtr);
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/**************************** Function Definitions ****************************/
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@ -141,21 +143,6 @@ int main(void)
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u32 Dptx_MstExample(XDptx *InstancePtr, u16 DeviceId)
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{
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u32 Status;
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u32 MaskVal;
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u8 StreamIndex;
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XDptx_VideoMode VideoMode = USE_VIDEO_MODE;
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u8 Bpc = USE_BPC;
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/* Enable multi-stream transport (MST) mode for this example. */
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XDptx_MstCfgModeEnable(InstancePtr);
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for (StreamIndex = 0; StreamIndex < NUM_STREAMS; StreamIndex++) {
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XDptx_MstCfgStreamEnable(InstancePtr, XDPTX_STREAM_ID1 +
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StreamIndex);
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}
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for (StreamIndex = NUM_STREAMS; StreamIndex < 4; StreamIndex++) {
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XDptx_MstCfgStreamDisable(InstancePtr, XDPTX_STREAM_ID1 +
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StreamIndex);
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}
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/* Do platform initialization here. This is hardware system specific -
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* it is up to the user to implement this function. */
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@ -180,20 +167,93 @@ u32 Dptx_MstExample(XDptx *InstancePtr, u16 DeviceId)
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return XST_FAILURE;
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}
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do {
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Status = Dptx_MstExampleRun(InstancePtr);
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if (Status == XST_ERROR_COUNT_MAX) {
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xil_printf("ACT trigger lost... Need to re-train.\n");
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}
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} while (Status != XST_SUCCESS);
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/* Do not return. */
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xil_printf("MST example DONE.\n");
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while (1);
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return XST_SUCCESS;
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}
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/******************************************************************************/
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/**
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* This function trains the link and allocates stream payloads.
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*
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* @param InstancePtr is a pointer to the XDptx instance.
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* @param DeviceId is the unique device ID of the DisplayPort TX core
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* instance.
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*
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* @return
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* - XST_SUCCESS if MST allocation was successful.
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* - XST_ERROR_COUNT_MAX if the ACT trigger was lost.
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* - XST_FAILURE otherwise.
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*
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* @note None.
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*
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*******************************************************************************/
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u32 Dptx_MstExampleRun(XDptx *InstancePtr)
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{
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u32 Status;
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u32 MaskVal;
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u8 StreamIndex;
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XDptx_VideoMode VideoMode = USE_VIDEO_MODE;
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u8 Bpc = USE_BPC;
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u8 NumStreams = NUM_STREAMS;
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XDptx_EnableTrainAdaptive(InstancePtr, TRAIN_ADAPTIVE);
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XDptx_SetHasRedriverInPath(InstancePtr, TRAIN_HAS_REDRIVER);
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XDptx_SetHasRedriverInPath(InstancePtr, TRAIN_HAS_REDRIVER);
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InstancePtr->AuxDelayUs = 0;
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InstancePtr->SbMsgDelayUs = 0;
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/* A DisplayPort connection must exist at this point. See the interrupt
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* and polling examples for waiting for connection events. */
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Status = Dptx_StartLink(InstancePtr);
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if (Status != XST_SUCCESS) {
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xil_printf("Link Training failed.\n");
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return XST_FAILURE;
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}
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XDptx_CfgMsaSetBpc(InstancePtr, XDPTX_STREAM_ID1, Bpc);
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XDptx_CfgMsaSetBpc(InstancePtr, XDPTX_STREAM_ID2, Bpc);
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XDptx_CfgMsaSetBpc(InstancePtr, XDPTX_STREAM_ID3, Bpc);
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XDptx_CfgMsaSetBpc(InstancePtr, XDPTX_STREAM_ID4, Bpc);
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/* If required, add delays in MST mode. */
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InstancePtr->AuxDelayUs = 30000;
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InstancePtr->SbMsgDelayUs = 100000;
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XDptx_ClearMsaValues(InstancePtr, XDPTX_STREAM_ID1);
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XDptx_ClearMsaValues(InstancePtr, XDPTX_STREAM_ID2);
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XDptx_ClearMsaValues(InstancePtr, XDPTX_STREAM_ID3);
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XDptx_ClearMsaValues(InstancePtr, XDPTX_STREAM_ID4);
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#ifdef ALLOCATE_FROM_SINKLIST
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xil_printf("Find topology >>>\n");
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InstancePtr->Topology.NodeTotal = 0;
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InstancePtr->Topology.SinkTotal = 0;
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XDptx_FindAccessibleDpDevices(InstancePtr, 1, NULL);
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xil_printf("<<< Find topology DONE; # of sinks found = %d.\n",
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InstancePtr->Topology.SinkTotal);
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if (NumStreams > InstancePtr->Topology.SinkTotal) {
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NumStreams = InstancePtr->Topology.SinkTotal;
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}
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#endif
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/* Enable multi-stream transport (MST) mode for this example. */
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XDptx_MstCfgModeEnable(InstancePtr);
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for (StreamIndex = 0; StreamIndex < NumStreams; StreamIndex++) {
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XDptx_MstCfgStreamEnable(InstancePtr, XDPTX_STREAM_ID1 +
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StreamIndex);
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}
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for (StreamIndex = NumStreams; StreamIndex < 4; StreamIndex++) {
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XDptx_MstCfgStreamDisable(InstancePtr, XDPTX_STREAM_ID1 +
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StreamIndex);
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}
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#ifndef ALLOCATE_FROM_SINKLIST
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u8 Lct;
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@ -217,26 +277,19 @@ u32 Dptx_MstExample(XDptx *InstancePtr, u16 DeviceId)
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}
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#else
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xil_printf("Find topology >>>\n");
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InstancePtr->Topology.NodeTotal = 0;
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InstancePtr->Topology.SinkTotal = 0;
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XDptx_FindAccessibleDpDevices(InstancePtr, 1, NULL);
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xil_printf("<<< Find topology DONE.\n");
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if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID1)) {
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XDptx_SetStreamSelectFromSinkList(InstancePtr, XDPTX_STREAM_ID1,
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STREAM1_USE_SINKNUM);
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}
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if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID1)) {
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if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID2)) {
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XDptx_SetStreamSelectFromSinkList(InstancePtr, XDPTX_STREAM_ID2,
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STREAM2_USE_SINKNUM);
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}
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if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID1)) {
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if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID3)) {
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XDptx_SetStreamSelectFromSinkList(InstancePtr, XDPTX_STREAM_ID3,
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STREAM3_USE_SINKNUM);
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}
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if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID1)) {
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if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID4)) {
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XDptx_SetStreamSelectFromSinkList(InstancePtr, XDPTX_STREAM_ID4,
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STREAM4_USE_SINKNUM);
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}
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@ -248,6 +301,11 @@ u32 Dptx_MstExample(XDptx *InstancePtr, u16 DeviceId)
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for (StreamIndex = 0; StreamIndex < 4; StreamIndex++) {
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if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID1 +
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StreamIndex)) {
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XDptx_CfgMsaSetBpc(InstancePtr, XDPTX_STREAM_ID1 +
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StreamIndex, Bpc);
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XDptx_CfgMsaEnSynchClkMode(InstancePtr,
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XDPTX_STREAM_ID1 + StreamIndex, 1);
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XDptx_CfgMsaUseStandardVideoMode(InstancePtr,
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XDPTX_STREAM_ID1 + StreamIndex, VideoMode);
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}
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@ -283,24 +341,29 @@ u32 Dptx_MstExample(XDptx *InstancePtr, u16 DeviceId)
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XDPTX_SOFT_RESET_VIDEO_STREAM_ALL_MASK);
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XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_SOFT_RESET, 0x0);
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/* Sync the stream source to the DisplayPort TX if needed. */
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Dptx_StreamSrcSync(InstancePtr);
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////////////////////////////////////
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/* Mask interrupts while allocating payloads. */
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MaskVal = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
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XDPTX_INTERRUPT_MASK);
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XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_INTERRUPT_MASK,
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0x3F);
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/* Allocate payloads. */
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XDptx_MstEnable(InstancePtr);
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XDptx_AllocatePayloadStreams(InstancePtr);
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/* Reset the transmitter. */
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XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_SOFT_RESET,
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XDPTX_SOFT_RESET_VIDEO_STREAM_ALL_MASK);
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XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_SOFT_RESET, 0x0);
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/* Clear the payload ID table first. */
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Status = XDptx_ClearPayloadVcIdTable(InstancePtr);
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if (Status != XST_SUCCESS) {
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return Status;
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}
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/* Sync the stream source to the DisplayPort TX if needed. */
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Dptx_StreamSrcSync(InstancePtr);
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////////////////////////////////////
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/* Allocate payloads. */
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Status = XDptx_AllocatePayloadStreams(InstancePtr);
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if (Status != XST_SUCCESS) {
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return Status;
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}
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/* Enable the main link. */
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XDptx_EnableMainLink(InstancePtr);
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XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_INTERRUPT_MASK,
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MaskVal);
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/* Do not return. */
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while (1);
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return XST_SUCCESS;
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}
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@ -186,6 +186,9 @@
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* investigated for the next SDK release.
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* - The driver does not handle audio. See the audio example in the driver
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* examples directory for the required sequence for enabling audio.
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* - Limited testing was done with 4-byte GT data width.
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* - Most testing was done on a KC705 board. Some testing was done on a ZC706
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* board, mostly with a 2-byte GT data width configuration.
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*
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* @note For a 5.4Gbps link rate, a high performance 7 series FPGA is
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* required with a speed grade of -2 or -3.
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@ -682,12 +682,6 @@ u32 XDptx_AllocatePayloadStreams(XDptx *InstancePtr)
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Xil_AssertNonvoid(InstancePtr != NULL);
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Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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/* Clear the payload ID table first. */
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Status = XDptx_ClearPayloadVcIdTable(InstancePtr);
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if (Status != XST_SUCCESS) {
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return Status;
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}
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/* Allocate the payload table for each stream in both the DisplayPort TX
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* and RX device. */
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for (StreamIndex = 0; StreamIndex < 4; StreamIndex++) {
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@ -914,6 +908,8 @@ u32 XDptx_ClearPayloadVcIdTable(XDptx *InstancePtr)
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}
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} while ((AuxData[0] & 0x01) != 0x01);
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XDptx_WaitUs(InstancePtr, 1000);
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Status = XDptx_SendActTrigger(InstancePtr);
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if (Status != XST_SUCCESS) {
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return Status;
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@ -53,7 +53,6 @@
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/******************************* Include Files ********************************/
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#include "math.h"
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#include "xdptx.h"
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#include "xdptx_hw.h"
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#include "xstatus.h"
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