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nandpsu: Fix timeout error for erase operation on slower devices

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The current timeout value is not enough for erase operation on slower
devices. so increasing the timeout value and also added usleep for
timeout routine to have a precise timeout.

Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
This commit is contained in:
Punnaiah Choudary Kalluri 2015-06-18 11:50:14 +05:30 • committed by Nava kishore Manne
parent 29f2ea0237
commit d29f063136
2 changed files with 5 additions and 1 deletions
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2
XilinxProcessorIPLib/drivers/nandpsu/src/xnandpsu.c
View file

@ -97,6 +97,7 @@
* SDR and NVDDR interface for timing modes 0 to 5.
* Modified Bbt Signature and Version Offset value for
* Oob and No-Oob region.
* 1.0 kpc 17/6/2015 Added timer based timeout intsead of sw counter.
* </pre>
*
******************************************************************************/
@ -897,6 +898,7 @@ static s32 XNandPsu_PollRegTimeout(XNandPsu *InstancePtr, u32 RegOffset,
break;
}
TimeoutVar--;
usleep(1);
}
if (TimeoutVar <= 0U) {

4
XilinxProcessorIPLib/drivers/nandpsu/src/xnandpsu.h
View file

@ -155,6 +155,8 @@
* SDR and NVDDR interface for timing modes 0 to 5.
* Modified Bbt Signature and Version Offset value for
* Oob and No-Oob region.
* 1.0 kpc 17/06/2015 Increased the timeout for complete event to avoid
* timeout errors for erase operation on slower devices.
* </pre>
*
******************************************************************************/
@ -200,7 +202,7 @@ extern "C" {
#define XNANDPSU_MAX_SPARE_SIZE 0x800U /**< Max spare bytes of a NAND
flash page of 16K */
#define XNANDPSU_INTR_POLL_TIMEOUT 10000U
#define XNANDPSU_INTR_POLL_TIMEOUT 0xF000000U
#define XNANDPSU_SDR_CLK ((u16)100U * (u16)1000U * (u16)1000U)
#define XNANDPSU_NVDDR_CLK_0 ((u16)20U * (u16)1000U * (u16)1000U)