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gpiops: Used Pin number in bank instead of pin number passed to APIs and changed the mask value.

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This patch uses pin number in bank rather than pin number passed to APIs and changed the mask value.

Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
This commit is contained in:
P L Sai Krishna 2014-10-14 15:45:09 +05:30 • committed by Suneel Garapati
parent 9cf8155cf6
commit da1be543e2
2 changed files with 14 additions and 10 deletions
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2
XilinxProcessorIPLib/drivers/gpiops/src/xgpiops.h
View file

@ -90,6 +90,8 @@
* for output pins on all banks during initialization.
* 1.02a hk 08/22/13 Added low level reset API
* 2.1 hk 04/29/14 Use Input data register DATA_RO for read. CR# 771667.
* 2.2 sk 10/13/14 Used Pin number in Bank instead of pin number
* passed to APIs. CR# 822636
*
* </pre>
*

22
XilinxProcessorIPLib/drivers/gpiops/src/xgpiops_intr.c
View file

@ -42,6 +42,8 @@
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a sv 01/18/10 First Release
* 2.2 sk 10/13/14 Used Pin number in Bank instead of pin number
* passed to API's. CR# 822636
* </pre>
*
******************************************************************************/
@ -257,7 +259,7 @@ int XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, int Pin)
((Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTMASK_OFFSET);
return (IntrReg & (1 << Pin)) ? TRUE : FALSE;
return (IntrReg & (1 << PinNumber)) ? FALSE : TRUE;
}
/****************************************************************************/
@ -321,7 +323,7 @@ int XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, int Pin)
((Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTSTS_OFFSET);
return (IntrReg & (1 << Pin)) ? TRUE : FALSE;
return (IntrReg & (1 << PinNumber)) ? TRUE : FALSE;
}
/****************************************************************************/
@ -390,7 +392,7 @@ void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, int Pin)
((Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTSTS_OFFSET);
IntrReg &= (1 << Pin);
IntrReg &= (1 << PinNumber);
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTSTS_OFFSET, IntrReg);
@ -608,26 +610,26 @@ u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, int Pin)
IntrType = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTTYPE_OFFSET) & PinNumber;
XGPIOPS_INTTYPE_OFFSET) & (1 << PinNumber);
IntrPol = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTPOL_OFFSET) & PinNumber;
XGPIOPS_INTPOL_OFFSET) & (1 << PinNumber);
IntrOnAny = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTANY_OFFSET) & PinNumber;
XGPIOPS_INTANY_OFFSET) & (1 << PinNumber);
if (IntrType == 1) {
if (IntrOnAny == 1) {
if (IntrType == (1 << PinNumber)) {
if (IntrOnAny == (1 << PinNumber)) {
IrqType = XGPIOPS_IRQ_TYPE_EDGE_BOTH;
} else if (IntrPol == 1) {
} else if (IntrPol == (1 << PinNumber)) {
IrqType = XGPIOPS_IRQ_TYPE_EDGE_RISING;
} else {
IrqType = XGPIOPS_IRQ_TYPE_EDGE_FALLING;
}
} else {
if (IntrPol == 1) {
if (IntrPol == (1 << PinNumber)) {
IrqType = XGPIOPS_IRQ_TYPE_LEVEL_HIGH;
} else {
IrqType = XGPIOPS_IRQ_TYPE_LEVEL_LOW;