qspipsu_v1_1: Modified the code according to Misrac 2012.
This patch modifies the code according to Misrac 2012. Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
This commit is contained in:
P L Sai Krishna
Nava kishore Manne
parent
1dd455366e
commit
dcf79611f8
3 changed files with 35 additions and 35 deletions
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@ -144,6 +144,7 @@ s32 XQspiPsu_CfgInitialize(XQspiPsu *InstancePtr, XQspiPsu_Config *ConfigPtr,
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InstancePtr->GenFifoCS = XQSPIPSU_GENFIFO_CS_LOWER;
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InstancePtr->GenFifoBus = XQSPIPSU_GENFIFO_BUS_LOWER;
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InstancePtr->IsUnaligned = 0;
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InstancePtr->IsManualstart = TRUE;
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/* Select QSPIPSU */
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XQspiPsu_Select(InstancePtr);
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@ -340,11 +341,11 @@ s32 XQspiPsu_PolledTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
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u32 StatusReg;
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u32 ConfigReg;
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s32 Index;
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u8 IsManualStart;
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u32 QspiPsuStatusReg, DmaStatusReg;
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u32 BaseAddress;
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s32 Status;
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s32 RxThr;
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u32 IOPending = (u32)FALSE;
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Xil_AssertNonvoid(InstancePtr != NULL);
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Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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@ -373,9 +374,6 @@ s32 XQspiPsu_PolledTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
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BaseAddress = InstancePtr->Config.BaseAddress;
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/* Start if manual start */
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IsManualStart = XQspiPsu_IsManualStart(InstancePtr);
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/* Enable */
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XQspiPsu_Enable(InstancePtr);
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@ -383,12 +381,11 @@ s32 XQspiPsu_PolledTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
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XQspiPsu_GenFifoEntryCSAssert(InstancePtr);
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/* list */
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for (Index = 0; Index < (s32)NumMsg; Index++) {
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GENFIFO:
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Index = 0;
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while (Index < (s32)NumMsg) {
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XQspiPsu_GenFifoEntryData(InstancePtr, Msg, Index);
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if (IsManualStart == TRUE) {
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if (InstancePtr->IsManualstart == TRUE) {
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XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_CFG_OFFSET,
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XQspiPsu_ReadReg(BaseAddress,
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XQSPIPSU_CFG_OFFSET) |
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@ -432,7 +429,8 @@ GENFIFO:
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Msg[Index].RxBfrPtr += (InstancePtr->RxBytes -
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(InstancePtr->RxBytes % 4));
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InstancePtr->IsUnaligned = 1;
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goto GENFIFO;
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IOPending = (u32)TRUE;
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break;
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}
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InstancePtr->RxBytes = 0;
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}
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@ -460,7 +458,7 @@ GENFIFO:
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((QspiPsuStatusReg & XQSPIPSU_ISR_TXEMPTY_MASK) == FALSE) ||
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(InstancePtr->RxBytes != 0));
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if(InstancePtr->IsUnaligned != 0) {
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if((InstancePtr->IsUnaligned != 0) && (IOPending == (u32)FALSE)) {
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InstancePtr->IsUnaligned = 0;
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XQspiPsu_WriteReg(BaseAddress,
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XQSPIPSU_CFG_OFFSET, (XQspiPsu_ReadReg(
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@ -469,12 +467,18 @@ GENFIFO:
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XQSPIPSU_CFG_MODE_EN_DMA_MASK));
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InstancePtr->ReadMode = XQSPIPSU_READMODE_DMA;
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}
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if (IOPending == (u32)TRUE) {
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IOPending = (u32)FALSE;
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} else {
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Index++;
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}
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}
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/* De-select slave */
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XQspiPsu_GenFifoEntryCSDeAssert(InstancePtr);
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if (IsManualStart == TRUE) {
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if (InstancePtr->IsManualstart == TRUE) {
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XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_CFG_OFFSET,
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XQspiPsu_ReadReg(BaseAddress, XQSPIPSU_CFG_OFFSET) |
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XQSPIPSU_CFG_START_GEN_FIFO_MASK);
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@ -520,7 +524,6 @@ s32 XQspiPsu_InterruptTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
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u32 StatusReg;
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u32 ConfigReg;
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s32 Index;
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u8 IsManualStart;
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u32 BaseAddress;
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s32 Status;
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@ -551,9 +554,6 @@ s32 XQspiPsu_InterruptTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
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BaseAddress = InstancePtr->Config.BaseAddress;
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/* Start if manual start */
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IsManualStart = XQspiPsu_IsManualStart(InstancePtr);
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InstancePtr->Msg = Msg;
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InstancePtr->NumMsg = (s32)NumMsg;
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InstancePtr->MsgCnt = 0;
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@ -568,7 +568,7 @@ s32 XQspiPsu_InterruptTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
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/* Put first message in FIFO along with the above slave select */
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XQspiPsu_GenFifoEntryData(InstancePtr, Msg, 0);
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if (IsManualStart == TRUE) {
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if (InstancePtr->IsManualstart == TRUE) {
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XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_CFG_OFFSET,
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XQspiPsu_ReadReg(BaseAddress, XQSPIPSU_CFG_OFFSET) |
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XQSPIPSU_CFG_START_GEN_FIFO_MASK);
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@ -604,7 +604,6 @@ s32 XQspiPsu_InterruptTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
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******************************************************************************/
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s32 XQspiPsu_InterruptHandler(XQspiPsu *InstancePtr)
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{
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u8 IsManualStart;
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u32 QspiPsuStatusReg, DmaIntrStatusReg = 0;
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u32 BaseAddress;
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XQspiPsu_Msg *Msg;
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@ -622,9 +621,6 @@ s32 XQspiPsu_InterruptHandler(XQspiPsu *InstancePtr)
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NumMsg = InstancePtr->NumMsg;
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MsgCnt = InstancePtr->MsgCnt;
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/* Start if manual start */
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IsManualStart = XQspiPsu_IsManualStart(InstancePtr);
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/* QSPIPSU Intr cleared on read */
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QspiPsuStatusReg = XQspiPsu_ReadReg(BaseAddress, XQSPIPSU_ISR_OFFSET);
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if (InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA) {
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@ -679,7 +675,7 @@ s32 XQspiPsu_InterruptHandler(XQspiPsu *InstancePtr)
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InstancePtr->IsUnaligned = 1;
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XQspiPsu_GenFifoEntryData(InstancePtr, Msg,
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MsgCnt);
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if(IsManualStart == TRUE) {
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if(InstancePtr->IsManualstart == TRUE) {
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XQspiPsu_WriteReg(BaseAddress,
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XQSPIPSU_CFG_OFFSET,
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XQspiPsu_ReadReg(BaseAddress,
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@ -752,7 +748,7 @@ s32 XQspiPsu_InterruptHandler(XQspiPsu *InstancePtr)
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/* This might not work if not manual start */
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XQspiPsu_GenFifoEntryData(InstancePtr, Msg, MsgCnt);
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if (IsManualStart == TRUE) {
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if (InstancePtr->IsManualstart == TRUE) {
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XQspiPsu_WriteReg(BaseAddress,
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XQSPIPSU_CFG_OFFSET,
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XQspiPsu_ReadReg(BaseAddress,
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@ -767,7 +763,7 @@ s32 XQspiPsu_InterruptHandler(XQspiPsu *InstancePtr)
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/* De-select slave */
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XQspiPsu_GenFifoEntryCSDeAssert(InstancePtr);
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if (IsManualStart == TRUE) {
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if (InstancePtr->IsManualstart == TRUE) {
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XQspiPsu_WriteReg(BaseAddress,
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XQSPIPSU_CFG_OFFSET,
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XQspiPsu_ReadReg(BaseAddress,
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@ -1011,7 +1007,7 @@ static inline void XQspiPsu_FillTxFifo(XQspiPsu *InstancePtr,
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Xil_AssertVoid(Msg->TxBfrPtr != NULL);
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while ((InstancePtr->TxBytes > 0) && (Count < Size)) {
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Data = *((u32*)(Msg->TxBfrPtr));
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Data = *((u32 *)((void *)(Msg->TxBfrPtr)));
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XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
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XQSPIPSU_TXD_OFFSET, Data);
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Msg->TxBfrPtr += 4;
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@ -1245,19 +1241,16 @@ static inline void XQspiPsu_ReadRxFifo(XQspiPsu *InstancePtr,
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Data = XQspiPsu_ReadReg(InstancePtr->
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Config.BaseAddress, XQSPIPSU_RXD_OFFSET);
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if (InstancePtr->RxBytes >= 4) {
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*(u32 *)Msg->RxBfrPtr = Data;
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(void)memcpy(Msg->RxBfrPtr, &Data, 4);
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InstancePtr->RxBytes -= 4;
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Msg->RxBfrPtr += 4;
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Count += 4;
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} else {
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/* Read unaligned bytes (< 4 bytes) */
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while (InstancePtr->RxBytes != 0) {
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*Msg->RxBfrPtr = (u8)Data;
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InstancePtr->RxBytes--;
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Msg->RxBfrPtr += 1;
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Count++;
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Data >>= (u32)8;
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}
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(void)memcpy(Msg->RxBfrPtr, &Data, InstancePtr->RxBytes);
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Msg->RxBfrPtr += InstancePtr->RxBytes;
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Count += InstancePtr->RxBytes;
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InstancePtr->RxBytes = 0;
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}
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}
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}
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@ -127,7 +127,7 @@ extern "C" {
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* requested if the status event indicates an error.
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*/
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typedef void (*XQspiPsu_StatusHandler) (void *CallBackRef, u32 StatusEvent,
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unsigned ByteCount);
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u32 ByteCount);
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/**
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* This typedef contains configuration information for a flash message.
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@ -173,6 +173,7 @@ typedef struct {
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s32 NumMsg;
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s32 MsgCnt;
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s32 IsUnaligned;
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u8 IsManualstart;
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XQspiPsu_Msg *Msg;
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XQspiPsu_StatusHandler StatusHandler;
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void *StatusRef; /**< Callback reference for status handler */
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@ -229,8 +230,6 @@ typedef struct {
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#define XQspiPsu_Disable(InstancePtr) XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + XQSPIPSU_EN_OFFSET, 0x0U)
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#define XQspiPsu_IsManualStart(InstancePtr) (((XQspiPsu_GetOptions(InstancePtr) & XQSPIPSU_MANUAL_START_OPTION) != FALSE) ? TRUE : FALSE)
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/************************** Function Prototypes ******************************/
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/* Initialization and reset */
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@ -144,6 +144,10 @@ s32 XQspiPsu_SetOptions(XQspiPsu *InstancePtr, u32 Options)
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XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET,
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ConfigReg);
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if ((Options & XQSPIPSU_MANUAL_START_OPTION) != FALSE) {
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InstancePtr->IsManualstart = TRUE;
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}
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Status = XST_SUCCESS;
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}
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@ -212,6 +216,10 @@ s32 XQspiPsu_ClearOptions(XQspiPsu *InstancePtr, u32 Options)
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XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET,
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ConfigReg);
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if ((Options & XQSPIPSU_MANUAL_START_OPTION) != FALSE) {
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InstancePtr->IsManualstart = FALSE;
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}
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Status = XST_SUCCESS;
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}
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