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BSP: modified iccarm makefile

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this patch modifies makefile of cortexa9/iccarm for proper linking of object file

Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This commit is contained in:
Kinjal Pravinbhai Patel 2014-08-21 14:40:24 +05:30 • committed by Jagannadha Sutradharudu Teki
parent 297266c370
commit df0b3b1a00
5 changed files with 9 additions and 11 deletions
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4
lib/bsp/standalone/src/changelog.txt
View file

@ -199,5 +199,7 @@
* cortexa9/smc.h
* 4.2 bss 08/11/14 Added microblaze_flush_cache_ext_range and microblaze_invalidate_
* cache_ext_range declarations in mb_interface.h CR#783821.
* Modified profile_mcount_mb.S to fix CR#808412.
* Modified profile_mcount_mb.S to fix CR#808412.
* 4.2 pkp 08/21/14 modified makefile of iccarm for proper linking of objectfiles in
* cortexa9/iccarm to fix CR#816701
******************************************************************************************/

2
lib/bsp/standalone/src/cortexa9/iccarm/Makefile
View file

@ -74,7 +74,7 @@ banner:
echo "${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<"
standalone_libs: ${OBJECTS}
$(ARCHIVER) --create ${RELEASEDIR}/${LIB} ${OBJECTS}
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
.PHONY: include
include: standalone_includes

2
lib/bsp/standalone/src/cortexa9/xil_cache.c
View file

@ -355,7 +355,7 @@ void Xil_DCacheInvalidateRange(unsigned int adr, unsigned len)
XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (tempadr));
#elif defined (__ICCARM__)
__asm volatile ("mcr " \
XREG_CP15_INVAL_DC_LINE_MVA_POU :: "r" (tempadr));
XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (tempadr));
#else
{ volatile register unsigned int Reg
__asm(XREG_CP15_INVAL_DC_LINE_MVA_POC);

4
lib/bsp/standalone/src/cortexa9/xil_exception.c
View file

@ -204,7 +204,7 @@ void Xil_DataAbortHandler(void *CallBackRef){
#ifdef __GNUC__
FaultStatus = mfcp(XREG_CP15_DATA_FAULT_STATUS);
#elif defined (__ICCARM__)
mfcp(XREG_CP15_DATA_FAULT_STATUS,FaultStatus);
#else
{ volatile register unsigned int Reg __asm(XREG_CP15_DATA_FAULT_STATUS);
FaultStatus = Reg; }
@ -231,7 +231,7 @@ void Xil_PrefetchAbortHandler(void *CallBackRef){
#ifdef __GNUC__
FaultStatus = mfcp(XREG_CP15_INST_FAULT_STATUS);
#elif defined (__ICCARM__)
mfcp(XREG_CP15_INST_FAULT_STATUS,FaultStatus);
#else
{ volatile register unsigned int Reg __asm(XREG_CP15_INST_FAULT_STATUS);
FaultStatus = Reg; }

8
lib/bsp/standalone/src/cortexa9/xil_exception.h
View file

@ -108,9 +108,7 @@ typedef void (*Xil_InterruptHandler)(void *data);
mtcpsr(mfcpsr() & ~ (Mask & XIL_EXCEPTION_ALL))
#elif defined (__ICCARM__)
#define Xil_ExceptionEnableMask(Mask) \
{ register unsigned int rval; \
mfcpsr(rval); \
mtcpsr(rval & ~ (Mask & XIL_EXCEPTION_ALL)) ;}
mtcpsr(mfcpsr() & ~ (Mask & XIL_EXCEPTION_ALL))
#else
#define Xil_ExceptionEnableMask(Mask) \
{ register unsigned int Reg __asm("cpsr"); \
@ -146,9 +144,7 @@ typedef void (*Xil_InterruptHandler)(void *data);
mtcpsr(mfcpsr() | (Mask & XIL_EXCEPTION_ALL))
#elif defined (__ICCARM__)
#define Xil_ExceptionDisableMask(Mask) \
{ register unsigned int rval; \
mfcpsr(rval); \
mtcpsr(rval | (Mask & XIL_EXCEPTION_ALL)) ;}
mtcpsr(mfcpsr() | (Mask & XIL_EXCEPTION_ALL))
#else
#define Xil_ExceptionDisableMask(Mask) \
{ register unsigned int Reg __asm("cpsr"); \