sw_apps:zynqmp_fsbl: Added watchdog support
This patch adds System Watchdog Timer support Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com> Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
This commit is contained in:
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4ceb19f1ae
commit
dff2a597f9
8 changed files with 79 additions and 9 deletions
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@ -123,6 +123,7 @@ extern "C" {
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* - FSBL_BS_EXCLUDE PL bitstream code will be excluded
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* - FSBL_SHA2_EXCLUDE SHA2 code will be excluded
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* - FSBL_EARLY_HANDOFF_EXCLUDE Early handoff related code will be excluded
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* - FSBL_WDT_EXCLUDE WDT code will be excluded
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*/
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#define FSBL_NAND_EXCLUDE_VAL (0U)
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#define FSBL_QSPI_EXCLUDE_VAL (0U)
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@ -132,6 +133,7 @@ extern "C" {
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#define FSBL_BS_EXCLUDE_VAL (0U)
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#define FSBL_SHA2_EXCLUDE_VAL (1U)
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#define FSBL_EARLY_HANDOFF_EXCLUDE_VAL (0U)
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#define FSBL_WDT_EXCLUDE_VAL (0U)
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#if FSBL_NAND_EXCLUDE_VAL
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#define FSBL_NAND_EXCLUDE
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@ -165,6 +167,9 @@ extern "C" {
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#define FSBL_EARLY_HANDOFF_EXCLUDE
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#endif
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#if FSBL_WDT_EXCLUDE_VAL
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#define FSBL_WDT_EXCLUDE
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#endif
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/************************** Function Prototypes ******************************/
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@ -538,6 +538,11 @@ END:
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void XFsbl_HandoffExit(u64 HandoffAddress, u32 Flags)
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{
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#ifdef XFSBL_WDT_PRESENT
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/* Stop WDT as we are exiting FSBL */
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XFsbl_StopWdt();
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#endif
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/**
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* Flush the L1 data cache and L2 cache, Disable Data Cache
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*/
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@ -237,6 +237,10 @@ extern "C" {
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#define CRL_APB_PCAP_CTRL_DIVISOR0_MASK 0X00003F00U
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#define CRL_APB_PCAP_CTRL_CLKACT_MASK 0X01000000U
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/* Register: CRL_APB_RESET_REASON */
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#define CRL_APB_RESET_REASON ( ( CRL_APB_BASEADDR ) + 0X00000220U )
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#define CRL_APB_RESET_REASON_PMU_SYS_RESET_MASK 0X00000004U
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/* apu */
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/**
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@ -342,6 +346,21 @@ extern "C" {
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#define PMU_GLOBAL_PWR_STATE_ACPU1_MASK 0X00000002U
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#define PMU_GLOBAL_PWR_STATE_ACPU0_MASK 0X00000001U
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/* Register: PMU_GLOBAL_ERROR_STATUS_1 */
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#define PMU_GLOBAL_ERROR_STATUS_1 ( ( PMU_GLOBAL_BASEADDR ) + 0X00000530U )
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#define PMU_GLOBAL_ERROR_STATUS_1_LPD_SWDT_MASK 0X00001000U
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/* Register: PMU_GLOBAL_ERROR_SRST_EN_1 */
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#define PMU_GLOBAL_ERROR_SRST_EN_1 ( ( PMU_GLOBAL_BASEADDR ) + 0X0000056CU )
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#define PMU_GLOBAL_ERROR_SRST_EN_1_LPD_SWDT_MASK 0X00001000U
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/* Register: PMU_GLOBAL_ERROR_SRST_DIS_1 */
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#define PMU_GLOBAL_ERROR_SRST_DIS_1 ( ( PMU_GLOBAL_BASEADDR ) + 0X00000570U )
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#define PMU_GLOBAL_ERROR_SRST_DIS_1_LPD_SWDT_MASK 0X00001000U
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/* Register: PMU_GLOBAL_ERROR_EN_1 */
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#define PMU_GLOBAL_ERROR_EN_1 ( ( PMU_GLOBAL_BASEADDR ) + 0X000005A0U )
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#define PMU_GLOBAL_ERROR_EN_1_LPD_SWDT_MASK 0X00001000U
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/* rpu */
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@ -503,8 +522,8 @@ extern "C" {
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/**
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* Definition for WDT to be included
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*/
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#ifdef XPAR_XWDTPS_0_DEVICE_ID
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/*#define XFSBL_WDT_PRESENT*/
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#if (!defined(FSBL_WDT_EXCLUDE) && defined(XPAR_XWDTPS_0_DEVICE_ID))
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#define XFSBL_WDT_PRESENT
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#endif
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/**
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@ -308,9 +308,9 @@ static u32 XFsbl_ProcessorInit(XFsblPs * FsblInstancePtr)
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static u32 XFsbl_ResetValidation(XFsblPs * FsblInstancePtr)
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{
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u32 Status = XFSBL_SUCCESS;
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#if 0
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u32 FsblErrorStatus=0U;
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u32 ResetReasonValue=0U;
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u32 ErrStatusRegValue;
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/**
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* Read the Error Status register
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@ -319,15 +319,16 @@ static u32 XFsbl_ResetValidation(XFsblPs * FsblInstancePtr)
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FsblErrorStatus = XFsbl_In32(XFSBL_ERROR_STATUS_REGISTER_OFFSET);
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ResetReasonValue = XFsbl_In32(CRL_APB_RESET_REASON);
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ErrStatusRegValue = XFsbl_In32(PMU_GLOBAL_ERROR_STATUS_1);
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/**
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* Add LPD_SWDT for r5
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* check if the reset is due to system WDT during
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* Check if the reset is due to system WDT during
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* previous FSBL execution
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*/
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/* WDT reset is missing in reset reason */
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if (((ResetReasonValue & CRL_APB_RESET_REASON_FPD_SWDT_MASK)
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== CRL_APB_RESET_REASON_FPD_SWDT_MASK) &&
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if (((ResetReasonValue & CRL_APB_RESET_REASON_PMU_SYS_RESET_MASK)
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== CRL_APB_RESET_REASON_PMU_SYS_RESET_MASK) &&
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((ErrStatusRegValue & PMU_GLOBAL_ERROR_STATUS_1_LPD_SWDT_MASK)
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== PMU_GLOBAL_ERROR_STATUS_1_LPD_SWDT_MASK) &&
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(FsblErrorStatus == XFSBL_RUNNING)) {
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/**
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* reset is due to System WDT.
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@ -353,7 +354,6 @@ static u32 XFsbl_ResetValidation(XFsblPs * FsblInstancePtr)
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*/
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END:
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#endif
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return Status;
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}
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@ -457,6 +457,11 @@ static u32 XFsbl_PrimaryBootDeviceInit(XFsblPs * FsblInstancePtr)
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{
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XFsbl_Printf(DEBUG_GENERAL,"In JTAG Boot Mode \n\r");
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Status = XFSBL_STATUS_JTAG;
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#ifdef XFSBL_WDT_PRESENT
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/* Stop WDT as we are in JTAG boot mode */
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XFsbl_StopWdt();
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#endif
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}
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break;
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@ -408,6 +408,11 @@ void XFsbl_FallBack(void)
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{
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u32 RegValue;
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#ifdef XFSBL_WDT_PRESENT
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/* Stop WDT as we are restarting */
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XFsbl_StopWdt();
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#endif
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/* Hook before FSBL Fallback */
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XFsbl_HookBeforeFallback();
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@ -99,6 +99,8 @@ u32 XFsbl_InitWdt()
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u32 Status = XFSBL_SUCCESS;
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XWdtPs_Config *ConfigPtr; /* Config structure of the WatchDog Timer */
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u32 CounterValue = 1;
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u32 RegValue;
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/**
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* Initialize the WDT timer
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@ -135,6 +137,16 @@ u32 XFsbl_InitWdt()
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*/
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XWdtPs_EnableOutput(&Watchdog, XWDTPS_RESET_SIGNAL);
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/* Enable generation of system reset by PMU due to LPD SWDT */
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RegValue = XFsbl_In32(PMU_GLOBAL_ERROR_SRST_EN_1);
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RegValue |= PMU_GLOBAL_ERROR_SRST_EN_1_LPD_SWDT_MASK;
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XFsbl_Out32(PMU_GLOBAL_ERROR_SRST_EN_1, RegValue);
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/* Enable LPD System Watchdog Timer Error */
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RegValue = XFsbl_In32(PMU_GLOBAL_ERROR_EN_1);
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RegValue |= PMU_GLOBAL_ERROR_EN_1_LPD_SWDT_MASK;
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XFsbl_Out32(PMU_GLOBAL_ERROR_EN_1, RegValue);
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/**
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* Start the Watchdog timer
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*/
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@ -216,7 +228,19 @@ void XFsbl_RestartWdt()
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*******************************************************************************/
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void XFsbl_StopWdt()
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{
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u32 RegValue;
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XWdtPs_Stop(&Watchdog);
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/* Disable LPD System Watchdog Timer Error */
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RegValue = XFsbl_In32(PMU_GLOBAL_ERROR_EN_1);
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RegValue &= ~(PMU_GLOBAL_ERROR_EN_1_LPD_SWDT_MASK);
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XFsbl_Out32(PMU_GLOBAL_ERROR_EN_1, RegValue);
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/* Disable generation of system reset by PMU due to LPD SWDT */
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RegValue = XFsbl_In32(PMU_GLOBAL_ERROR_SRST_DIS_1);
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RegValue |= PMU_GLOBAL_ERROR_SRST_DIS_1_LPD_SWDT_MASK;
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XFsbl_Out32(PMU_GLOBAL_ERROR_SRST_DIS_1, RegValue);
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}
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#endif /** end of WDT wrapper code */
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@ -77,6 +77,8 @@ extern "C" {
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#ifdef XFSBL_WDT_PRESENT
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u32 XFsbl_InitWdt();
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u32 XFsbl_ConvertTime_WdtCounter(u32 seconds);
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void XFsbl_StopWdt();
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void XFsbl_RestartWdt();
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#endif
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/************************** Variable Definitions *****************************/
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@ -113,6 +113,11 @@ u32 XFsbl_PartitionLoad(XFsblPs * FsblInstancePtr, u32 PartitionNum)
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{
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u32 Status=XFSBL_SUCCESS;
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#ifdef XFSBL_WDT_PRESENT
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/* Restart WDT as partition copy can take more time */
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XFsbl_RestartWdt();
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#endif
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/**
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* Load and validate the partition
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*/
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